GB1600874A - Electronic thermometer - Google Patents

Description

(54) AN ELECTRONIC THERMOMETER (71) We OMRON TATEISI ELEC TRONICS CO., a corporation organised and existing under the laws of Japan, of 10, Tsuchido-cho, Hanazono, Ukyo-ku, Kyoto, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an electronic thermometer, and particularly to an improved thermometer utilizing a microprocessor. This invention also relates to an improved thermometer for displaying the outptut from a temperature responsive transducer in a digital display particularly within a given temperature measuring range.

A conventional electronic thermometer needs a separate counter for comparison of temperature, holding of the highest temperature, or the like. This is disadvantageous since it results in a large volume of the electronic thermometer because of the large size of its counter. In addition, the electronic output from a temperature responsive transducer is precisely in proportion to a temperature within a predetermined temperature range though not as precise when out of said range. Therefore accurate readings may not be obtained if the output from the temperature responsive transducer is displayed on the digital readout when operating out of said temperature range. If no indication is proved when out-of-range, there is no way of knowing if the thermometer is in operation.

It is an object of the present invention to provide an improved electronic thermometer of relatively small-size.

According to this invention, an electronic thermometer comprises a bridge circuit having a temperature responsive transducer in a branch thereof for producing an unbalanced voltage with a predetermined polarity when a reference temperature is exceeded, a charge-and-discharge circuit including a capacitor connected to be charged by said unbalanced voltage, a microprocessor provided with a reference value corresponding to the reference temperature, counting means for counting a count equivalent to said reference value, and means for allowing the charge-and-discharge circuit to discharge if a temperature of the transducer is exceeding the reference temperature when the counting means counts to the counted value and an interrupt circuit for applying an interrupt signal to the microprocessor when the charge-and-discharge circuit discharges to a predetermined value, the microprocessor being provided with means for computing a temperature from the reference value and a value accumulated in a counting sequence starting when the discharging starts and ending when the interrupt signal is produced.

The preferred embodiment of the invention has a built in temperature display, the microprocessor including means for causing the computed temperature to be displayed thereon. In this embodiment, the computed temperature corresponds to the sum of the reference value and the accumulated value, this sum being related to the temperature in such a manner that it can be displayed directly as a temperature reading. The thermometer may also include means for causing a "high" or "low" sign to be displayed when the temperature is outside a predetermined range.

The interrupt point in the counting sequence varies in accordance with the time it takes for the charge-and-discharge circuit to discharge to a predetermined voltage, e.g.

zero. Because the counting is interrupted the possibility exists that the counted value on the interrupted point may be incorrectly read, and another possibility exists that the counted value at which the counting sequ ence recommences following interruption is miscounted on recounting. These erroneous counted values may be prevented by including a correction step as part of the temperature computation to correct the counted value in the counting sequence.

The invention will now be described by way of example with reference to the drawings, in which: Figure I is an electrical circuit diagram including a bridge circuit; Figure 2 is a graph illustrating the charging and discharging operation of the circuit of Figure 1; Figure 3 is a block diagram of one embodiment of the present invention; Figure 4 is a contents location diagram of the RAM of Figure 3; Figures 5A, 5B, 6 and 7 are flow charts of operations performed by the microprocessor of the preferred embodiment, and Figure 8 is a front elevation of a thermometer in accordance with the invention.

At first, an embodiment of an electronic thermometer utilizing a microprocessor will be explained referring to the drawings, Figure 1 to Figure 4, Figure SA and Figure SB.

Figure 1 is an electronic schematic circuit showing a construction of an embodiment of a bridge circuit. a charge-and-discharge circuit, and an interrupting circuit used in the present invention. In Figure 1, 201 shows a bridge consisting of a temperature responsive transducer 202 and resistors 203, 204 and 205. and a battery (or other power source) 206 connected to input terminals 207 and 208 of the bridge 201. The input of an operational amplifier 211 is connected to the output terminals, 209. 210. Capacitor 212 is connected between output terminal 209 and the output terminal of the amplifier 211. The positive terminal of capacitor 212 is connected to a microprocessor 214 through a resistor 213.Numeral 215 is a transistor for detecting a zero point having a base connected to the negative terminal of capacitor 212. a grounded emitter and a collector connected through a resistor 217 to a voltage source 216. The collector is also connected to the microprocessor 214. Num erals 215, 216 and 217 constitute an inter rupt circuit outputting an interrupt signal.

The operation of Figure 1 will be ex plained as follows. A body temperature is transmitted to the temperature responsive transducer 202 having a resistance value which varies with temperature. As long as the temperature is not over 30"C, the polarity of the voltage of the output termin als 209, 210 of the bridge 201 is reversed with respect to the polarity for charge of the capacitor 212 and the capacitor 212 is not charged owing to the interposed operational amplifier 211. When the temperature of the temperature responsive transducer 202 is over 30"C, the polarity of the output voltage on the output terminals 209 and 210 is oriented in a predetermined manner and capacitor 212 is charged.For this purpose the bridge 201 should be balanced when the temperature of the temperature responsive transducer 202 is 30 C. As described hereinafter, the microprocessor 214 counts to 200 at a count area (CR) (hereinafter "count register") and thereafter detects whether the temperature of the temperature responsive transducer 202 is over 30"C, in other words after every 200 counts a predetermination is made as to whether the capacitor 212 is charged. An operation after the count 200 is reached will be described below. If at this point the temperature is over 30"C, the microprocessor 214 generates a discharge instruction and discharges the charge on the capacitor 212 through resistor 213.A MOS transistor (not shown in the drawings) for discharging the capacitor is included in the microprocessor 214 and conducts in accordance with a microprocessor instruction to discharge. When this instruction is received the charge on capacitor 212 is discharged through resistor 213 and the MOS transistor. When the charged voltage of the capacitor 212 drops to a predetermined value (zero voltage in this embodiment), transistor 215 produces a signal introduced into the microprocessor 214 as an interrupt signal. The microprocessor 214 interrupted by the interrupt signal causes the MOS transistor to become nonconductive and the capacitor 212 to begin to charge again. The time at which the discharge ends (and the interrupt occurs) is prior to the time at which the counting register (CR) counts to 200. The counting operation and discharge time are described in accordance with Figure 2.Referring to Figure 2, the count register CR counts 200 during the time intervals t0 to t1, and tl to t2, respectively. Every count to 200 the microprocessor 214 detects if the capacitor 212 is charged. When the capacitor 212 is charged at the time point t2, the microprocessor 214 allows a charge-and-discharge circuit (211, 212, 213 and microprocessor MOS transistor in Figure 1) to discharge. As described above, the capacitor 212 is charged by an output voltage of a predetermined polarity between the output termin als 209 and 210 produced by the tempera ture of the transducer being over 30"C.

Accordingly, the charged voltage is propor tional to an exceeded value over 30"C of the temperature responsive transducer. For ex ample, at the temperature 36.5"C of the transducer 212, an unbalanced voltage of the bridge 201 produced by the temperature rising 6.5"C becomes a charged voltage for the capacitor 212. By setting proper resist ance values for resistor 213 and the MOS transistor, a counted value of the counting register (CR) may be fixed at 65 during the period from a point of the capacitor beginning a discharge to the point where the transistor for zero point detection begins to produce an interrupt signal, namely from the time point t2 to the time point t3.In this case, the counting value from start to end of discharge represents the charged voltage of the capacitor 212 which is the output voltage of the bridge 201 produced by the temperature of the transducer 202 and exceeding 30"C by 6.5"C. On the condition that the temperature of the transducer 202 is 35"C, the counting register (CR) counts 50 in accordance with the temperature 5"C.

When the discharge ends at the time point t3 shown in Figure 2, the microprocessor 214 allows the charge-and-discharge circuit to again start a charge, and capacitor 212 begins an interrupted sequence which consumes an amount of time corresponding to 100 counts of the count register, the latter being disabled during the interrupt sequence. After executing the interruption sequence, the microprocessor 14 instructs a continuation of the counting in the counting register. The counting register (CR) begins counting where it left off when the interrupt signal was received, i.e. it counts from 65 to 200 when the temperature is 36.5"C since it has already counted 65 prior to the generation of the interrupt signal.At a time point t4 ending this counting, the sum total of the counting value (200) of the counting register (CR) and a count value caused by the interrupt signal whereby, in the processing of the interrupt instruction, a time equivalent to 100 counts of the counting register (CR) is consumed is 300. The microprocessor 214 at the time point t4 again detects whether the capacitor 212 is charged or not, instructs a discharge if charged, and repeats this operation as many times as appropriate.

During this repeat operation the temperature of the transducer 202 is assumed to rise to the same temperature as a body temperature for measurements. Until then, every 300 of the sum total count steps as shown at the time points, t4, t6, t8 in Figure 2, the sum of reference value of 300 and the counted value of the counting register (CR) at the end of the capacitor discharge is computed. The reference value of 300 is the value corresponding to the temperature of 30"C. If the temperature of the transducer 202 at the time point t2 is 36.5"C, the counting value of the counting register (CR) at the time point t3 is 65 and 36.5"C. is computed by adding 300 to 65 and converting the value of 365, into temperature, i.e 365 becomes 36.5"C.

While the temperature of the transducer 202 is rising to body temperature, for example, the counting value of the counting register (CR) a current interrupt time point increased more than at the previous interrupt time point. The counting value for instance at the time point t5 is larger than at the time point t3. When the body temperature is reached however, the counting value of the counting register (CR) remains constant when capacitor discharge is completed.Provided that the sum total of 300 and the counting value from start to end of the discharge is memorised every time, the sum total of this is compared with the sum total of the last time, and if the sum total of this time is found to be not larger than the sum total of the previous time computed, the temperature transducer 202 is regarded as being equal to the body temperature and the sum total value at that time is converted into temperature and indicated on a display.

The above mentioned operations performed by the microprocessor will now be described with the aid of flow charts.

First, referring to Figure 3, structures internal to the microprocessor are described. Numeral 221 designates the microprocessor which contains registers F, T, A and B, an instruction register IR, a logic operation circuit ALU, a program counter PC, a +1 circuit and other conventional microprocessor structures, e.g. clock, address buffer, decoder, bus lines etc. The microprocessor 221 is connected with a read-only memory (ROM) and random access memory (RAM) via conventional address and data bus hnes.

Referring to Figure 4, an address for the RAM is fixed by BR (0 to 9, A to F) an an axis of abscissas and MR (0 to 7) on an axis of ordinates.

BR on the axis of abscissas is decided by the B register, and the axis of ordinates is decided by a program. In Figure 4 CT, LC are counters, XR is a display register, CR is a counting register, DR is a data register, F, A, B are registers.

Figure 5A and Figure SB are flow charts.

There are some skipped numbers of steps or inquiries.

In a step 1, the RAM is reset. In a step 2, the microprocessor instructs the counting register CR to count 200. In a step 3, every 200 counted by the counting register CR adds +1 to the data in a counter CT. An inquiry step 4 judges if a data of the counter CT reaches 16. If NO, an inquiry step 5 judges if a temperature is 30"C or less. If YES (30"C or less) a step 6 allows a register F2 to set and an inquiry step 7 judges if a temperature has been displayed.

As it will be understood from the following description, if the temperature is 30"C, or less except after it is once over 30"C for example, both data in DR and XR at the time point tl are zero. Returning to step 2, until the counter CT is incremented by +1 and data in the counter CT reaches 16, the process flows from inquiry step 4 to inquiry step 5. For instance if it is at the time point t2, the temperature of the transducer 202 has already reached 30"C. Then the result of the decision in inquiry step 5 if a temperature is below 30"C should be NO. Then in step 10 the register F2 is reset, and in step 11 a discharge instruction is given from the microprocessor to the charge-and-discharge circuit, and in step 12 INTE is set to "1".By INTE being set to "1" the microprocessor is conditioned to accept an interrupt instruction. Then in step 2 the counting register CR continues to count, but when the chargeand-discharge circuit discharges down to a predetermined value (in this embodiment it discharges down to zero voltage), the transistor 15 for zero voltage detection in Figure 1 supplies an interrupt signal, this signal (INTE) is supplied to the microprocessor, the step flows to step 13, and the counting in CR in step 2 is interrupted at that instant.

This time point corresponds to t3 in Figure 2, for example. When in step 13 a charge instruction is applied to the charge-anddischarge circuit, and the capacitor again starts to be charged.

In step 14 the data in the registers A. F, B is transmitted to the RAM and in step 15 the data in the counting register CR is applied to the data register DR. For example, if a counted value of the counting register at the time point t3 is 65. this counted vaue 65 is entered into the data register DR. In step 16, the data in the data register is corrected.

If the counted value in CR supplied by an interrupting signal INT is, for example, at the moment of transition from 19 to 20, 9 at the least significant digit turns to 0, the data in the counting register CR at the time point when the second digit is not yet changed to 2 is transmitted to the data register DR, the data in DR becomes 10. To take care of this problem, the data in DR has to be corrected to 20. After the data in DR is corrected in step 16, the register F2 is reset in step 17, the counter LC is incremented by + 1 in step 18. In the counter LC, the number of occurrences of the charge-and-discharge operation is counted so that the operation of charging and discharging in the charge-anddischarge operation is counted so that the operation of charging and discharging in the charge-and-discharge circuit is repeated 15 times.In inquiry step 19. the condition whether LC= 15 is judged. If a NO response is obtained, the same number of steps is arranged to be consumed by the program in step 20 as in the case of the routine following a YES response. This is designed so that an equivalent step number to 100 in the counting register CR is consumed in any routine during the term from an interrupt instruction status to a status out of the interrupt instruction. In step 21, F2 is set. In step 22 and step 23, a number of steps is counted. In steps 22 and 28 a predetermined step number is consumed for the same purpose as in step 20. Data transmitted into the RAM is read into the registers A, F, B in step 24, and the process is returned to step 2 in step 25. Upon returning to step 2, the counting register CR restarts the counting which has been interrupted by the interrupt signal INT.For example, if at the point the interrupt instruction is received 65, has been counted, the remainder value of 135 is counted until the value 200 is counted, and on counting to 200, the processing sequence proceeds to step 3 to add + 1 to the data in CT. After the time point t2 in Figure 2, the operations from step 2 to inquiry step 5 and from step 10 to step 25 are repeated. Upon repeating this operation 15 times the condition LC=15 is reached in step 18 and a YES response to inquiry step 19 causes the process to move to inquiry step 26 enquiry step 26 checks if DR 20. In this embodiment, however, a measurement is regarded as impossible when the temperature is below 32"C or above 43"C, and an underrange or overrange signal is displayed.

If a YES response for the inquiry DR 20 is obtained a check is made in inquiry step 27 if DR 130. A YES response in step 27 causes the addition of 300 to DR in step 28, then the condition XR DR is checked in inquiry step 29. The register XR should be loaded by the data in the data register DR as described hereinafter and in the present case it is loaded by the former data in the register DT. When LC=15 is first obtained, data in the register DR is not yet entered into the register XR and a response to step 29 should be NO. Then proceeding to step 30, the data in the data register DR is entered into the register XR, in step 23 a predetermined step is consumed, and the sequence proceeds step 2 via steps 24 and 25. The counter LC is reset on a count of 15 by step 40 described hereinafter, and recounts from 1.

While the above mentioned operations 2 to 5, 10 to 19. 26 to 30, and 23 to 25 are being repeated, the temperature of the temperature responsive transducer 202 rises to the body temperature to be measured.

Thereafter if DR 20 in inquiry step 26 is YES and DR 130 in inquiry step 27 is YES, a response to inquiry setp 29 should be XR=DR and the temperature is displayed in steps 49 and 50. This displays the value of DR plus 300, converting it into a temperature. In this embodiment a calculated value in step 28 divided by 10 is displayed as a temperature.

A NO response to inquiry step 26, which determines DR 20 results in a determination of an inquiry step as to whether a temperature has been displayed. A response that a temperature has been already displayed in step 50 shows that it has become once DR 20 and XR-DR (XR DR) and the temperature responsive transducer 202 has been removed from a body, while an instruction for temperature display is made in step 49 and a maximum temperature measured till then in step 50 remains on display. A response to inquiry step 31 that a temperature of the transducer 2 has yet to reach body temperature and further rising is predicted. Since there may be, however, a case of a measured temperature below 32"C, the sequence is advanced to step 21, where it sets F2 and returns to step 2 through steps 22, 23, 24 and 25.

A NO response to inquiry 27 to determine DR 130 shows that the temperature of the transducer 202 has already been over 43"C and is outside a precise temperature measurement range. An instruction for "H" is made in step 32 and "H" is displayed in step 50.

If there is a NO response in inquiry step 26 and the sequence returns to step 2 through steps 21 to 25 on a NO response to inquiry step 31, a further if there is a NO response to inquiry 47 to determine if CT=16, inquiry 5 determines if the temperature 30"C. The continuing operation to step 10 will be repeated if a NO response is obtained to inquiry step 5. If the response to inquiry 5 is YES, F2 is set in step 6, inquiry step 8 determines if a temperature has already been displayed. If a temperature has not been displayed, the temperature of the transducer should be rising and the sequence should return to step 2.If the temperature has been already displayed, the temperature of the transducer 202 should be lowered by being removed from a body to a lower temperature than the former measured value, so that a maximum temperature so far is displayed in step 50. In the above operation, a response of CT=16 in inquiry step 4 leads to step 33 and resets the counter CT, and inquiry step 34 determines of F2=1. If at that time the temperature is below 30"C or LC does not yet equal 15, F2 is set in step 6 or 21 and F2=1 exists, so that an instruction for 35 and "L" is displayed in step 36. Then in step 37, +1 is added to the contents of the counter CT. On counting up 576 during one second passes in CT the LC register is reset in step 40, the CT counter is reset in step 41, and the sequence is returned to step 2.A response to inquiry step 34 that F2 is not set gives an instruction to display data entered into the display register XR at a temperature in step 42 and proceeds to the routine 36, 37, 38 to display the data "a temperature" for one second in the same manner as a display "L".

As will be apparent from the foregoing description, in this case "L" is displayed for one second until over 32, during which period the temperature is rising; any data is not displayed if CT has not yet counted up to 16 in inquiry step 4 (1.5 second in this embodiment). A temperature exceeding 32"C is displayed for one second, and then a blank term of 1.5 second without any display, so that a flashing display is produced. If the temperature drops below 32"C after exceeding 32"C, or exceeds 43"C. the maximum temperature during the measurement period which is entered into the register XR or "H" is respectively continuously displayed.

Figure 8 is an elevation of an electronic thermometer. 800 is the electronic thermometer, and numeral 801 is its display. In Figure 8, a number 36.5 (i.e. a temperature) is shown; other temperatures will, of course, be displayed when other temperature measuring ranges are used. In a portion 802 of the display, "H" or "L" will be displayed when the temperature is over range or under range.

Although in this embodiment "H" or "L" are displayed to indicate out of range measurements, other alarm means such as a sound are possible.

Now referring to Figure 6, an operation to count 200 in CR in step 2 of the flow chart shown in Figure 5A will be described.

When, in step 2 (Figure 5A) an instruction from the microprocessor is given to the counting register CR to count 200, as shown in Figure 6, in step 51, a numerical value of 7 is entered into the register B, in step 52 a numerical value of 7 is entered into the register A, in step 53 the contents of the RAM at the address M(B.2) (the first column of CR in Figure 4) decided by a numerical value of the register V (being 7) and by the numerical value 2 is read out and is added to the data in the register A. At that time CR has not yet counted and the data is zero, and data in the first stage should be zero. In inquiry step 54 it is checked if a carry comes out of the register A. The registers A dna B have 4 bits respectively. Register A will not produce any carry since its contents remain 7 even if the data (zero) in the first stage if CR is incremented.Accordingly, there is a NO response to inquiry 54. The NO response adds 10 to the data in the register A in step 56 and feeds the data in the register A into the address M(B.2) in step 57. Then the data in the register B is 7, so that M(B.2) is an address in the first stage of CR in the RAM, the added data in the register A by 10 becomes 17, and the data in the register A becomes 1 by a carry 1 coming out. Then entering this into M(B.2) causes the first stage of CR to be incremented by 1. Then in step 58 the data in the register B is 6, the content of register B having been subtracted by 1, and in step 59 the data in the register A is set to 6. In step 60, the data at the address M(B.2), namely the data in the second step (zero at present) of CR, is read out, the read out value is added into the data in the register A, and then the added value is entered back into the register A.At this point the data in the register A remains at 6.

In step 61, the data in the fourth bit of the register F (F4) is added into the register A.

But 1 does not yet appear in this fourth bit and the data is zero. As a result the data in the register A remains 6, and a response to inquiry step 62 to check if any carry comes out from the register A is NO. In step 64 the data in the register A is increased by 10 (the data in the register A now being 0 since an addition of 10 is 16), in step 65 the data in this register A is entered into the address M (B.2). At that time the data in the register B is 6, so that the address M(B.2) is the second stage of CR. Accordingly the data in the second stage of CR remains zero. In step 66 the data in the register V is subtracted by 1 and in inquiry step 67 the condition F4=1 is checked. In the operation so far, 1 has been read into the first stage of CR in the RAM and a counting step to count 1 has been performed.

In step 51 the register B is again set to 7, in step 52 the register A is set to 7, in step 53 the data (1 in this embodiment) at the address M (B.2) (the first stage of CR) is read out and is added to the register A, and in inquiry step 54 a carry check is performed. At this point, no carry occurs since the data in the register A is now 8. The process moves to step 56 whereby 10 is added into the data in the register A (in this case the data in the register A becomes 2 by the carry 1 coming out), and in step 57 this value 2 is entered into the address M(B.2) in the RAM. Therefore in CR at the first stage becomes 2.The data in the register B is subtracted by 1 in step 58, 6 is entered into the register A in step 59. the data a M(B.2) (the data in the second stage of CR currently zero) is read out and is added into the register A in step 60. As a result, the data in the register A remains 6. In step 61, F4 is added into the register A but F4 is zero. so that a response to inquiry step 62 to check if a carry has come out is NO. In step 64, 10 is added into the register A (at that time a carry 1 comes out of the register A and the value of the register A is zero) and the value of the register A (zero) is entered into the address M(B.2) in the RAM (the data in the register B being 6). That is, zero is entered into the second stage of CR.Thereafter 1 is subtracted from the contents of the register B in inquiry step 66, the condition F4 = 1 is checked in in inquiry step 67 and since the response is NO, the process returns to step 51. In the above operations, the second stage of CR remains at zero, and the data in the first stage has become 2. That is, the operation to count 1.

After the data in the first stage of CR has become 9 by repeating the above counting operation 9 times, the data in the second stage being 0, in the tenth counting operation M(B.2) + A is 16, and by entering this into the register A the carry 1 occurs and the data in the register A becomes zero. Since a response to inquiry 54 is YES, F4 is set to 1 in step 55.In step 57, the data in the register A (zero) is entered into the address M(B.2) (the first stage in CR) and the data in the first stage in CR is zero. 1 is subtracted from the data in the register V which becomes 6 in step 58 the data in the register A is 6 in step 59, the data (zero) at the address M(B.2) is read out and is added into the register A in step 60, the data in the fourth bit F4 of the register F is added to the data in the register A, and the result entered into the data in the register A in step 61. This causes the date in the register A to be 7. A NO response to inquiry step 62 to determine if the carry is 1 proceeds to step 64 where the data in register A is added by 10. At that time a carry 1 occurs from the register A and the data in the register A becomes 1.This value is entered into the address M(B.2) (the second stage of CR since B is 6) in step 65. In step 66, only 1 is subtracted from the data in the register B and a NO response to inquiry step 67 which checks if F4 = 1, returns the process to step 51. In this counting operation, the data in the first stage of CR has become zero, while the data in the second stage has become 1, that is 10 has been counted in CR. In the counting steps from the eleventh to the 19th like the counting steps from the first to the ninth, the data in the first stage of CR progresses towards 9 from 1, one by one, while the sequence proceeds to step 56 from inquiry step 54, because of no carry coming out.

Since the data at the address M(B.2) (the second stage) is 1, the data in the register A becomes 7 in step 60, the data in the register A is incremented by 10, in step 64, and 7+10 = 17 is performed so that the carry 1 comes out and the data in the register A becomes 1. Then in step 65, the data at M(B.2) is set to 1, so that in the operation from the eleventh to 19th counting cycles the numerical value at the first stage of CR is added one by one, while the numerical value in the second stage remains 1. In the 20th counting cycle, the data in the first stage in CR has been 9 already, so that inquiry step 54 produces carry 1, F4 is set to 1 in step 55, the data in the register A turns to 0, and in step 57 the data at the address M(B.2) (the first stage of CR) of the RAM is set to zero.The data in register A is set to 7 in step 60 and to 8 in step 61, so that in step 64, A + 10 becomes 18. a carry 1 coming out causes the data in the register A to be 2, this 2 is then entered into the address M(B.2) (the second stage of CR) in step 65, and the sequence will return to step 51. Accordingly the second stage of CR is set to 2, the first stage of CR to zero and the counting value in CR becomes 20.

When the above counting operations have been repeated 99 times, both the second and the first stages are at 9. In the 100th counting cycle operation, M(b.2)+A is 16 in step 53. A carry 1 comes from register A, the data in register A returns to zero. a YES response to inquiry 54 makes F4 = 1 in step 55, in step 57 a zero is entered into M(B.2t (the first stage of CR). in step 60 M(B.2)+A is 15, in step 61 A+F4 is set to 16, so that a carry 1 comes from the register A and the data in the register A returns to zero.

Thereafter, a response to inquiry step 62 is YES, F4 is 1, and in step 65 a zero is entered into M(B.2) (the second stage of CR). A response to inquiry step 67 is YES and F1 is set to 1 in step 68. The stage F1 = 1 shows the counting value in CR has reached 100 after the operation to count 1 have been repeated 100 times.

The sequence after F1 is set to 1 proceeds to step 69. The operations from step 69 to inquiry step 85 are wholly equivalent to the operations from step 51 to inquiry step 67.

When CR counts up 100, F4 will be 1 in step 81 and a YES response to inquiry step 85 will appear. Then CR will count 200 in total, and the sequence will return to step 3 as shown in Figure 5-1.

As it will be understood from the above embodiment as shown in Figure 6, CR counts from 0 to 100 from step 51 to inquiry step 67, so that the number of steps to count 1 for the above counting cycle may be 15. If CR counts from 0 to 200, the number of steps needed to count 1 for the above counting will be about twice as many as in this embodiment. From step 69 to inquiry step 85, CR further counts from 0 to 100 and the number of steps needed to count 1 for the above term is 15 as in the case from step 51 to inquiry step 67. This may be about half of the number of steps compared with simply counting from 0 to 200, since in this case 100 is counted from step 51, to inquiry step 67 and a further 11 is counted from step 69 to inquiry step 85 making a total of 200.

The number of steps required to count 1 from step 69 to inquiry step 85. As described counting from step 69 to inquiry step 85 is a count which occurs after CR counts 100 and F1 is 1, and is an operation to count from the value 100 to 200.

Referring now to Figure 7, the operation for the correction performed in step 16 will be described. After an interrupt signal INT is viewed in step 2 in Figure 5-1, the step 13 produces a charge signal into the chargeand-discharge circuit in step 14, the data in the registers F, A, and B is fed to the register F, A and B of the RAM and in step 15 the data in CR are entered in DR.

Numerals 90 to 111 marked beside each block in Figure 7 show each step number or inquiry step number as was done in Figures 5A, 5B and 6. First, in step 90 a value of C which decides an address (abscissa) in Figure 4 is entered into the register V. C is a numerical value corresponding to the abscissa of C in Figure 4 which, in this embodiment is 12. In step 91, the data at the address M(C O) (the address of the register B in the RAM shown in Figure 4, into which the data in the register B is transported in step 14) is read out and is entered into the register A. In step 92, the data in the register V is set to C +1. This value is 13. In step 93, the data at the address (D.O) of the RAM (the register of the RAM shown as A) is logically negated and is entered in the register A.In step 94 the data in the register A is logically negated and is entered in the register B, and the data in the register B is logically negated and is entered in the register A. This means that the data in the registers A and B and which have been stored in the RAM in step 14 by an interrupt signal have been returned to the registers A and B.

Inquiry step 95 determines if B=6. As shown in Figure 6, the data in the register B is set to 7 in step 51, to 6 in step 58 and to 5 in step 66. Therefore if there has been a response of B=6, it means that during the sequence from step 57 to step 65 in Figure 6, counting CR has been interrupted and a counting value at that time in CR has been entered into DR. The data in the register B is set to 5 in step 66. Since the data in the register B is set to 5 when in step 65 M(B.2) - A is performed in other words, the second stage of CR may be incremented by 1 if F4 = 1 in step 61 - a fact that a value in the register V is 6 shows counting in CR has been interrupted before step 65. When the first stage of CR is incremented by 1 in step 57, the value in the register B is set to 6.

Recounting the uncounted counts in CR after interruption must start from 51 in Figure 6 before which the data in the first stage of DR should be decremented by 1.

Upon response B=6 to inquiry step 95, in step 96 the register B is set to 7, in step 97 the register A is loaded with F (for example, the value 15 in Figure 4) and in step 98 M(B.5)+A is performed and the result stored in A. Since B=7, M(B.5) is the address in the first stage of DR as shown Figure 4. Unless the data at the address M(B.5) is zero, a carry 1 appears whenever M(B.5)+A is entered into register A and the data in register A becomes a value subtracted by 1 from the data at the address M(B.5). For example, if the data at the M(B.5) (the first stage of DR) is 1, M(B.5)+A=16 since A=15. This is entered into register A so that carry 1 is produced and the data in register A becomes zero. Or if the data at M(B.5) is 15 and M(B.5)+A is entered into register A, carry 1 appears and the data in register A will be 4.In this manner, upon a YES response to inquiry step 99 to determine if carry 1 occurs, the data in register A is entered into M(B.5).

Accordingly, the data at M(B.5), namely the data at the first stage of DR, is subtracted by only 1. This is a correcting operation to subtract 1 from DR, since counting in CR is interrupted after +1 is added to CR in step 57 and the counted value in CR at that time has been brought once to DR. The data in register B is subtracted by only 1 in step 102. Inquiry step 103 determines if Fl equals (F1=l). A NO response to inquiry step 103 when CR has not yet counted to 100 leads to inquiry 107 to determine if B=5, and a NO response to inquiry 107 because of B being 6 in this case leads to step 17.

In the above operation, if carry 1 is not obtained in inquiry step 99 - that is, the data at the address M(B%5) is zero - the first stage of CR is zero, indicating that counting in CR before 1 is added to the second stage has been interrupted. The data in CR is then fed to DR. Accordingly, the first stage (in this case) of CR remains zero and the second stage in DR is corrected to 9 and counting in CR is restarted, a counting operation should again be made from step 51.

To perform this correction. the processing sequence proceeds from inquiry step 99 to step 100 where 10 is added to register A.

Since the data in register A is F=15 so far, the data in register A becomes 9 when 10 is added to it. This value in register A is entered into M(B.5) in step 101. Then the data in the first stage of DR is set to 9. The data in register V is subtracted by only 1 in step 102, the condition F1=1 is determined in inquiry step 103, a NO response here leads to inquiry step 107 and thence to step 17 after ending a correction operation since Bf5.

In the above case, if F1 = 1 in inquiry step 103, it shows that CR has already counted 100. Then register V is set to 5 in step 104, register A is set to 1 in step 105, the address M(B.5) is set to the numerical value 1 in step 106. The address M(B.5) is the third stage of DR in Figure 4, and has a 1 entered therein from register A. After that, the process continues to step 17 in Figure 5-2.

A NO response to inquiry step 95 to determine if B=6 leads to inquiry step 103.

The condition BW6 and B=7 indicates that the counting step in CR is interrupted prior to step 57 where in the interrupted step the first stage of CR is not incremented by 1. If B=5 however, this means that it has been interrupted in the steps following step 65 and the second stage of CR is, in this case, incremented by 1. If Bt6 the process moves to inquiry step 103 to determine if F1=1, and a NO response to this inquiry causes a determination as to whether B=5 to be made in inquiry step 107. If B=5 is not incremented by 1, it should be B=7, the first stage of CR is not incremented by 1, and further the second stage is not incremented by 1. Therefore, no correction is necessary and the sequence proceeds to step 17 in Figure 5-2 from inquiry 107.

When B is not 6 in inquiry step 95 and B is 5 in inquiry 107, the condition F4=1 is determined in inquiry step 108. If F4+ 1 correction is not necessary, and the sequence proceeds to step 17 in Figure SB from inquiry 108.

If F4 is 1 and a response to inquiry 108 is YES, it means that the counted value in CR has reached 100. In other words, the counted vaue in CR is incremented from 99 to 100, and is then stopped at the time point when the data in the first and the second stages are zero. Therefore, the data in the third stage of DR should be 1. Accordingly in step 109 register B is set to 5, in step 110 register A is set to 1, and in step 111 the value in register A is entered into the RAM at the address M(B.5). Then the data in register B is 5, the address M(B.5) of RAM is the third stage of DR in Figure 4, and then in 111 the third stage of DR is set to 1. The sequence proceeds from step 111 to step 16.

If F1 is 1 in inquiry step 103, in step 104 register B is determined as being set to 5, in step 105 register is set to 1 and in step 106 the 1 in register A is entered into the RAM at the address M(B.5). Since the address M(B.5) is the third stage of DR, in step 106 the third stage of DR is set to 1. Thereafter, the sequence proceeds to step 16 in Figure 5-2.

The above description is based on steps from step 51 to the inquiry step 67 or step 68, but step 69 to inquiry step 85 correspond to step 51 to inquiry step 67, respectively.

Therefore, when counting in CR is interrupted between step 69 and inquiry step 85, a correcting operation is done in the same manner as when an interruption occurs between step 51 and inquiry step 67.

However, F1 is usually 1 between step 69 and inquiry step 85. Accordingly, there is always a YES response to inquiry step 103 in this case, and the third stage of DR is set to 1.

As understood from the above descrip tion, the present invention provides the following operations: When a point where counting in CR is interrupted by an interrupt signal while the data in register B is 7 -- namely, before the first stage of CR is incremented by 1 in step 57 -- the data in DR will not be corrected.

When the data in the register B is 6 after the data in the first stage of CR has been incremented by 1 in step 57 and before the data at the second stage of CR is incremented by 1 in stage 65 -- the data in the first stage of DR is decremented by 1 unless it is zero, or is corrected to 9 if it is zero.

When the value of register B is 5 and the data at the second stage of CR has been incremented by 1 -- the third stage of DR will be set to 1 if F4 has been 1, or will not be set to 1 if F4 has not been 1. When an interruption occurs between step 69 and inquiry step 85, an equivalent correction to that described above will be made, and a correction will occur to change the data in the third stage of DR to 1 because of F1 being 1. When counting in CR starts again after an interruption, the counting will start from step 51 or step 69 if over 100 counted.

Then if an interruption occurs after 1 is added to the first stage of DR, this 1 is cancelled. If the first stage of DR is set at zero and the second stage is not yet incremented by 1 when a count value CR is exceeding 9, the first stage DR is set to 9.

When an interruption is made at the point when the counting value in CR is over 99 and just 100, the data in the third stage of DR is corrected to 1. In this manner, a counting value in DR restarting after the interruption occurs can be corrected to a proper value.

WHAT WE CLAIM IS: 1. An electronic thermometer comprising: a bridge circuit having a temperature responsive transducer in a branch thereof for producing an unbalanced voltage with a predetermined polarity when a reference temperature is exceeded; a charge-and-discharge circuit including a capacitor connected to be charged by said unbalanced voltage; a microprocessor provided with a reference value corresponding to the reference temperature, counting means for counting a count equivalent to said reference value, and means for allowing the charge-anddischarge circuit to discharge if a temperature of the transducer is exceeding the reference temperature when the counting means counts to the counted value; and an interrupt circuit for applying an interrupt signal to the microprocessor when the charge and discharge circuit discharges to a predetermined value; the microprocessor being provided with means for computing a temperature from the reference value and a value accumulated in a counting sequence starting when the discharging starts and ending when the interrupt signal is produced.

2. A thermometer according to Claim 1 including a temperature display, the microprocessor having means for causing the com- puted temperature to be displayed thereon.

3. A thermometer according to Claim 1 or Claim 2 including a ROM and a RAM, both connected to the microprocessor.

4. A thermometer according to any preceding claim wherein the microprocessor is connected to perform a detecting sequence for detecting a temperature over the reference temperature, the charge-and-discharge circuit being responsive to a detection output produced in the detecting sequence as a discharge signal.

5. A thermometer according to any preceding claim wherein the microprocessor is responsive to the interrupt signal to interrupt the counting sequence and initiate an operation sequence to compute a temperature in accordance with the accumulated value.

6. A thermometer according to Claim 5 wherein the operation sequence comprises adding the reference value to the accumulated value to produce a summed value representing the computed temperature.

7. A thermometer according to Claim 6 having a temperature display, the microprocessor being connected to feed the summed value to the display.

8. A thermometer according to any of Claims 5 to 7 wherein the counting sequence of the microprocessor includes a first counting sequence for counting up from zero to a predetermined value less than the reference value, and a second counting sequence for counting up to the reference value from the said predetermined value, the number of steps in the first sequence being equal to that in the second sequence, each sequence counting a "1" value when executed.

9. A thermometer according to any of Claims 5 to 8 wherein the microprocessor is organised to perform a correction sequence as part of the operation sequence to correct a counted value in the counting sequence in response to a position of the counting sequence at this time of being interrupted by the interrupt signal.

10. A thermometer according to a any preceding claim wherein the microprocessor is provided with a counting area in a memory for storing the said accumulated value, the counting area being arranged for performing a count from the stored value up to the count equivalent to the reference value, the charge-and-discharge circuit being discharged when the count equivalent to the reference value is reached.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (15)

**WARNING** start of CLMS field may overlap end of DESC **. tion, the present invention provides the following operations: When a point where counting in CR is interrupted by an interrupt signal while the data in register B is 7 -- namely, before the first stage of CR is incremented by 1 in step 57 -- the data in DR will not be corrected. When the data in the register B is 6 after the data in the first stage of CR has been incremented by 1 in step 57 and before the data at the second stage of CR is incremented by 1 in stage 65 -- the data in the first stage of DR is decremented by 1 unless it is zero, or is corrected to 9 if it is zero. When the value of register B is 5 and the data at the second stage of CR has been incremented by 1 -- the third stage of DR will be set to 1 if F4 has been 1, or will not be set to 1 if F4 has not been 1. When an interruption occurs between step 69 and inquiry step 85, an equivalent correction to that described above will be made, and a correction will occur to change the data in the third stage of DR to 1 because of F1 being 1. When counting in CR starts again after an interruption, the counting will start from step 51 or step 69 if over 100 counted. Then if an interruption occurs after 1 is added to the first stage of DR, this 1 is cancelled. If the first stage of DR is set at zero and the second stage is not yet incremented by 1 when a count value CR is exceeding 9, the first stage DR is set to 9. When an interruption is made at the point when the counting value in CR is over 99 and just 100, the data in the third stage of DR is corrected to 1. In this manner, a counting value in DR restarting after the interruption occurs can be corrected to a proper value. WHAT WE CLAIM IS:

1. An electronic thermometer comprising: a bridge circuit having a temperature responsive transducer in a branch thereof for producing an unbalanced voltage with a predetermined polarity when a reference temperature is exceeded; a charge-and-discharge circuit including a capacitor connected to be charged by said unbalanced voltage; a microprocessor provided with a reference value corresponding to the reference temperature, counting means for counting a count equivalent to said reference value, and means for allowing the charge-anddischarge circuit to discharge if a temperature of the transducer is exceeding the reference temperature when the counting means counts to the counted value; and an interrupt circuit for applying an interrupt signal to the microprocessor when the charge and discharge circuit discharges to a predetermined value; the microprocessor being provided with means for computing a temperature from the reference value and a value accumulated in a counting sequence starting when the discharging starts and ending when the interrupt signal is produced.

2. A thermometer according to Claim 1 including a temperature display, the microprocessor having means for causing the com- puted temperature to be displayed thereon.

3. A thermometer according to Claim 1 or Claim 2 including a ROM and a RAM, both connected to the microprocessor.

4. A thermometer according to any preceding claim wherein the microprocessor is connected to perform a detecting sequence for detecting a temperature over the reference temperature, the charge-and-discharge circuit being responsive to a detection output produced in the detecting sequence as a discharge signal.

5. A thermometer according to any preceding claim wherein the microprocessor is responsive to the interrupt signal to interrupt the counting sequence and initiate an operation sequence to compute a temperature in accordance with the accumulated value.

6. A thermometer according to Claim 5 wherein the operation sequence comprises adding the reference value to the accumulated value to produce a summed value representing the computed temperature.

7. A thermometer according to Claim 6 having a temperature display, the microprocessor being connected to feed the summed value to the display.

8. A thermometer according to any of Claims 5 to 7 wherein the counting sequence of the microprocessor includes a first counting sequence for counting up from zero to a predetermined value less than the reference value, and a second counting sequence for counting up to the reference value from the said predetermined value, the number of steps in the first sequence being equal to that in the second sequence, each sequence counting a "1" value when executed.

9. A thermometer according to any of Claims 5 to 8 wherein the microprocessor is organised to perform a correction sequence as part of the operation sequence to correct a counted value in the counting sequence in response to a position of the counting sequence at this time of being interrupted by the interrupt signal.

10. A thermometer according to a any preceding claim wherein the microprocessor is provided with a counting area in a memory for storing the said accumulated value, the counting area being arranged for performing a count from the stored value up to the count equivalent to the reference value, the charge-and-discharge circuit being discharged when the count equivalent to the reference value is reached.

11. A thermometer according to any

preceding claim further comprising means for indicating that a temperature is not within a predetermined range.

12. A thermometer according to Claim 11 wherein the indicating means causes a display of a letter meaning high when the temperature is over the range or a letter meaning low when the temperature is below the range.

13. A thermometer according to Claim 11 wherein the indicating means causes a display of "H" when the temperature is over the range of "L" when the temperature range is below the range, the microprocessor including means for causing the display of measured temperature out of the said range.

14. A clinical thermometer according to any preceding claim.

15. An electronic thermometer constructed and arranged substantially as herein described and shown in the drawings.