GB1599075A

GB1599075A - Amorphous semiconductor memory device for employment in an electrically alterable memory

Info

Publication number: GB1599075A
Application number: GB17354/78A
Authority: GB
Original assignee: Burroughs Corp
Current assignee: Unisys Corp
Priority date: 1977-05-31
Filing date: 1978-05-03
Publication date: 1981-09-30
Also published as: US4115872A; DE2822264C2; NL184186C; BE862625A; DE2822264A1; JPS53148933A; FR2393398A1; FR2393398B1; IT1096139B; SE423654B; NL184186B; BR7803207A; JPS6331955B2; CA1124857A; SE7805554L; IT7823462A0; NL7804961A

Description

PATENT SPECIFICATION ( 11) 1 599 075

tn ( 21) Application No 17354/78 ( 22) Filed 3 May 1978 ( 19) o ( 31) Convention Application No 801773 ( 32) Filed 31 May 1977 in ( 33) United States of America (US) C ( 44) Complete Specification Published 30 Sep 1981 t ( 51) INT CL 3 H Ol L 45/00 S ( 52) Index at Acceptance H 1 K 1 DB 2510 2519 2521 2523 252 B 252 C 252 D 4 C 11 9 C 3 9 M 1 9 M 2 DB ( 54) AMORPHOUS SEMICONDUCTOR MEMORY DEVICE FOR EMPLOYMENT IN AN ELECTRICALLY ALTERABLE MEMORY ( 71) We, BURROUGHS CORPORATION, a corporation of the State of Michigan, United States of America, of Burroughs Place, Detroit, Michigan 48232, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by

the following statement: 5

BACKGROUND OF THE INVENTION

Field of invention

This invention relates to an electrically alterable read-only memory and more particularly to an amorphous semiconductor memory device cell for employment therein 10 Description of the prior art

Most semiconductor memory cells are volatile in the sense that they must be refreshed in order to maintain the data stored therein In the case of semiconductor memory latches, the cell is still volatile in the sense that data is lost should there be a power failure However, it 15 has been discovered that certain amorphous semiconductor materials are capable of being switched to and from a low resistance crystalline state which does provide a non-volatile memory cell Particular materials that may be employed are disclosed in the Ovshinsky U.S Patent No 3,271,591, the Neale U S Patent No 3,699,543 and the Buckley U S.

Patent No 3,886,577 A particular type of memory switching amorphous semiconductor 20 material is the tellurium based chalcogenide class materials which have the general formula:

Ge A Te BXCYD Such amorphous high resistance semiconductor material can be placed between a pair of 25 spaced apart electrodes such that the application to one of those electrodes of a voltage pulse above a given threshold produces a relatively low resistance filamentous crystalline path (set operation) A reset set of pulses of appropriate value and duration causes the crystalline path to return to the relatively amorphous state (reset operation).

The prior art designs of amorphous or ovonic memory switches have had a characteristic 30 threshold voltage VT which is high at the first operation and in early operating life and lower thereafter ("first-fire effect") or which declines continuously throughout the life of the switch Particularly, this decline is in response to repeated "reset" operations where the memory element is restored from its conducting condition to its high resistance condition.

However, there are instances where it appears that the device lasted through 106 set-reset 35 cycles where the threshold voltage was observed to have a minimum low value (between 5 and 10 volts) and was relatively invariant to additional write cycles.

It now appears that electromigration of the constituents of the memory material toward the different electrodes causes the steady decline in the threshold voltage In the above described materials, germanium is shown to migrate to the negative electrode and to 40 approach 50 % concentration there Similarly, tellurium migrates to the positive electrode.

This migration of material produces regions that are inactive in the switching process because their ratios of constituents are no longer appropriate The region where the ratio of constituents is appropriate for switching is thus reduced in effective thickness and the threshold voltage becomes low, similar to that of a much thinner layer 45 2 1 599 075 2 The migration of material also produces concentration gradients Diffusion then operates as a countervailing process, producing an equilibrium Thermal gradients may also contribute to the process.

The above referenced Buckley patent discloses an ovonic memory structure in which the threshold voltage decline is altered by placement of a tellurium layer between the positive 5 electrode and the amorphous memory material layer This alters the threshold voltage decline but doesn't eliminate it.

It is then an object of the present invention to provide an improved amorphous semiconductor memory device.

From one aspect the invention consists in an electrically alterable memory device 10 comprising:a positive electrode; a negative electrode; and a structure of memory material mounted successively inbetween said electrodes, which structure is formed of deposited first, second and third regions, said first region being 15 adjacent to said negative electrode, said third region being adjacent to said positive electrode, said second region being between said first and third regions; said second region being formed of a tellurium-germanium based chalcogenide which has higher electrical resistance in its amorphous state and lower electrical resistance in its crystalline state and can be switched from one state to the other upon application to said 20 electrodes of an electrical signal of appropriate value; said third region being formed of a material having a higher percentage of tellurium than said second region so as to be inactive to switching by said electrical signal, said first region being formed of material including tellurium and having a higher percentage of germanium than said second region so as to be inactive to switching by said 25 electrical signal.

From another aspect the invention consists in an electrically alterable memory device comprising:a positive electrode; a negative electrode; and 30 a structure of memory material mounted inbetween said electrodes, which structure is formed of successively deposited first, second and third regions, said first region being adjacent to said negative electrode, said third region being adjacent to said positive electrode, said second region being between said first and third regions; said second region being formed of a tellurium-germanium chalcogenide which has 35 higher electrical resistance in its amorphous state and lower electrical resistance in its crystalline state and can be switched from one state to the other upon application to said electrodes of an electrical signal of appropriate value; said third region being formed of a material having a higher percentage of tellurium than said second region so as to be inactive to switching by said electrical signal, 40 said first region being formed of material including tellurium and having a higher percentage of germanium than said second region so as to be inactive to switching by said electrical signal, the extent of said first region parallel to said negative electrode being sufficient to prevent direct contact between said second region and said negative electrode and the extent of said third region parallel to said positive electrode being at least as great as 45 that of said first region.

From yet another aspect the invention consists in a method of producing an electrically alterable memory device comprising the steps of:depositing on a substrate a first conductive layer to form a negative electrode; forming an insulating layer with an opening therein on said first conductive layer; 50 depositing a first memory layer through said opening on to said first conductive layer; depositing a second memory layer on to said first memory layer; depositing a third memory layer on to said second memory layer; and depositing a second conductive layer on said third memory layer to form a positive electrode; 55 wherein said second memory layer is formed of a tellurium-germanium based chalcogenide which has higher electrical resistance in its amorphous state and lower electrical resistance in its crystalline state and can be switched from one state to the other upon application to said electrodes of an electric signal of appropriate value, wherein said third memory layer is formed of a material having a higher percentage of tellurium than said 60 second layer so as to be inactive to switching by said electrical signal, and wherein said first memory layer is formed of a material including tellurium and having a higher percentage of germanium than said second layer so as to be inactive to switching by said electrical signal.

Methods of performing the invention will now be described with reference to the drawings, wherein: 65 3 1 599 075 3 Figure 1 is a cross-section of an amorphous memory device of the prior art;

Figures 2 to 4 are cross-sectional diagrams of various embodiments of the present invention; and Figure 5 is a curve of the threshold voltage variations of different devices as a function of the number of set-reset cycles 5 As was indicated above, the present invention employs an amorphous semiconductor material which is of the tellurium based chalcogenide class materials: Ge A Te BXCYD The X constituent may be antimony, bismuth, arsenic or others, while the Y constituent may be sulfur or selenium A preferred embodiment of the present invention employs the material Gels Te 8 I Sb 252 10 Ge 24 Te 72 Sb 252 may be employed in another embodiment.

An embodiment of prior art memory device which uses such a material is illustrated in

Figure 1 As shown there, the entire memory device 11 is formed as an integral part of a silicon substrate 12 Device 11 would normally be employed in an array having vertical and horizontal conductors for the random access thereof In Figure 1, one of these conductors is 15 the N+ region 14 in substrate 12 which forms a part of a rectifier made up by region 14, N region 15 and P region 16 This rectifier along with memory device 11 form the crossover point between the orthogonal conductors 13 and 14 where conductor 14 is the negative electrode.

Silicon chip 12 is provided with an insulating material 17 which maybe silicon dioxide and 20 in turn is provided with a plurality of openings 10 to initially expose the semiconductor material at those points where respective memory devices 11 are to be located An electrically conductive layer 18 is selectively deposited over the exposed portions of the silicon chip The amorphous semiconductor memory material 19 is then deposited by appropriate techniques over opening 15 To complete the memory device, crystalline 25 tellurium layer 20 is sputter deposited over the memory material and a barrier-forming refractory metal layer 21 is deposited over that before the electrically conductive metal layer 13 is formed As disclosed in the above referenced Buckley Patent, the material of layer 20 is purposely chosen to be tellurium so as to offset the tellurium migration towards the positive electrode during the set and reset cycles The material of layer 21 is chosen to 30 be a barrier to the migration of the material of layer 13 (e g: Al) As was indicated above, while this tends to alter the threshold voltage decline, it does not eliminate it The present invention is designed to provide a much more stable threshold voltage over a much longer lifecycle.

A general embodiment of the present invention is diagrammatically illustrated in Figure 35 2 As shown therein, the memory device is formed on an insulative layer 22 which may or may not be a semiconductor substrate as in the case of Figure 1 To complete the appropriate connections, conductor 24 is first deposited on insulator layer 22 to form a negative electrode Another insulative layer 27 is formed thereover with an opening 25 to receive the memory device At this point, the present invention departs markedly from the 40 prior art in that layer 28 is deposited which layer is a tellurium base chalcogenide, specifically germanium-tellurium with a proportion with the respective constituents of 1:1.

On top of this layer, the amorphous memory glass material 29 is formed and a tellurium based layer 30 is deposited over the memory glass layer Tellurium based layer 30 may contain up to 10 % germanium The second conductor 23 is then deposited over the device 45 to form the positive electrode In the embodiment of Figure 2, the amorphous memory glass layer 29 is composed primarily of germanium and tellurium with the amount of germanium ranging between 15 % and 33 % Although the second conductor 23 is in electrical contact with the edges of the layers 28 and 29, the configuration of the device is such that migration of the components of these layers leading to threshold voltage decline is 50 largely eliminated.

A specific embodiment of the present invention is illustrated in Figure 3 This device is similar in structure to the embodiment of Figure 2 except that a barrier conductor layer is formed over the entire memory device and insulative substrate In Figure 3, the device is again formed on suitable insulative substrate 32 which may be of a semiconductor material 55 Negative conductor 34 is then formed thereon and layer 38 is a composition of germanium tellurium in a ratio of approximately 1:1 and is selectively deposited Insulative layer 37 is then formed over the selectively deposited germanium tellurium layer 38 with openings 35 in insulator 37 at the locations of the germanium tellurium selective deposits The amorphous memory material 39 and the tellurium material 40 are then deposited selectively 60 so as to overlap opening 35 Of course, the respective layers 37, 39 and 40 may be deposited over-all and selectively removed Barrier conductor material 41 is then deposited over the entire memory device and positive conductor 33 is then formed It is to be understood that, while the positive conductor 33 is in electrical contact with the edge of the layer 39 through the barrier layer 41, nevertheless the arrangement is such that migration of components of 65 1 599 075 the layer 39 leading to threshold voltage decline is largely eliminated.

Insulative layer 37 of Figure 3 is a dielectric which may be chemically vapor deposited and may be patterned photolithographically in a manner to form respective openings 35 as "pores" With this method, layer 37 permits layer 38 to be very conductive, either because of the method of deposition or because of the thermal treatment after deposition; without 5 becoming a short circuit between layers 34 and 41.

The amorphous material 39 may be of the approximate composition ranging from Ge 15 Te 85 to Ge 33 Te 66 possibly with additives It also may be patterned photolithographically.

Layer 40 may be tellurium possibly with additives so as to be in conducting state at the 10 time of the first electrical test It may be patterned simultaneously with the amorphous material 39 The barrier conductor material 41 may be molydenum or Tilo W 90 High conductance conductor 33 may be aluminum or gold.

Another embodiment of the present invention is illustrated in Figure 4 This embodiment is similar to Figure 3 and will not be described in detail except to point out the germanium 15 rich material 48 overlaps opening 45 in the dielectric material 44 and amorphous memory material 49 Also, the tellurium rich layer 50 overlaps the selective deposited area of the germanium rich material 48 Once again the arrangement inhibits migration from the memory material 49.

While the embodiments of this invention, as described in detail above, utilize three layers 20 of material, each uniform in concentration within the layer as deposited, the use of layers of graded composition may also be useful Indeed, a structure consisting of one continuously graded layer may be optimum The use of multiple layers to approximate initially the continuously graded structure that results from operation of the device through many set-reset cycles is a convenience in fabrication of the device Use of multiple layers, 25 moreover, permits the separate heat treatment of the first layer or layers to establish it in a more or less conducting condition before operation.

More than three layers may also be used to more closely still approximate the continuously graded structure that results from operation through many set-reset cycles.

Comparison of threshold values of the present invention with the declining threshold 30 values of prior art devices is disclosed in Figure 5 which is a set of curves representing threshold voltage values as a function of the number of set-reset cycles Curve A represents the threshold value decline for a uniform amorphous material layer of the prior art It will be observed that this threshold value continues to decline until at least 106 set-reset cycles after which it appears to be invarient to additional cycles Curve B represents the threshold 35 voltage variation for prior art device such as the type disclosed in Figure 1 Here again, the threshold value is initially high and levels out after about 102 cycles after which it is relatively invarient.

As distinct therefrom, Curve C represents the threshold value stability of the present invention where the difference in percentage of constituents in the various regions of the 40 present invention approach that of what is observed in a standard amorphous memory device after 106 set-reset cycles It is observed that the threshold value although equal to the minimum low value observed by the other prior art devices starts out at this low value and is constant throughout the life of the device The magnitude of this minimum low threshold value can be adjusted by adjusting the thickness of the amorphous memory layer As has 45 been indicated above, the thickness of the amorphous material region in the prior art devices tend to be reduced by the constituent migrations to the respective electrodes.

Different embodiments of the present invention have been described above, which embodiments are a layered or graded structures each region of which has a different concentration of particular constituents of the amorphous memory material so as to 50 approach that structure which is achieved by a uniform amorphous material after many set-reset cycles The layers of regions closest to the positive electrode should be increasingly rich in tellurium while the layers closest to the negative electrode should be increasingly rich in germanium By appropriate adjustment of the number of layers and their concentration of constituents, one can obtain an amorphous memory device which has an uniform 55 threshold value throughout its life cycle Such a device is most desirable for use in an electrically alterable read-only memory.

While three embodiments of the present invention have been disclosed, it will be understood by one skilled in the art that variations and modifications may be made therein without departing from the scope of the invention as claimed 60

Claims

WHAT WE CLAIM IS:

1 An electrically alterable memory device comprising:

a positive electrode; a negative electrode; and a structure of memory material mounted inbetween said electrodes, which structure is 65 1 599 075 5 formed of successively deposited first, second and third regions, said first region being adjacent to said negative electrode, said third region being adjacent to said positive electrode, said second region being between said first and third regions; said second region being formed of a tellurium germanium based chalcogenide which has higher electrical resistance in its amorphous state and lower electrical resistance in its 5 crystalline state and can be switched from one state to the other upon application to said electrodes of an electrical signal of appropriate value; said third region being formed of a material having a higher percentage of tellurium than said second region so as to be inactive to switching by said electrical signal, said first region being formed of material including tellurium and having a higher 10 percentage of germanium than said second region so as to be inactive to switching by said electrical signal.

2 An electrically alterable memory device comprising:a positive electrode; a negative electrode; and 15 a structure of memory material mounted inbetween said electrodes, which structure is formed of successively deposited first, second and third regions, said third region being adjacent to said positive electrode, said first region being adjacent to said negative electrode, said second region being between said first and third regions; said second region being formed of a tellurium-germanium chalcogenide which has 20 higher electrical resistance in its amorphous state and lower electrical resistance in its crystalline state and can be switched from one state to the other upon application to said electrodes of an electrical signal of appropriate value; said third region being formed of a material having a higher percentage of tellurium than said second region so as to be inactive to switching by said electrical signal, 25 said first region being formed of material including tellurium and having a higher perentage of germanium than said second region so as to be inactive to switching by said electrical signal, the extent of said first region parallel to said negative electrode being sufficient to prevent direct contact between said second region and said negative electrode and the extent of said third region parallel to said positive electrode being at least as great as 30 that of said first region.

3 A memory device according to Claim 1 or Claim 2, wherein said third region is substantially tellurium.

4 A memory device according to any of the preceding Claims, wherein said first region is formed of approximately equal proportions of tellurium and germanium 35 A memory device according to any of the preceding Claims, wherein said second region is formed of Ge 15 Te 8 M Sb 252.

6 A memory device according to any of Claims 1 to 4, wherein said second region is formed of Gej 4 Te 725 b 252.

7 A method of producing an electrically alterable memory device comprising the steps 40 of:depositing on a substrate a first conductive layer to form a negative electrode; forming an insulating layer with an opening therein on said first conductive layer; depositing a first memory layer through said opening on to said first conductive layer; depositing a second memory layer on to said first memory layer; 45 depositing a third memory layer on to said second memory layer; and depositing a second conductive layer on said third memory layer to form a positive electrode; wherein said second memory layer is formed of a tellurium-germanium based chalcogenide which has higher electrical resistance in its amorphous state and lower 50 electrical resistance in its crystalline state and can be switched from one state to the other upon application to said electrodes of an electrical signal of appropriate value, wherein said third memory layer is formed of a material having a higher percentage of tellurium than said second layer so as to be inactive to switching by said electrical signal, and wherein said first memory layer is formed of a material including tellurium and having a higher percentage of 55 germanium than said second layer so as to be inactive to switching by said electrical signal.

6 1 599 075 6 8 An electrically alterable memory device substantially as hereinbefore described with reference to, and as illustrated in, Figures 2 to 4 of the accompanying diagrammatic drawings.

For the Applicants, 5 G.F REDFERN & COMPANY, Marlborough Lodge, 14 Farncombe Road, Worthing, West Sussex BN 11 2 BT 10 Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey 1981.

Published by The Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.