GB1597595A - Manufacture of semiconductor elements - Google Patents

Manufacture of semiconductor elements Download PDF

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Publication number
GB1597595A
GB1597595A GB25964/78A GB2596478A GB1597595A GB 1597595 A GB1597595 A GB 1597595A GB 25964/78 A GB25964/78 A GB 25964/78A GB 2596478 A GB2596478 A GB 2596478A GB 1597595 A GB1597595 A GB 1597595A
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Prior art keywords
ion
mask
produced
substrate
ion source
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GB25964/78A
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Funkwerk Erfurt VEB
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Funkwerk Erfurt VEB
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Description

PATENT SPECIFICATION
( 11) 1597595 ( 21) Application No 25964/78 ( 22) Filed 24 Jan 1977 ( 19) ( 62) Divided out of No 1 597 594 ( 31) Convention Application No 191181 ( 32) Filed 4 Feb 1976 in( 33) Dem Rep of Germany (DD) ( 44) Complete Specification published 9 Sept 1981 ( 51) INT CL 3 H Ol J 27/00 ( 52) Index at acceptance HID 10 14 A 14 C 44 ( 54) IMPROVEMENTS RELATING TO THE MANUFACTURE OF SEMICONDUCTOR ELEMENTS ( 71) We, VEB FUNKWERK ERFURT (formerly KOMBINAT VEB FUNKWERK ERFURT), of 50 Erfurt, Rudolfstrasse 47, German Democratic Republic, a corporation organised and existing under the laws of the German Democratic Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the follow-
ing statement:-
This invention relates to an apparatus which is suitable for the manufacture of a semiconductor element by a process in which there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one layer disposed thereon are produced Such a process is described and claimed in the complete specification of our co-pending patent application 2738/77 (Serial No 1597594).
In the manufacture of semiconductor components, it is known to use photolithographic processes for producing the structures; the layers to be structured are coated with a photoresist, subsequently exposed to light according to the desired structures, and developed In the developing process which follows, a locally confined region of the layer of photoresist is removed In these regions the layer disposed thereunder is subsequently removed by means of liquid etchants, either wholly or partially depending on the subsequent process step Depending on the technology applied, this procedure is repeated an appropriate number of times Besides semiconductor layers, the layers to be structured may be insulating or conductive.
Photolithographic processes have the disadvantage that, by reason of the wet processes required, uncontrollable contamination is caused which may result in unstable electrical parameters and a reduction in the yield.
A significant disadvantage resides in the fact that in the photolithographic processes there is a theoretical limit to the resolution imposed by the wavelength of the light used.
There are moreover known ion implanta 50 tion processes for the purpose of doping the entire area.
There is also known the process involving the writing ion beam (precision beam technology), which, however, is too time-con 55 suming on account of the high doses required for the purpose.
It is also known that, relative to unradiated oxide, silicon oxide which has been subjected to ion radiation has the property of differen 60 tial rates of etching which depend on the radiation dose and the quality of the oxide.
The object of the invention is to provide an apparatus suitable for carrying out a process which eliminates the disadvantages de 65 scribed, is capable of giving a higher yield and in which the wet processes required in photolithographic processes are avoided, which gives a higher resolution and thus a higher degree of integration coupled with 70 good reproducibility of the parameters, which enables the structuring of electrically conductive layers required in the manufacturing process for semiconductor structures to be performed non-photolithographically 75 and which, to a large extent, eleminates contamination.
According to the invention, there is provided apparatus for the manufacture of a semiconductor element by a process in which 80 there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one layer disposed 85 thereon are produced, said apparatus comprising a said ion source which is adapted for the extraction therefrom of an ion beam of high divergence, a system of apertures arranged to produce from said ion beam a 90 tn 1,597,595 partial beam of substantially homogeneous intensity, and a mask having a structure of which an image is to be produced, an ionoptical system and a holder for a said element, said mask being disposed between said ion source and said ion-optical system in the path of said beam of high divergence, and said ion-optical system being arranged to cause said beam to converge on to the semiconductor element, the arrangement being such that, in operation of the apparatus, said partial beam causes an image of the mask structure, reduced in size, to be produced on said substrate.
Preferably in apparatus according to the invention, the ion source is provided with a change-over device which makes it possible for the apparatus to be used with a variety of kinds of ions.
In apparatus according to the invention, a support for the mask may comprise means for changing masks and for the correct positioning of a mask For the purpose of producing a plurality of like structures on a semiconductor substrate, means may be provided in a target chamber for mechanically displacing said substrate, or a diverting system for the ion beam may be provided and so arranged that the ion beam may be reproducibly displaced.
The technical advantages of the process to be carried out by means of the apparatus according to the present invention reside in the fact that, in using the process, as compared with the known processes, non-photolithographic structuring of the electrically conductive layers is achieved Thus, it is possible, in connection with the non-photolithographic structuring of suitable silicon dioxide insulating and protective layers to perform, by using the process, a semiconductor manufacturing process which, as compared with known processes, is entirely nonphotolithographic.
As compared with known processes, a significantly higher resolution is also achieved, and thus a higher packing density and, by reducing the contamination, an improvement in the stability of the electrical parameters is made possible The thermal stressing as well as the requirements for accuracy of positioning of the exchangeable masks are smaller by a factor of 102 (area) as compared with a contact mask process, by reason of the 10-fold reduction produced by the object-glass Likewise the requirements concerning the manufacturing tolerances for the exchangeable masks are reduced by a factor of 10, as compared with the requirements for the quality of the image, i e 1 gm of tolerance in the accuracy of positioning of the mask corresponds, in the case of a reduction ratio of 1:10, to an image displacement of 0 1 gm.
The economic effects reside in simplification of the technical procedure, a significant increase in the periods of application of the masks as compared with conventional photographic stencils, as well as an increase in the yield 70 The present invention will now be explained in greater detail with reference to the following examples:
The insulating layers on the semiconductor surface which, as a rule, consist of silicon 75 dioxide, are bombarded, preferably with light ions, over a locally confined region, by means of the apparatus embodying the invention, which is in the form of an ion optical appliance, which will hereinafter be referred 80 to as an ion projector.
The ion projector defines a combination of a particle accelerator and an ion-optical projection device, which consists of an ion source, an ion-optical system (object-glasses), 85 an arrangement for receiving, preferably self-supporting, metal masks, a target chamber with a transfer device for semiconductor substrates, an appropriate vacuum system and a variety of measuring, electronic and 90 electrical auxiliary devices.
Light ions, for example protons or mixtures of light ions, are produced in an ion source and extracted from the latter in such a way that the ion beam is of high divergence 95 By means of a system of apertures, a partial beam of high homogeneity of intensity is created, which passes through a mask of which an image is to be produced and on which appropriate semiconductor structures 100 are formed By means of a focussing lens, the total intensity of the beam passing through the mask is directed into the entrance aperture of the objective of which an image is to be produced The objective reduces the mask 105 of which an image is to be produced according to the spacing between the objective and the image, e g by a factor of 10 relative to the original size of the desired structure on the semiconductor substrate, the image being 110 created in the vicinity of the focal plane and the objective lens potential difference defining the majority of the energy of the ions.
This "ion image" of the mask now im 115 pinges on the silicon dioxide layer and penetrates the latter to a depth depending on the energy and nature of the ions.
The electrostatic lenses and the stability of the high tension are so arranged that the 120 optical quality, depth of focus and resolution satisfy the requirements When using protons having an energy of, e g 60 ke V, the theoretical resolution is approximately 10-3 A.
For the purpose of effective application of 125 the ion projector to the production process, the latter is provided with a device for changing the masks, of adequate accuracy.
There is moreover provided a target chamber of appropriate capacity with all the auxiliary 130 1,597,595 equipment, for accommodating the semiconductor substrate.
The subsequent etching process for structuring the insulating layer is carried out by a dry etching procedure by means of gaseous etchants and preferably, though not necessarily, with the complete elimination of the wet processes.
The electrically conductive layer of the semiconductor structure, which frequently consists of aluminium, is bombarded in locally confined regions with protons (H+ -ions) by means of the apparatus according to the present invention, structural modifications in the aluminium layer being produced in such a way that, in the course of the etching processes, the bombarded regions have a higher etching rate relative to the nonbombarded regions In the apparatus according to the present invention the protons are accelerated to energies of 40-100 ke V.
The required dose is 10 " 10 '9 protons per cm 2 Following the locally confined bombardment of the aluminium layer, the structured, electrically conductive Al-layer of the semiconductor structure is produced by an Al-etching process.

Claims (4)

  1. Claims 1 to 3, wherein, for the purpose of
    producing a plurality of like structures on a semiconductor substrate, means are provided in a target chamber for mechanically displacing said substrate.
    Apparatus according to any one of Claim 1 to 3, wherein, for the purpose of producing a plurality of like structures on a semiconductor substrate, a diverting system for the ion beam is provided and so arranged that the ion beam may be reproducibly displaced.
    6 Apparatus according to Claim 1 and constructed and adapted to operate substantially as hereinbefore described.
    SAUNDERS & DOLLEYMORE, Chartered Patent Agents, 2 a Main Avenue, Moor Park, Northwood, Middx HA 6 2 HA, For the Applicants.
    Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd -1981 Published at The Patent Office, Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.
    WHAT WE CLAIM IS:1 Apparatus for the manufacture of a semiconductor element by a process in which there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one layer disposed thereon are produced, said apparatus comprising a said ion source which is adapted for the extraction therefrom of an ion beam of high divergence, a system of apertures arranged to produce from said ion beam a partial beam of substantially homogeneous intensity, and a mask having a structure of which an image is to be produced, an ionoptical system and a holder for a said element, said mask being disposed between said ion source and said ion-optical system in the path of said beam of high divergence, and said ion-optical system being arranged to cause said beam to converge on to the semiconductor element, the arrangement being such that, in operation of the apparatus, said partial beam causes an image of the mask structure, reduced in size, to be produced on said substrate.
  2. 2 Apparatus according to Claim 1, wherein the ion source is provided with a change-over device which makes it possible for the apparatus to be used with a variety of kinds of ions.
  3. 3 Apparatus according to Claim 1 or (I 1 rim 2, wherein a support for the mask comprises means for changing masks and for the correct positioning of a mask.
  4. 4 Apparatus according to any one of
GB25964/78A 1976-02-04 1977-01-24 Manufacture of semiconductor elements Expired GB1597595A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD76191181A DD136670A1 (en) 1976-02-04 1976-02-04 METHOD AND DEVICE FOR PRODUCING SEMICONDUCTOR STRUCTURES

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GB1597595A true GB1597595A (en) 1981-09-09

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GB2738/77A Expired GB1597594A (en) 1976-02-04 1977-01-24 Manufacture of semiconductor elements

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JP (1) JPS52155064A (en)
CS (1) CS209199B1 (en)
DD (1) DD136670A1 (en)
DE (1) DE2701356A1 (en)
FR (1) FR2340565A1 (en)
GB (2) GB1597595A (en)
SE (1) SE7700374L (en)

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US4967088A (en) * 1987-06-02 1990-10-30 Oesterreichische Investitionskredit Aktiengesellschaft Method and apparatus for image alignment in ion lithography

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GB2165692B (en) * 1984-08-25 1989-05-04 Ricoh Kk Manufacture of interconnection patterns
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US5266409A (en) * 1989-04-28 1993-11-30 Digital Equipment Corporation Hydrogenated carbon compositions
US5281851A (en) * 1992-10-02 1994-01-25 Hewlett-Packard Company Integrated circuit packaging with reinforced leads

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US3666548A (en) * 1970-01-06 1972-05-30 Ibm Monocrystalline semiconductor body having dielectrically isolated regions and method of forming
DE2115823C3 (en) * 1971-04-01 1975-09-18 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method for producing microstructures on a semiconductor wafer
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering
NL7413977A (en) * 1974-10-25 1976-04-27 Philips Nv APPLICATION OF A CONDUCTOR LAYER PATTERN WITH PARTS LOCATED AT A MINIMUM DISTANCE, ESPECIALLY IN THE MANUFACTURE OF SEMI-CONDUCTOR DEVICES.
DE2554638A1 (en) * 1975-12-04 1977-06-16 Siemens Ag PROCESS FOR GENERATING DEFINED BOOT ANGLES FOR AN ETCHED EDGE

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967088A (en) * 1987-06-02 1990-10-30 Oesterreichische Investitionskredit Aktiengesellschaft Method and apparatus for image alignment in ion lithography

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DD136670A1 (en) 1979-07-18
JPS52155064A (en) 1977-12-23
FR2340565A1 (en) 1977-09-02
DE2701356A1 (en) 1977-08-18
CS209199B1 (en) 1981-11-30
SE7700374L (en) 1977-08-05
GB1597594A (en) 1981-09-09

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