GB1596943A

GB1596943A - Level control of digital signals

Info

Publication number: GB1596943A
Application number: GB5812/78A
Authority: GB
Original assignee: ITT Industries Ltd
Current assignee: ITT Industries Ltd
Priority date: 1978-02-14
Filing date: 1978-02-14
Publication date: 1981-09-03
Also published as: BR7900884A; DE2905080A1; NL7900757A; FR2417221A1; AU4406979A; BE874142A; AU529904B2; DK58979A; SE7901179L; ES477655A1; MX145798A; NO790461L; NO148240B; NO148240C; JPS54114913A

Description

(54) LEVEL CONTROL OF DIGITAL SIGNALS (71) We, ITT INDUSTRIES LIMI TED, a British Company of 190 Strand, London W.C.2R lDU, England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates generally to the field of telephony and to multiplexed PCM signal transmission and communication and particularly to digital filtering of multiplexed linear digitally encoded analogue signals to provide selective digital transmission level control. The invention also relates to level control of linear PCM signals in trunk and subscriber carrier systems and digital switching systems.

Present transmission equipment utilized in systems having a plurality of analogue signal inputs which are translated into digital data signals require separate analog LC or active filters for each input channel to bandpass limit the input analogue signals prior to the digital encoding thereof. More particularly, channelbank equipment at telephone local and central offices must maintain high quality signal transmission and a constant signal level for each call transmitted, regardless of the switching path of the call. To do so, compensation must be provided for cabling losses and losses in the channel-bank equipment in maintaining signal quality. Prior art systems having analogue filters per channel are both costly and non-uniform in signal output, and cannot be time shared among channels as can the digital level control of the present invention.In modern telephone transmission equipment, incoming analogue speech signals are bandpass filtered, converted to pulse code modulated (PCM) signals according to a compressed law, and transmitted onto a span line. On the receive side, compressed PCM signals are expanded and converted back to analogue speech signals. Appropriate multiplexing and demultiplexing of channels in such systems still requires the analogue filters per channel.

While the present invention is not limited to any particular digital encoding format, a specific embodiment particularly useful in telephony is disclosed in which the signals which are level controlled are linear PCM (LPCM) signals derived from input analogue signals which have been pulse density modulated (PDM) and then translated from PDM to LPCM signals.

A PDM signal is comprised of a code in which the instantaneous amplitude of an analogue signal is represented by the ratio of logical 'l's and '0's in a binary signal, such that the average number of pulses in a given period is proportional to the amplitude of the analogue signal being encoded. An analogueto-digital converter of the PDM type is described by U.K. Patent No. 1,450,989. A PCM signal is derived by sampling an input at regular intervals, quantizing the samples into discrete steps and generating therefrom a code pattern of a series of pulses. A code translation arrangement for converting a PDM signal to a PCM signal is described by U.K.

Patent No. 1,436,878 in which patent the PCM signal is linear. A linear PCM Code (LPCM) is one in which a linear relationship exists between the digitally encoded analogue input and the digital output. When PCM signals are transmitted over a span line, they are usually compressed, i.e. made nonlinear to reduce, the quantity of data transmitted and to obtain an effident signal to noise ratio.

In telephone channel-bank equipment, low plass filtering is required to keep out-of-band signals from occurring as in-band modulation products due to sampling, which would otherwise result in "fold-back" tones in the channel.

High pass filtering may be required to reduce the 50 or 60 Hz power supply influence prior to compressed PCM conversion to eliminate the high quantizing noise, which is generated by the 50 or 60 Hz signal causing excursions into the higher quantization segments. A commonly required standard in modern telephone transmission is 20 db of 50 Of 60 Hz rejection prior to PCM compression, which is obtained by high pass filtering.

Programmable low pass and high pass digital filters of the prior art are described by U.S.

Patent Nos. 4,002,989 and 4,002,988 res pectively, and a signal processor with digital filter is described by U.S. Patent No.

4,016,410.

According to one aspect of the present invention there is provided a telephone trunk or subscriber carrier system for a plurality of time multiplexed communications channels, each of said channels being capable of transmitting serially a plurality of n-bit digital words, comprising analogue-to-digital conversion means for converting analogue input signals in each communication channel into n-bit digital words, such that said n-bit digital words are linearly related to said analogue input signals; multiplexing means for time division multiplexing a plurality of n-bit digital words from a plurality of communications channels into a serial data stream; digital filter means having said multiplexed n-bit digital words serially coupled thereto for filtering said words and for digitally multiplying said words with weighting coefficients;; digital level control means for varying at least some of said coefficients to maintain predetermined transmission levels of said n-bit digital words in said multiplexed communication channels; and means for coupling said time multiplexed data stream to said digital level control means such that said level control is time shared by said plurality of communication channels.

According to another aspect of the invention there is provided a combined digital filter and digital level control for a time multiplexed digital communications system comprising; means for serially receiving a plurality of multiplexed n-bit digital inputs at a predeter mined clock rate for deriving a plurality of parallel n-bit words therefrom; digital multiplication means for weighting each of said n-bit words, in parallel, with coefficients, at least some of which coefficients are controllably variable, such that the non variable coefficients effect a highpass filtering of said n-bit words and said variable co efficients provide a controllable gain or attenu ation of said n-bit words; means for adding said parallel n-bit weighted words to derive a digitally multi plied output; and means for controllably varying in a pre determined manner said variable coefficients.

According to a further aspect of the in vention there is provided a digital level control for a time multiplexed digital communication system comprising: means for serially receiving a plurality of multiplexed digital words at a predetermined clock rate and for deriving a plurality of parallel digital words therefrom; digital multiplication means for weighting each of said words in parallel with coefficients, at least some of which coefficients are variable and to provide selective gain or attenuation of said digital words: means for adding said parallel weighted words to derive a digitally multiplied output; and control means for selecting said variable coefficients in accordance with a predetermined transmission level for said digital words.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block diagram of the transmit portion of a telephone trunk carrier system in which a plurality of analogue channels of data are multiplexed into a LPCM code for compression and transmission over a telephone span line, and which incorporates the digital level control of the present invention, Figure 2 is a block diagram of the receive portion of a telephone trunk carrier system in which an incoming multiplexed PCM signal is digitally level controlled, demultiplexed, and converted to analogue, Figure 3 is a simplified block diagram of a digital level control in accordance with the present invention, Figure 4 is a block and logic diagram of the digital level control described with reference to figures 1 and 3, and Figure 5 is a block and logic diagram of the digital level control described with reference to figures 2 and 3.

Referring now to Figure 1, one transmit channel of a multiple chanel telephone communications channel bank is illustrated, although the described invention is applicable to communications systems generally and in particular to such systems having multiplexed data channels. Analogue signals are transformer coupled to pulse density modulator 10 via subscriber line 12, which signals are analogue speech signals having a signal level effected by transmission line conditions as aforedescribed. Pulse density modulator 10 is described in detail by the aforementioned U.K. Patent No. 1,450,989 and converts the incoming analogue signals on each of twentyfour channels to a 4.032 megabit/sec. PDM data stream. The use of pulse density modulation is illustrative only, since other linear digital modulation techniques may be utilized, such as delta modulation. The PDM cede for each channel is coupled via line 15 to a PDM to LPCM converter 14, which is described in detail by the aforementioned U.K. Patent No.

1,436,878. PDM to LPCM converter includes a digital filter which suppresses high frequency noise and produces a filtered signal which is sampled to select every mth group of n pulses.

Thus, at the output of converter 14, the 4.032 Megabit/second PDM data stream of l-bit words is converted to a linear pulse code modulated signal of 32 KiIowordslsec. of 14bit words on line 16 and which are time multiplexed with a plurality of other channels from other PDM to LPCM converters (illustratively six) to derive a multiplexed LPCM code on line 18 which is coupled to a digital multiplier 20, which comprises a digital low pass filter and shift register circuit which is time shared with four other like digital multipliers coupled to line 22 at multiplexing gates 24, and the LPCM code on line 22 is coupled to and all twenty-four channels multiplexed thereon are time shared by high pass digital filter and level control circuit 28.

Digital multiplier 20 is described in detail in U.K. Patent No. 1,476,603 M. J. Gingell - 13. However, generally, multiplier 20 serially receives a plurality of n-bit digital code groups, of total bit length corresponding to one serial data word period. The set of serial data words, inputted at a predetermined clock rate, is then multiplied in parallel, i.e.

simultaneously, by a corresponding set of fixed coefficients being derived for one of the n-bit serial inputs. The weighted parallel n-bit codes are then added to obtain an output which may be 32 Kilowords/sec. of 21-bit words.

The output is at the same clock rate as is the input.

After multiplexing with four additional multiplexors at multiplexor gate 24, the LPCM data on line 22 becomes a 8-Kilowords/sec. of 21-bit words LPCM data stream. This data stream is then high pass filtered and digitally level controlled by a combined high pass digital filter and level control circuit 28. The digital level control 28 is a digital multiplier and filter arrangement similar to that of multiplier 20, with the difference that instead of a matrix of fixed coefficients by which incoming code groups are multiplied as in multiplier 20, the coefficient matrix of level control 28 is variable and derived either from a memory or other data source, which may be remote from level control 28, and coupled thereto via line 26. The high pass filtering provides 50 or 60 Hz rejection for all of the twentyfour channels.Envelope delay equalization may also be provided. The level control coefficients, in the illustrated embodduent, are stored in a ROM and accessed to provide selective attenuation and/or gain of the digitally encoded 21-bit words to maintain a systemwide transmission level control on a per call basis, as is needed for interfacing with a telephone network. As illustrated by Figure 4, the level control is an integral part of the high pass filter. Timing, synchronization and 4.032Mhz clock signals are derived in conventional manner from a timing circuit 30 on lines 32, 34 and 36 respectively for all channels.

The digitally filtered and level controlled linear PCM signals on line 38 are coupled to a compression network 40, of the compandor type to convert the linear PCM to compressed PCM in a known manner to reduce the quantity of data transmitted, for example, by deriving CCITT Standard A-Law 8-bit PCM compressed from the 21-bit PCM, and coupling same at a 1.54 MHz rate on span line 42 in accordance with a compression algorithm. Such compression law is described in CCITT Recommendative G7 11 Green Book Vol. 3 1972.

Referring now to Figure 2, the receive por tion of the telephone trunk carrier system of Figure 1 is illustrated. The incoming compressed PCM on line 42 is expanded from 8-bit Kw/sec. in A-law companding to a 8 Kw/S 21 bit bytes in expander 44 in well known manner and coupled out on line 45 as linear PCM to level control 46 for selectable adjustment of gain and attenuation characteristics of the signal. Level control 46 is similar to level control 28 on the transmit side, except that no high pass filter is included in this example. Level control data may be remotely coupled to level control 46 via line 48 from a data bus, processor, or memory.

The 32 Kw/sec 21-bit PCM on line 50 is demultiplexed at demultiplexing gates 52 into four lines, each of which is 32 Kw/sec 21-bit LPCM having 6 channels multiplexed thereon and which is coupled to a digital multiplier 54.

Digital multiplier 54 may be of like design as multiplier 20 on the transmit side, by which the multiplexed channels in the applied 21-bit data words are multiplied in parallel by a weighted constant coefficient matrix of the add and shift type to derive a low pass filtered output on line 56, which is then demultiplexed into six single channels at demultiplexing gate 58, each of which 24 channels is coupled to a digital-to-analog converter 60 to convert the 32 Kw/sec. 16-bit LPCM words on line 62 to an analogue signal. Digital to analogue converter 60 is preferably of the type whereby the sampling rate of the digital input thereto is increased and the number of bits per sample is decreased. A digital to analogue converter of this type is described in detail by U.K. patent 1,444,216.The referenced D/A converter employs interpolation to decode using a small number of most significant bits of the increased rate sample. Thus, by performing the D/A conversion at an increased rate and feeding back and filtering the least signficant bits as an error signal, an accurate D/A conversion is obtained. Before conversion to analogue, a PDM signal is derived having a mean density proportional to the analogue signal represented by the LPCM code groups, which signal may be 4.032 megawords/sec. of l-bit words. Operationally, the LPCM code groups are interpolated, quantized, rate multiplied, pulse density modulated and low pass filtered to derive the analogue signal on line 64. After amplification at amplifier 66 the analogue signal is transformer coupled to the subscriber line 68 for the intended channel.Timing is provided in conventional manner by timing circuit 70, which provides a 4.032 MHz clock on line 72, synchronization on line 74 and other associated timing signals via lines 76 and 78 to the various digital circuits, which are preferably of intergrated circuit MSI and LSI design.

Referring now to Figure 3, a simplified block diagram is shown, illustrative of the level control portion of high pass filter and level control 28 described with reference to Figure 1. Any number of input channels 1 through N may be time multiplexed at multiplexor 80, limited only by the speed of the technology, to time share the digital level control 82, when coupled thereto via line 84 as LPCM words. In the described embodiment, 8 kilowords/sec, of 21-bit words X 24 channels are coupled thereto via line 84. The channels are operated on serially, each being multiplied in turn by its respective gain factor.

The 21 bit words are multiplied by coefficients assigned on a per-channel basis, either in software or hardware and each coefficient appears in turn, in parallel form, at lines 1 through M from memory 86, which may be a ROM, RAM, PROM or other memory having a control port 88 by which an external control of the gain settings may be obtained. In the illustrated embodiment, M is eleven, i.e. the gain coefficient is ll-bit wide. Thus, in the 21X13-bit multiplier, the level control varies 11 of 13 bits of the coefficient in accordance with external or stored control to effect a O-db to 3-db level change prior to compression. Multiplex clocking and strobe pulses are provided via lines 90 and 92 respectively.

Referring now to Figure 4, a schematic of the combined high pass filter and digital multiplier 28 of the transmit portion of the transmission equipment described with reference to figure 1 is illustrated.

Twenty-four channel of 21-bit words at an 8Kw/sec. rate (4.032 MBPS) are multiplexed at the data input 100 and coupled to a 21-bit by 13-bit multiplier 102.

The multiplier has three inputs 103, 104, 105. Data entering these inputs is multiplied respectively by coefficients aO, al and a2.

Coefficients al and a2 are fixed but aO is variable and supplied by the 32 word X 11 bit ROM 112. The address supplied to the ROM determines the value of aO selected.

The multiplier computes the result NO aO + N1 al + N2 a2 where NO N1 and N2 are the serial data words entering at 103, 104 and 105. The result at 109 is passed in turn to two serial shift registers 106 and 107 each of which are 21 bits X 24 channels long. The outputs from these shift registers feed back to the multiplier 102.

The signal output is formed by adding the multiplier serial output word at 109 together with the serial word just leaving shift register 107 minus twice the word leaving register 106.

The resultant digital filter has the transfer function (1 - 2Z-1 + Z-2) G(Z) = a, ~~~~~~~~~ 1 - a1Z-' - a2Z-2 where Z = e30Vt = Cos wt + j Sin wt w = 2irf t = 1/fs f is input signal frequency fs is sampling frequency (8 kHZ in this case).

With suitable choice for the values a, and a2 this becomes a high pass filter response with gain proportional to the value of aO.

As the data for each of the 24 channels passes in turn through the multiplier a different value of a0 can be selected from, for example a RAM which contains 24 different addresses, one for each channel. The RAM can be addressed by a counter 111 which cycles through from 1 to 24 in synchronism with the channels passing through the multiplier.

Referring now to Fig. 2 which shows the receive portion a level control 46 without the high pass is shown after the expander.

The level control is shown in more detail in Fig. 5. The operation is substantially the same as the high pass filter without the additional inputs a 1 and a2 and the shift register.

Time division multiplexed data enters the input 200 of the multiplier 201 where it is multiplied by the coefficient a0 selected from the ROM 202 by the address, in this instance, from a RAM 203.

WHAT WE CLAIM IS: 1. A telephone trunk or subscriber carrier system for a plurality of time multiplexed communications channels, each of said channels being capable of transmitting serially a plurality of n-bit digital words, comprising analogue-todigital conversion means for converting analogue input signals in each communication channel into n-bit digital words, such that said n-bit digital words are linearly related to said analogue input signals; multiplexing means for time division multiplexing a plurality of n-bit digital words from a plurality of communications channels into a serial data stream; digital filter means having said multiplexed n-bit digital words serially coupled thereto for filtering said words and for digitally multiplying said words with weighting coefficients; ; digital level control means for varying at least some of said coefficients to maintain predetermined transmission levels of said n-bit digital words in said multiplexed communica- tion channels; and means for coupling said time multiplexed data stream to said digital level control means

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. provided in conventional manner by timing circuit 70, which provides a 4.032 MHz clock on line 72, synchronization on line 74 and other associated timing signals via lines 76 and 78 to the various digital circuits, which are preferably of intergrated circuit MSI and LSI design. Referring now to Figure 3, a simplified block diagram is shown, illustrative of the level control portion of high pass filter and level control 28 described with reference to Figure 1. Any number of input channels 1 through N may be time multiplexed at multiplexor 80, limited only by the speed of the technology, to time share the digital level control 82, when coupled thereto via line 84 as LPCM words. In the described embodiment, 8 kilowords/sec, of 21-bit words X 24 channels are coupled thereto via line 84. The channels are operated on serially, each being multiplied in turn by its respective gain factor. The 21 bit words are multiplied by coefficients assigned on a per-channel basis, either in software or hardware and each coefficient appears in turn, in parallel form, at lines 1 through M from memory 86, which may be a ROM, RAM, PROM or other memory having a control port 88 by which an external control of the gain settings may be obtained. In the illustrated embodiment, M is eleven, i.e. the gain coefficient is ll-bit wide. Thus, in the 21X13-bit multiplier, the level control varies 11 of 13 bits of the coefficient in accordance with external or stored control to effect a O-db to 3-db level change prior to compression. Multiplex clocking and strobe pulses are provided via lines 90 and 92 respectively. Referring now to Figure 4, a schematic of the combined high pass filter and digital multiplier 28 of the transmit portion of the transmission equipment described with reference to figure 1 is illustrated. Twenty-four channel of 21-bit words at an 8Kw/sec. rate (4.032 MBPS) are multiplexed at the data input 100 and coupled to a 21-bit by 13-bit multiplier 102. The multiplier has three inputs 103, 104, 105. Data entering these inputs is multiplied respectively by coefficients aO, al and a2. Coefficients al and a2 are fixed but aO is variable and supplied by the 32 word X 11 bit ROM 112. The address supplied to the ROM determines the value of aO selected. The multiplier computes the result NO aO + N1 al + N2 a2 where NO N1 and N2 are the serial data words entering at 103, 104 and 105. The result at 109 is passed in turn to two serial shift registers 106 and 107 each of which are 21 bits X 24 channels long. The outputs from these shift registers feed back to the multiplier 102. The signal output is formed by adding the multiplier serial output word at 109 together with the serial word just leaving shift register 107 minus twice the word leaving register 106. The resultant digital filter has the transfer function (1 - 2Z-1 + Z-2) G(Z) = a, ~~~~~~~~~

1 - a1Z-' - a2Z-2 where Z = e30Vt = Cos wt + j Sin wt w = 2irf t = 1/fs f is input signal frequency fs is sampling frequency (8 kHZ in this case).

WHAT WE CLAIM IS: 1. A telephone trunk or subscriber carrier system for a plurality of time multiplexed communications channels, each of said channels being capable of transmitting serially a plurality of n-bit digital words, comprising analogue-todigital conversion means for converting analogue input signals in each communication channel into n-bit digital words, such that said n-bit digital words are linearly related to said analogue input signals; multiplexing means for time division multiplexing a plurality of n-bit digital words from a plurality of communications channels into a serial data stream; digital filter means having said multiplexed n-bit digital words serially coupled thereto for filtering said words and for digitally multiplying said words with weighting coefficients;; digital level control means for varying at least some of said coefficients to maintain predetermined transmission levels of said n-bit digital words in said multiplexed communica- tion channels; and means for coupling said time multiplexed data stream to said digital level control means

such that said level control is time shared by said plurality of communication channels.

2. A system according to Claim 1 wherein said digital filter means comprises a first digital filter for low-pass filtering said multiplexed n-bit words, and a second digital filter for high pass filtering said multiplexed n-bit words, said digital level control being coupled to said high pass digital filter.

3. A system in accordance with Claim 2, wherein said high pass filter includes means for serially receiving said low pass filtered n-bit digital words and for digitally multiplying said digital words in parallel with weighting coefficients, at least some of which weighting coefficients are fixed and some of which weighting coefficients are variable; and control means for varying said variable coefficients to effect a predetermined gain or attenuation of said n-bit digital words.

4. A system in accordance with Claim 3, wherein said control means includes: a matrix of said weighting coefficients; memory means associated with said matrix for varying said variable coefficients in accordance with information stored in said memory.

5. A system in accordance with Claim 4 wherein said control means includes means for addressing said memory means to select said variable coefficients.

6. A system in accordance with any preceding claim wherein said analogue to digital conversion means includes: means for converting said analogue input signals into a pulse density modulated code; and means for converting said pulse density modulated code into said n-bit digital words.

7. A system in accordance with Claim 6, further comprising: pulse compression means for translating said time multiplexed level controlled linear PCM into compressed PCM; and means for transmitting said compressed PCM onto a transmission line.

8. A system, in accordance with Claim 7 further comprising: receiving means for receiving said compressed PCM from said transmission line, said receiving means comprising: means for converting said compressed PCM to linear PCM n-bit words; digital level control means for selectively and controllably weighting at least some of the data bits of said n-bit words, and having an output; demultiplexing means for deriving a plurality of digital data channels from said output of said digital level control means; and digital to analogue conversion means for converting said demultiplexed data in each of said data channels into analogue signals.

9. A system in accordance with Claim 8 wherein said digital to analog conversion means includes: means for converting said linear PCM n-bit words into a pulse density modulated code; and means for converting said pulse density modulated code into said analogue signals.

10. A combined digital filter and digital level control for a time multiplexed digital communications system comprising: means for serially receiving a plurality of multiplexed n-bit digital inputs at a predetermined clock rate for deriving a plurality of parallel n-bit words therefrom; digital multiplication means for weighting each of said n-bit words, in parallel, with coefficients, at least some of which coefficients are controllably variable, such that the nonvariable coefficients effect a highpass filtering of said n-bit words and said variable coefficients provide a controllable gain or attenuation of said n-bit words; means for adding said parallel n-bit weighted words to derive a digitally multiplied output; and means for controllably varying in a predetermined manner said variable coefficients.

11. A combined digital filter and digital level control in accordance with claim 10 wherein said means for controllably varying said variable coefficients includes means for varying said variable coefficients in accordance with a predetermined transmission level.

12. A combined digital filter and digital level control in accordance with claim 11, further comprising: multiplexing means for time multiplexing a plurality of n-bit digital words from a plurality of channels into said serial n-bit digital input such that said digital multiplication means is time shared by data from said plurality of channels.

13. A combined digital filter and digital level control in accordance with claim 12 wherein said nonvariabie coefficients are fixed in accordance with a high pass filter characteristic of said digital filter.

14. A combined digital filter and digital level control in accordance with claim 12 wherein said nonvariable coefficients are fixed in accordance with a low pass filter characteristic of said digital filter.

15. A combined digital filter and digital level control in accordance with claim 12 wherein said control means includes: a memory for storing a matrix of variable coefficients: and addressing means for accessing said memory to select said variable coefficients.

16. A combined digital filter and digital level control in accordance with any preceding claim wherein the number of said variable coefficients is one.

17. A digital level control for a time multiplexed digital communication system comprising: means for serially receiving a plurality of multiplexed digital words at a predetermined clock rate and for deriving a plurality of parallel digital words therefrom; digital multiplication means for weighting each of said words in parallel with coefficients, at least some of which coefficients are variable and to provide selective gain or attenuation of said digital words: means for adding said parallel weighted words to derive a digitally multiplied output; and control means for selecting said variable coefficients in accordance with a predetermined transmission level for said digital words.

18. A digital level control in accordance with claim 17 further comprising: multiplexing means for time multiplexing a plurality of said digital words from a plurality of channels into a serial digital input such that said digital multiplication means is time shared by data from said plurality of channels.

19. A digital level control in accordance with claim 18 wherein said control means includes: memory means for storing a matrix of alterable coefficients: and addressing means for accessing said memory to select said alterable coefficients.

20. A digital filter in accordance with claim 19 wherein the number of said alterable coefficients is one.

21. A digital level control in accordance with claim 19 or 20 wherein said memory is a read only memory.

22. A telephone trunk or subscriber carrier system substantially as described with reference to the accompanying drawings.

3. A combined digital filter and digital level control for a time multiplexed digital communication system substantially as described with reference to the accompanying drawings.

24. A digital level control for a time multiplexed digital communication system substantially as described with reference to the accompanying drawings.