DE2905080A1 - DIGITAL TIME MULTIPLEX MESSAGE TRANSMISSION SYSTEM WITH SINGLE CHANNEL ENCODING / DECODING - Google Patents

Description

~ ⁵ ". '■. 2SO5080

M.J. Gingell-14

Time division multiplexed digital communication system with single channel coding / decoding

The invention relates to a digital communication system for time-division multiplex transmission of a large number of communication channels, in which serial n-bit words are transmitted each representing a message channel.

Such a transmission system is known, for example, from:

Burkhardt, R., Halbach, W. and Neth, A .: PCM 30, a pulse code modulation system for the Deutsche Bundespost. "Der Ingenieur der Deutsche Bundespost", 1977, booklet "2," p.49-53, booklet 3, So86-89 and booklet 4, pages 126 to 131. In this and other known transmission systems in which a large number of analog Input signals are converted into digital signals, a separate analog LC or active filter is necessary for each input channel in order to subject the input signals to a bandpass limitation before they are digitally encoded ensure high quality and a constant signal level for each transmitted call, regardless of the switching path for the call. To do this, the cable attenuation and the losses in the channel switching units must be compensated in order to maintain the signal quality. The known systems have analog filters for each channel and are both expensive and inconsistent in terms of output signals. With modern

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Telephone transmission equipment is the incoming one analog voice signals are filtered in a bandpass filter, and in accordance with a compressed characteristic curve in PCM signals implemented and then sent out via the transmission line. The compressed PCM signals are received at the receiving end expanded and converted back into the analog voice signals. The multiplex formation and the multiplex resolution of the channels in these systems requires that these filters be present for each channel.

The present invention is not limited to any particular type of digital coding. It's a special one Embodiment specified in which the signals whose level is regulated are linearly coded PCM signals (LPCM), derived from analog input signals, which are first pulse density modulated (PDM) and then from the Pulse density modulation (PDM) can be converted into the linearly coded PCM signals (LPCM).

A PDM signal consists of a code that shows the current Amplitude of an analog signal by the ratio of the logical ones and zeros of a binary Signal is represented in such a way that the average number of pulses in a given period is proportional to the amplitude of the encoded analog signal. An analog-to-digital converter that uses pulse density modulation (PDM) uses is described in GB-PS 1,450,989. A PDM signal is generated by sampling an input signal at regular intervals Time intervals and by quantizing the sample values in discrete steps and generating a code pattern a Series of pulses derived. An order for code conversion,

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which converts a PDM signal into a PCM signal is in in DE-OS 2,439,712. There the PCM signal is linear. A linear PCM code is one in which between there is a linear relationship between the digitally coded analog input signal and the digital output signal. When PCM signals are transmitted over a transmission line are usually compressed, i.e. made non-linear, in order to reduce the number of signals transmitted and maintain an effective signal-to-noise ratio.

There is low pass filtering in the telephone channel switching unit necessary to prevent out-of-band signals from occurring as in-band modulation products as a result of the Sampling, which would otherwise lead to unwanted sounds in the telephone channel would lead. A high-pass filtering may be necessary to avoid the influence of the power supply in the frequency domain 50 or 60 Hz before converting to the compressed PCM signals in order to avoid the strong quantization noise that results from the fact that the 50 or 60 Hz signal Signal transfers into the higher quantization segments caused. In modern telephony transmission, a standard of 20 dB is commonly used for 50 or 60 Hz signal rejection required before PCM compression, which is achieved by high-pass filtering.

Programmable low-pass and high-pass digital filters are in US-ps 4,002,989 and U.S. Patent 4,002,988, while a signal processor with a digital filter is disclosed in U.S. Patent No. 4,002,988 4,016,410.

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It is the object of the invention to provide a PCM transmission system indicate that meets the conditions mentioned and thereby avoids the disadvantages of known systems shown.

The object is achieved with the means specified in claim 1. Further training results from the Subclaims.

The invention will now be explained in more detail with reference to the drawings, for example. Show it:

1 shows a block diagram of the transmission-side part of the PCM system according to the invention, in which a Multiple analog communication channels in an LPCM code to form a multiplex signal Compression and transmission over a telephone transmission line is summarized,

2 shows a block diagram of the part on the receiving side the PCM transmission system according to the invention,

3 shows a simplified block diagram of a digital Level regulator according to the invention,

4 shows a block diagram of the in connection with the Fig.1 and 3 described digital level regulator and

5 is a block diagram of the in connection with the

Figures 2 and 3 described digital level controller.

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In Pig.1, a transmission channel is a channel switching unit Telephone system shown with a variety of channels. However, the invention is also applicable to communication systems in general, and in particular to such systems with time-division multiplexed data channels. Analog signals that are on the subscriber line 12 arrive, via a transmitter to a pulse density modulator 10 coupled. These signals are analog voice signals with a signal level that depends on the properties the transmission line, as previously described, is determined. The pulse density modulator 10 is described in detail in the aforementioned GB-PS 1 450 989 and sets the analog signals arriving on one of 24 channels into a PDM data stream at a speed of 4.032M Bits / s around. The use of pulse density modulation is only given as an example, since other linear digital ones are also used Modulation techniques such as delta modulation can be used. The one belonging to one of the news channels PDM code is sent to a converter 14 via a line 15 Conversion from PDM to LPCM supplied in "its details." is described in DE-OS 2,439,712 mentioned above. The PDM-LPCM converter contains a digital filter, which suppresses the high frequency noise and provides a filtered signal that is sampled around every mth group of η-pulses- Thus the converter sets 14 the PDM data stream of 4.032 M bits / s into a linearly coded PCM signal of 32 kw / s (kw = kiloword.) of 14 bit words each tan. This signal on line 16 is with a Variety of other channels from other PDM-LPCM converters (a total of 6, for example) combined in time division multiplex, so that a multiplex LPCM code appears on line 18,

M.J. Gingell-14

which is fed to a digital multiplier 20. This contains a digital low-pass filter and a Shift register circuit and is time division multiplexed with three other corresponding digital multipliers connected to the line 22 at the multiplex gates 24. The LPCM code on line 22 which is a time division multiplexed signal of 24 channels is processed further in time division multiplex by a high-pass and level control circuit 28.

The digital multiplier 20 is described in detail in DE-OS 2,636,028. In general, the multiplier receives 20 a multiplicity of digital code groups, the total number of bits of which corresponds to the period of a serial data word is equivalent to. The set of serial data words entered at a given clock frequency is then multiplied in parallel, i.e. simultaneously with a corresponding set of fixed coefficients. The weighted parallels n-bit codes are then added to give an output of 32 kw / s, with each word 21 bits having. The output signal has the same clock frequency as the input signal.

After combining this signal with three other multiplex signals in the multiplex gate 24 appears on the Line 22 is an LPCM data stream at 8 kw / s (8000 words per second of 21-bit words). This data stream goes through then a high-pass filter and a digital level regulator, which are combined in a combined circuit 28. Of course, the high-pass filter and level control functions can also be separated from each other. The circuit 28 is a digital multiplier and filter arrangement similar to that of the multiplier 20, with the difference

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that instead of a: matrix of fixed coefficients, with the incoming code groups as in the multiplier 20 are multiplied, the coefficient matrix is now variable and either from a memory or another Data source is provided. These can be separated from the high-pass and level control circuit 28 and with be connected to it via a line 26. The high-pass filtering suppresses the 50 or 60 Hz component for all 24 channels. Group delay equalization can also be performed. The coefficients for level control are stored in a read-only memory in the exemplary embodiment shown and used for selective attenuation and / or amplification of the digitally encoded 21 bit words used to create a system-wide Control of the transmission level is obtained individually for each connection, as is the case for connection to a telephone network necessary is. As shown in Figure 4, the level control is a component of the high-pass filter. the Timing signals, the synchronizing signals and the 4.032 MHz clock signal are generated in a known manner Timing circuit 30 on their output lines 32, 34 and 36 common to all channels. The digitally filtered and level-regulated linear PCM signals pass via line 38 to a compressor 40, which the linear PCM signals converted in a known manner into compressed PCM signals in order to reduce the number of data to be transmitted. To do this, it conducts the 21-bit PCM signals, for example PCM signals compressed according to the CCITT standard Α characteristic with 8 bits, which are transmitted over a transmission line 42 at a speed of 1.54 MHz. A suitable one The compression law is in the CCITT recommendation G711, Green Book Vol. 3, 1972.

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In Fig. 2 the receiving-side part is now the digital one Message transmission system shown in Figure 1. The compressed PCM signals arriving on line 42 are companded according to the Α-characteristic of 8 kw / s with 8 bits per word in 8 kw / s with 21 bits per word in converted in a known manner in the expander 44 and converted as linear PCM signals via an output line 45 to a level controller 46 for the selectable setting of the amplification and attenuation of the signal. The level control circuit 46 is similar to the level control circuit 28 on the transmission side, except that in this example there is no high-pass filter associated with it. Via a line 48, the data for level control can be sent from a remote data bus, processor or memories of the level control circuit 46 are supplied. The PCM signals with 32 kw / s at 21 bits per word on the line 50 are in the demultiplexer 52 to four Lines divided, each of which carries a multiplex signal from six channels with 32 kw / s with 21 bits per word and is connected to a digital multiplier 54.

The digital multiplier 54 can have the same structure as the multiplier 20 on the transmission side, from that of the incoming data words with 21 bits from the multiplex channels multiplied in parallel with a constant matrix of the weighting coefficients of the "add and shift" type are, so that a low-pass filtered output signal appears on a line 56, which is then in a Demultiplextor 58 is divided into six individual channels. Each of the 24 channels has its own digital-to-analog converter 60 connected to the linear encoded PCM words at 32 kw / s at 16 bits per word appearing on line 62

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converts it into an analog signal. The digital-to-analog converter 60 is preferably of the type in which the sampling speed of the digital input signals is increased and the number of bits per sample is decreased. A digital-to-analog converter of this type is in the DE-OS 2 605 724 described in detail. This digital-to-analog converter uses interpolation for decoding and evaluates a small number of the most significant bits of the samples appearing with the increased sampling speed. If thus the digital-to-analog conversion takes place at an increased speed, and the least significant bits are fed back as an error signal and are filtered, you get an exact digital-to-analog conversion » Before the conversion into an analog signal, a PDM signal is derived, which has a medium density, the analog signal represented by the LPCM code groups is proportional »This LPCM signal can have a bit rate of 4.032 M bits / s have «The LPCM code groups are interpolated, quantized, multiplied in their bit rate, pulse density modulated and in a low-pass filter filtered so that the analog signal appears on line 64 the analog signal via a transmitter to the subscriber line 68 of the associated communication channel »The time control takes care of a time control circuit in the usual way 70, on line 72 a clock signal with 4.32 MHz, on line 74 a synchronization signal and on lines 76 and 78 other associated timing signals to the various digital circuits outputs, which are preferably integrated circuits of the LSI and MSI category, ". -" -.

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3 shows a simplified block diagram of the Level control part of the combined high-pass and level control circuit 28, which in connection with Fig.1 has been described. The multiplexer 80 holds any number of input channels that are only passed through the maximum processing speed of the present technology is limited to a time division multiplexed signal together. Accordingly, the digital level control circuit 82, to which the time division multiplex signal via the line 84 in the form of LPCM words, used in time division multiplex. This is the case in the exemplary embodiment described a signal with 8 kw / s with 21 bits per word multiplied by the number of channels, namely by 24. Die Channels are processed serially, each one in turn multiplied by its gain factor.

The words with 21 bits each are multiplied by coefficients assigned to them on a channel-by-channel basis, either by a predetermined circuit, or by programming. Each coefficient appears one after the other in parallel Form on output lines 1 to M of a memory 86 which a read-only memory, a read / write memory, a programmable read-only memory or another memory is, which has a control input 88, with the aid of which an external control of the gain factors is possible.

In the example shown, M is equal to eleven, i.e. the gain factor or coefficient has 11 bits. Thus, the level control in the 21x13 bit multiplier changes 11 from 13 Bits of the coefficient corresponding to externally supplied or stored control data in order before the compression to cause a level change from 0 db to 3 db. Of the

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Multiplex clock and sampling pulses appear on lines 90 and 92.

In Fig.4 is a block diagram of the combined digital High-pass and multiplier circuit 28 of the transmission part of the transmission system shown in FIG.

Digital signals with a speed of 8 kw / s with 21 bits per word from 24 channels appear in time division multiplex (4.032 M bits / s) at the data input 100 of a multiplier 102 which can multiply 21 bits by 13 bits.

The multiplier has three inputs 103, 104 and 105. The data at input 103 are given with coefficients a0, which am Input 104 with coefficients a1 and that at input 105 with coefficients a2. The coefficients al and a2 are fixed, but a0 is variable and is stored in a read-only memory 112 with 32 words each 11 bits provided. The to the read-only memory 112 applied address determines the value of the selected coefficient a0.

The multiplier calculates the result N0 «a0 + Ni where N1, N2 and N3 are those at inputs 103, 104 and 105 appearing serial data words are. The result appearing at the output is one after the other two connected one after the other Shift registers 106 and 107 each having a length of 21 × 24 bits (504 bits). The output signals of these shift registers are fed back to the multiplier 102. The output signal is formed by adding to the output signal of the multiplier at output 109 the serial word which is currently exits the shift register 107, adds and subtracts twice the word which is currently the shift register

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leaves.

The digital filter thus realized has the transfer function

_{G (z)} . aO) _>
1-a ₁ z " ¹ -a ₂ Z" ²

Where:

Z = e- ^Iwt = cos wt + j sin wt,

w = 2uf t = 1 / fs,

f is the frequency of the input signal and fs is the sampling frequency (8 khz in this case).

With a suitable choice of the values of a .. and a _? this arrangement represents a digital high-pass filter, the gain of which is proportional to the value of a. Since the data of each of the 24 channels pass through the multiplier in turn / can have a different value of a _{Q for each channel}

for example, a read / write memory can be selected which contains 24 addresses. The read / write memory can go through a counter 111 can be addressed, which is cyclically synchronous with the channels from 1 to 24 counts.

in Fig.2, which shows the transmission side, is a level regulator without the high-pass filter connected after the expander 44.

The digital level control is shown in more detail in Fig. 5. The mode of operation is essentially the same as that of the high-pass filter according to FIG. 4, but without the additional ones Inputs a1 and a2 and the shift register. The data appear in time division multiplex on the input line 200 of the

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Multiplier 101 and are there with the coefficient aO multiplied by the address supplied by a read / write memory 203 in this example the read only memory 202 is selected.

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Claims (10)

Dipl.-Phys. Leo Thul
Short street 8
7 Stuttgart 30 M. JοGingell-14 INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK Claims Communication system are transmitted to the time-division multiplex transmission of a plurality of message channels., Wherein the serial n-bit ~ words each, a message channel represent eichnet gekennz characterized in that for each message channel, a separate encoder (10? 14? Fig.1) for converting the analog input signals into the digital n-bit words and a dedicated decoder (SO? Fig «2) for converting the digital n-bit words into the analog output signals is provided so that the time division multiplexing and the time division multiplexing resolution in several stages (18, in 1, 52, 58 in FIG. 2), digital filters (20, 28 in FIG. 1, 54 in FIG. 2) and digital level regulators (28 in FIG. 1, 46 in FIG. 2) are present which are common to several communication channels and process their signals in time division multiplex » Kg / Sch
02/07/1979 909838/0601 M.J. Gingell-14 2. System according to claim 1, characterized in / that the encoder (10, 14 in Fig.1) of its own for each communication channel deliver linearly coded PCM signals and that these are supplied in time division multiplex to a compressor (40 in Fig.1) on the transmitter side common to all channels be, which converts them into compressed PCM signals that are sent out via the transmission line, that on the receiving side (Fig.2) an expander (44) is present, which converts the compressed PCM signals into linear PCM signals, which after the digital Filtering, digital level control and time-division multiplexing can be fed to the channel-specific decoders (60). 3. System according to claim 1 or 2, characterized in that in each time division multiplex stage at least one digital multiplier (20, 28 in Fig. 1, 46, 54 in Fig. 2, 82 in Fig. 3, 102 in Fig. 4, 20 in Fig. 5), at the input of which the time-division multiplexed words from several communication channels appear serially, and which multiplies the individual words by one of a number of weighting coefficients that are either unchangeable from channel to channel (at 20 and 54) or are at least partially changeable from channel to channel (at 28 and 46, or at Fig.3, Fig.4, Fig.5) in order to selectively amplify or attenuate the individual words and that control devices (86 in Fig.3 , 110, 111, 112 in Fig. 4, 202, 203 in Fig. 5) are available, which select the variable weighting coefficients depending on the desired signal level of the digital words. 909638/0601 M.J. Gingell-14 4. System according to claim 3, characterized in that at least one of the digital multipliers (20, 28 in Figure 1; or 102 in Figure 4) for realizing a digital filter shift register (106, 107 in Figure 4) and Adders are connected, which carry out a channel-by-channel, digital filtering of the digital information arriving in time-division multiplex word-by-word serially at the input of the digital multiplier. 5. System according to claim 4, characterized in that the weighting coefficients of the digital filter (20 in Fig.1, 54 in Fig.2) are the same for all channels. 6. System according to claim 4, characterized in that the weighting coefficients (ao, al, a2 in Fig.4) of the digital filter (Fig.4) with n-bit words belonging to a single channel, which are equal to the at time intervals Duration of a time-division multiplex frame arrive one after the other and are delayed by different multiples of the frame duration (504 bits), multiplied in parallel and the products are combined via adders to the filter output signal (108), with at least some of the weighting coefficients (ao, al, a2) of the channel being added Channel is changeable. 7. System according to claim 6, characterized in that those weighting coefficients (ao) of the digital filter (Fig.4) can be changed which determine the level of the digital filter output signals and that the unchangeable weighting coefficients (a1, a2) determine the filter characteristics of the digital filter . 909838/0601 ο α Π c η M.J. Gingell-14 8. System according to one of claims 3 to 7, characterized in that the control device consists of a memory (112 in Fig. 4, 202 in Fig. 5) for storing a matrix of the weighting coefficients and of addressing means (110, 111 in Fig. 4 , 202, 203 in FIG. 4), which feed the respective weighting coefficients from the memory to the digital multiplier (102 in FIG. 4, 201 in FIG. 5). 9. System according to one of the preceding claims, characterized in that the conversion of the analog signals into the linearly coded signals and the corresponding reconversion takes place in each case via the path of pulse density modulation (10 in Figure 1). 10. System according to one of claims 3 to 9, characterized in that the variable weighting coefficients have a value less than two. 809838/0601