GB1595449A - Method and apparatus for the transmission of information in digital form - Google Patents

Description

(54) METHOD AND APPARATUS FOR THE TRANSMISSION OF INFORMATION IN DIGITAL FORM (71) We, SCHLUMBERGER LIMITED, a Corporation of the Netherlands Antilles, with administrative office at 277 Park Avenue, New York, N.Y. 10017, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a method and apparatus for transmitting information in digital form between two or more information sources and receivers. The sources and receivers may be computers and/or peripherals such as printers, card readers, magnetic tapes, magnetic drums, and so on.

Information transmission from one source to one of several receivers takes place via a common transmission system comprising a network of electrical wires or digital signal lines, currently referred to as a "bus". The invention allows information transmission between several computers, or between a computer and its peripherals, or even between several computers and peripherals associated with other computers.

Hereinafter, all devices capable of generating information to be transmitted will be regarded as sources while all devices capable of using received information will be regarded as receivers. Of course it will be recognized that some devices are capable of both transmitting and receiving functions and will be regarded as a source when transmitting and receiver when receiving.

There are different known methods for performing a transmission between several information sources and receivers. In the case of a transmission between a computer and its peripherals, use is made of a bus connecting the different sources and receivers of information to each other. Information transfer from a source peripheral to a receiver peripheral device generally takes place under the control of the computer. To achieve this, for example, the information to be transmitted is first transferred from the source peripheral to registers or memory of the computer and then transferred from the computer to the recipient peripherals. These transfer operations are carried out following instructions given by the computer and are synchronized by the computer's own time base. When two computers are conversing with each other, they are generally connected by a bus and the information is transferred from the memory of one to the memory of the other.

An initial difficulty arises when the sources and receivers are made by different manufacturers. In this case, it is not possible to connect them to each other because their outputs and inputs are not compatible, i.e. the messages transmitted by the source are not intelligible to or assimilable by the receiver, from the standpoint of electrical characteristics as well as from that of the code or the format of the information. In this case, at each output and input of the bus, use is made of an interface whose role is to ensure the compatibility, i.e. the intelligibility, of the messages sent by the source in question to the others.

Another difficulty stems from time lost by the computer controlling the information transfers.

Frequently, because the synchronization between computer memories required during transfers prohibits any other possibility conflicting use which could change its timing, the controlling computer must essentially be dedicated to this operation during the transfer time. Even sophisticated computers usually require the transfer time to be "stolen" from some part of its cycle time.

The U.S. patent No. 3,810,103 provides a solution to this problem. The main teaching of that patent is that the transfer of data from a transmitting source to different receivers can be achieved asynchronously with respect to the time base of the computer by relegating the transfer-rate timing to the receiver. Each receiver has means for indicating that it has received a transmission, and means for indicating to the computer when it is ready to receive another transmission.

It may however be noted that the transfer of data is still controlled by the computer.

Another solution is provided by the U.S.

patent No. 3,815,099. According to that patent, the data can be transferred directly from one peripheral to another peripheral.

To accomplish this, the peripheral which wishes to transmit data to a receiving peripheral requests the authorization from the computer. If the logic of the computer shows that the transfer is possible, the computer gives the authorization to the peripheral which then acquires the control of the data transfer bus. The source peripheral then transfers its data directly to the receiving peripheral through the bus. When the data transfer operation is completed, the peripheral restores the control to the computer.

Another feature of the system described in that patent is the fact that the memory of the computer is considered to be a peripheral in which data can transit before being sent directly to the recipient peripheral. It is noted that the data transfer is controlled in general by the computer and, on request, by a peripheral unit.

The different existing solutions exhibit drawbacks, among which may be mentioned the fact that systems employing them lack versatility, i.e. it is possible to connect only certain types of peripheral units to the bus.

The connected unit must be compatible with the entire system. Another shortcoming of existing solutions is that optimum use is not made of the available time, by the bus or by the different sources and receivers. Further, in all these systems the computer is at least partially assigned the task of controlling the transfer operations, even when the transfer is to take place from one peripheral to another peripheral. This results in a loss of computer time as well as bus time.

The best overall performance of a transmission system is accomplished when each part of the system transmits at its maximum rate. By contrast, in prior art systems it is common practice to slow the transmission rate of the system down to match the slowest device involved in a particular transmission.

As discussed above, when the receiver must acknowledge the receipt of each word and signal to the source or the computer that it is ready for another word before it can be sent, it is the receiver that controls the transmission rate, both of the source and of the bus; i.e. of all points in the transmission system. Thus, a slow receiver controls and slows transmission rate of the overall system. When the receiver is capable of faster rates than the source, and returns its ready signal almost immediately, it is the slower source which becomes the limiting factor of the overall transmission rate. Because of this type of limitation, the transmission rate of the bus is usually at least as high as the fastest device using the bus or the bus itself may also become a rate limiting factor.

It is an object of the present invention to provide methods and apparatus for use in digital information transmission, in which at least some of the abovementioned drawbacks and disadvantages are alleviated.

According to one aspect of the invention, there is provided a digital information exchange system comprising a multiplicity of information sources and information transmitting means, said information sources including at least two emitting sources and at least one receiving source, and said information transmitting means interconnecting said information sources and including: a bus having transmittion wires for transmitting both data and source controls words; a multiplicity of interfaces, each of which connects an associated one of said information sources to said bus and is provided with a memory in which information to be transmitted from the associated source to said bus, or vice versa, can be temporarily stored, said information being stored in the memory in the form of an information file comprising at least one control or data word; and a supervisor connected to said bus for controlling the information transfer via said bus, said information being transmitted along said bus asynchronously with respect to said sources, wherein said supervisor comprises means for storing system operating instructions, each interface comprises means responsive to said system operating instructions, and said bus comprises instruction wires for transmitting instructions between said instruction storing means and said instruction responsive means, one of said instructions allowing said supervisor to check the interface of each emitting source simultaneously to determine whether it has a data file to transmit.

According to another aspect of the invention, there is provided a method for transmitting digital information between at least two information emitting sources and at least one information receiving source via a bus, comprising the steps of: assigning a supervisor to the bus; assigning a respective memory to each of said sources; writing the information from each source having information to transmit into the memory which is assigned to that source, under the control of that source; causing said supervisor to check the memory assigned to each s;aid information emitting source simultaneously to determine whether it has information to transmit; transferring the information thus written via said bus to the memory or memories assigned to the source or sources to which the information is addressed, under the control of said supervisor; and transferring the information thus received to the source or sources to which the receiving memory or memories is or are assigned, under the control of the receiving source; wherein an order of priority is determined for the transfer of said information via said bus with the application of a strategy.

The invention will now be described, by way of example only, with reference to the accompanying drawings, of which: FIG.1 illustrates a method of information transmission and shows schematically transmission apparatus including only one bus; FIG. 2 shows apparatus which may be employed to transmit between two buses; FIG. 3 shows schematically a possible transmission system in which three buses are used; FIG. 4 represents schematically the structure of an information file as it is stored in a multiword memory associated with an information source; FIG. 5 illustrates how selected receivers are indicated in a file to be transmitted; FIG. 6 illustrates schematically the process used for transmitting the information; FIG. 7 shows schematically the connections of an interface with the bus; FIG. 8 is a block diagram of an interface connected, on the one hand, to an information source and receiver and, on the other hand, to the bus; FIG. 9 represents a simplified interface allowing the transmission of an information file containing only one word; FIG. 10 represents in detail an embodiment of the memory part of an interface; FIG. 11A, 11B, 11C, 11D, llE, and 11F represent in detail an embodiment of the logic circuits of an interface; FIG. 12 illustrates the different instructions sent by the supervisor; FIG. 13 represents the block diagram of a supervisor; FIG. 14 represents in detail a part of an embodiment of the supervisor; FIG. 15 represents an embodiment of the file length counter of the supervisor; FIG. 16 illustrates a method, or strategy, allowing the supervisor to assign an order of priority to each source among several requesting sources wishing to transmit at the same time; FIG. 17 represents a particular embodiment for implementing the strategy; and FIG. 18 illustrates the timing of various logic signals generated and utilized by the circuits shown in the above Figures.

Computers are normally equipped with a certain number of input and output terminals which allow them to be connected with peripherals or with other computers. Messages or information to be transferred are organized in the form of information files.

These files are made up of one or more words each comprising the same number of bits. This number of bits is in general sixteen, sometimes eight if the computer is small and sometimes thirty-two or more in the case of a more powerful computer. In the following description, the illustrative embodiment of the invention uses information files consisting of identical words each having sixteen bits. This figure is of course given only as an example.

In one regard, an information source may be considered as a "talker" and the receivers of the information considered as "listeners".

In this regard, computer buses provide, in addition to the 16 basic data lines, a bus wire or signal line for designating which of these functions are to be performed.

Logic signal levels such as "0" or "1" are sent on this line for this purpose and will be referred to hereinafter as TFLG or LFLG (standing for "talker flag" and "listener flag"). Devices interfaced to the bus also use the logic levels "0" or "1" to indicate that a "talker" has information to transmit or a "listener" is ready to receive.

Other lines commonly provided on such buses are a data read or write wire, and finally, at least two additional wires left available to the user.

The method and apparatus for transmitting information between different sources and receivers described herein uses only these output and input wires or lines, whatever the type of computer or peripheral. The terms wire and line will be used interchangeably herein, contemplating use of either electronic or photo-optic connections such as light pipes, for example, in the latter case.

It is evident that the present system would offer limited advantage in connecting two computers of the same type and manufacturer because, in that case, it is sufficient to directly connect the different input and output terminals to each other by means of a suitable coupling. On the other hand, the present invention would provide the advantage of relieving both computers of the bus supervision constraint. When a larger number of computers and/or peripherals have to be connected to each other, a highlycomplex direct connection is involved, and the present invention makes it possible to achieve the connection of the different sources and receivers to each other without restriction.

In FIG. 1 is show how the different transmitting and/or receiving sources are connected in accordance with the present invention. With each information source and/or receiving device 2 is associated an interface 4 which is connected to a bus 6. A source 2 can be of the type that only transmits information and, in this case, it is represented by Si and an arrow running from its associated interface 4 to network 6. A receiver can be of the type that only receives information and, in this case, it is represented by Ri and an arrow running from bus network 6 to its associated interface 4. When a device is of the type that can both transmit and receive information, it is represented by Si/Ri and a two-way arrow. The devices 2 are connected via their associated interfaces 4 in parallel to the bus 6. From a practical viewpoint, this means that the electrical wires or lines making up the bus network 6 are not cut and that the devices are directly connected, via interface 4, to bus 6.

It will be noted in FIG. 1 that no distinction is made between computers and peripheral devices. In fact, devices 2 can be of any type. Disregarding technological problems, any number of using devices can be connected to the same bus network 6. Each interface 4 includes at least one memory capable of accommodating an information file. When a source device desires to transmit an information file to one or more receiving devices, it first transmits its file to the memory of its associated interface. The file is thus in the standby position in memory associated with device 2 but included in interface 4. This transmission is independent of ongoing transmissions along bus 6. The only exception, of course, would be the case where the bus transmission is actively utilizing the interface memory.

In this regard, each bus 6 has a means of supervising the transmission activity on the bus. As shown in mG. 1, a bus supervisor 8 is connected directly to bus 6. It should be appreciated that supervisor 8 is different from any general purpose digital computer connected to bus 6 which would take the form, if connected, of device 2 and be connected through an interface 4.

When a bus transmission is authorized by supervisor 8, the information file in the memory source-associated interface is transmitted to similar memory in the interface(s) of the receiving device(s) via the bus 6.

Thereafter, the receiving devices read from the memory of their interface at whatever time they choose. It is noted that a source device wishing to transmit information writes its information into the memory of its interface at a rate and at the moment which suits it and that the same holds as regards the reading, by each receiving device, from the memory of its interface. It is also noted that the transfer of information from interface to interface takes the form of memory-tomemory transfer, which can be achieved very rapidly and that it is completely independent of the possibilities of the computers and the peripherals, in particular as regards their availability and their transmission or reception rates.

The role of supervisor 8 is to control the transfer of information. To accomplish this, the supervisor constantly checks whether one of the sources has a file to transmit. It asks the source for the identity of the receivers (addresses) of the information. It then checks whether the memories of the interfaces of these addresses are available to receive. If one of these memories is not available, it concludes that transmission is not possible for the moment and it goes on to consider the next source. When transmission is possible, it orders the transmission and finally, when the transmission is completed, it informs the source device and the receiving device(s) of the end of transmission.

FIG. 2 illustrates how two buses are connected together. Buses 6 and 12, onto which are complected devices such as computers and/or peripherals (not shown) are linked by means of an intermediate stage 14. FIG.

2 illustrates the case where the information is to be transmitted from bus 6 to bus 12, intermediate stage 14 being a receiver with respect to bus 6 under supervision of supervisor 8, and an information source with respect to bus 12, under supervision of supervisor 10. Thus, this intermediate stage acts as a memory controlled by the supervisor of one bus for writing into the memory and controlled by the supervisor of the other bus for reading.

When there is a very large number of sources (talkers) and receivers (listeners) transmitting on one bus, this bus may become saturated. In this case, it may be necessary to use several buses. This is illustrated in FIG. 3 which represents schematically a transmission system in accordance with the present invention including three buses. Device 16 and supervisor 8 are connected to a first bus, 6; devices 22 and supervisor 10 are connected to a second bus, 12; devices 28 and supervisor 30 are connected to a third bus, 32.

Intermediate stages 14, 38 and 42 are shown in FIG. 3 connecting bus #1 to #2, #2 to #3, and #1 to #3, respectively.

Stages 14 and 38 are shown as divided one- way stages A and B. In fact, certain types of transmission take place only in one direction, in which case the use of a one-w,ay intermediate stage such as shown as 42 is justified. However, generally, transmissions take place in both directions and it is necessary to use a two-way intermediate stage. It may nevertheless be considered that a twoway intermediate stage has two distinct oneway parts A and B for transmission of information in each of the two directions.

As shown in FIG. 3, devices 16 of bus 6 can transmit information to devices 22 of bus 12 via intermediate stage 14A and, conversely, from bus 12 to bus 6 via intermediate stage 14B. Similarly, devices 22 can transmit information to devices 28 of bus 32 via intermediate stage 38A and, conversely, from devices 28 of bus 32 to devices 22 on bus 12 via intermediate stage 38B. Information transmission is also possible from devices on bus 6 to devices of bus 32 through the intermediate stage 42. Devices transmitting most frequently with each other are preferably grouped on the same bus such that transmission throiugh an intermediate stage from one bus to another occurs less frequently than single bus transmissions.

To transmit information from bus 6 to bus 32, as shown in FIG. 3, intermediate stage 42 may be used. It is also possible to transmit first from bus 6 to bus 12 through intermediate stage 14A and then from bus 12 to bus 32 via intermediate stage 38A.

If the transmissions between bus 6 and bus 32 are rare, intermediate stage 42 may be superfious.

It is noted that transmission of information takes place asynchronously from two viewpoints. First of all, if we consider a system having only one bus, as shown in FIG. 1, the time base of the bus transmission system is that of the supervisor and not that of the device(s) connected to the bus line, even if one device is a computer. This is easily understood because the information files transit in the memories of the interfaces and, once in the memories, the assembly formed by the interfaces and their associated memories, the supervisor and the bus may be regarded as independent of the information source and/or receiving devices. Also, if a system equipped with several buses is considered, the time bases of the different bus supervisors are independent of each other.

If we consider the transmission of information from a source device to its associated memory in its interface, the time base is that of the source rather than that of the bus supervisor. If we consider the transmission of information from the memory associated with a receiver device in its interface, the time base is that of the receiver, which is independent of the time base of the information source or that of the bus supervisor.

The only time relationship is that transmission from the source to source-associated memory must precede that from source-associated memory along the bus to receiverassociated memory to the receiver.

It has already been indicated that the information to be transmitted is organized in the form of a file. Each file is composed of a specified number of words, varying from one to several words. Each word is composed of a given number of bits. FIG. 4 represents, as an example, the structure of an information file which can be stored in the memories of the interfaces and is the particular case where the transmitting bus has sixteen input wires and sixteen output wires.

Each word, represented by number increasing along the direction of arrow A, has sixteen bits noted from 0 to 15 in FIG. 4, represented by numbers increasing along the direction of arrow B. The information file can include up to 256 words, noted from 0 to 255 in FIG. 4. The structure of 256 words of sixteen bits each of course represents only an example and is not limitative.

The figures 0 to 255 indicated by the arrow A also represent the addresses in memory at which the information file is stored.

For example, address 0 is the first word, and can be used to specify the length of the file; i.e., the number of words to be transmitted. Thus, each file is not fixed at 256 words. The file can contain information relative to the receiver(s), for example, the addresses of the information to be transmitted. For example, the word at address 1 can be reserved to indicate the addresses of the information to be transmitted when one bus is used. The word written at address 2 can contain the addresses for devices on bus 2; the word at address 3, the address for the devices on bus 3, and so on. The rest of the available words of the information file are reserved for the information proper. It is evident that all the words in a given file need not contain information. It may then be advantageous to transmit only the words containing the information, as indicated by the file length information contained in word 0, for example. The indication of the source of the information; i.e., of the source device address, can be entered in the information file but this is not a necessity. The information contained in the file may concern commands from one source to one or several receivers and/or data proper. Command words and data words are transmitted on the same wires of the bus. The supervisor ignores the words in the files except for those assigned to file length, addresses, etc.

FIG. 5 shows a very simple way to indicate each device selected to receive the information file. The indication is made by means of the bits of an assigned word. It is assumed that there are no more than sixteen devices connected to a given bus. The word address 1 corresponds to bus number 1, address 2 to bus number 2, and so on.

To each bit 0 to 15 of address word n is assigned a device on bus n. If the bit corresponding to a given device is in a given logic state, 0 or 1, this will mean by convention that this device is the addressee of the information file. Thus, in the example of FIG. 5, where a "1" state indicates the receiver, devices 0, 3, 4, 5, 7, 9, 10 and 13 are the selected addressees on bus number 1, and devices 0, 1, 3, 5, 6, 11, 13 and 14 are the selected addressees on bus number 2.

This advantageous organization makes it possible to save time in the transmission of information from device interface to interface and bus to bus.

The general process of supervision of the transmission system is shown in FIG. 6 by means of a process flow diagram. The diagram shows the successive stages of the transmission and particular instruction codes (in paranthesis) used by the supervisor. First, as shown in block 42, the system is initialized (INI) by setting memories, counters, etc. in the interfaces to their start state, for example, at zero. Next, as shown at block 44, the supervisor asks whether any sources have requested to transmit a file. As previously mentioned, sources of information may be regarded as "talkers". Thus, the instruction used has the connotation "talker acknowledge", abbreviated here as TAC.

Thus, block 44 corresponds to the supervisor sending a "TAC" instruction to all devices on its bus.

As next shown in FIG. 6, at block 46, the supervisor determines whether there are other requests from sources requesting to transmit or devices having prior requests still pending. If no acknowledgement results or no pending prior requests remain, the test indicated at block 46 answers NO and the supervisor continues to poll the devices on its bus for requesting information sources.

lf the test reply is YES, the supervisor applies (block 48) a stategy to determine an order of priority among the different sources requesting to transmit. The transmitting source selected is then "opened" by applying an OTF (Open Talker File) instruction which also closes the bus to other devices (block 50). The supervisor then asks for the list of the addresses (receivers or "listeners") for the file (block 52) utilizing a GRL (Get Required Listeners) instruction.

As shown next at block 54 of FIG. 6, the supervisor next determines if all of the receivers have their associated memories available to receive the file to be transmitted. The addressees are scanned and asked to acknowledge if they are available and if the transmission of information is possible (block 56). If transmission is not possible, the supervisor will select another transmitter by returning to the step indicated in block 44. If all receivers are available and transmission is possible, the addressees (listeners) of the file are then "opened" (block 58) using an Open Listener File (OLF) instruction. The supervisor then asks (block 60) the selected source for the length of the file to be transmitted, using a Get File Length (GFL) instruction. The file transmission is then initiated (block 62) by a FIT instruction. At the end of the file, the supervisor signals (block 64) to the source and the receivers that the file has been sent and received as indicated by an EOF instruction.

The process then returns to the step shown in block 44 of FIG. 6; i.e., the supervisor again looks to see whether one or more sources have made requests to transmit.

Now that the method and apparatus have been generally described, specific circuits will be discussed.

FIGS. 7 to 11 show an embodiment of an interface. The interface is universal in that, on the one hand, it can be connected to a device capable of acting as an information source or receiving device and, on the other hand, it uses for its connection to the device only the terminals normally available at the output of such devices. FlG. 7 shows schematically the connection of an interface to the bus. To transmit a file composed of words made up of sixteen bits each to the bus or to receive such a file from the bus, the interface needs only sixteen connection terminals noted from 0 to interface to indicate that its listening or receiving memory is not available; e.g., its contents have not been transmitted to the receiving device and is thus write protected.

The wire located in FIG. 7 to the right of the data wires 0 to 15 and whose transmitter and receiver are hachured is an additional wire used for assigning a number to each of the interfaces and associated devices and hence for individualizing them. To achieve this, this "hachured" wire is connected to the particular one of data wires 0 to 15 equal to the number of the interface and device (in FIG. 7, for example, this hachured wire has been connected to the data wire 13 which means that the illustrated interface has been assigned the number 13). This method of individualizing the interfaces has two advantages: firstly, all the interfaces can be constructed in the same manner (it is only during the set-up of the transmission system that they are individualized) and, secondly, the interfaces are not assigned an address in the usual sense of the word. It may be noted that if two transmitting interfaces connected to the same bus bear the same number, there has been a wiring error.

Summarizing, the illustrated interface has twenty-two electrical connections, sixteen information wires used both for the inputs and outputs of the interfaces and six wires used for the "supervision" of the bus system: three wires for receiving instructions from the bus supervisor, a PLS signal wire to indicate that an instruction is being sent by the supervisor, wire B to indicate the availability or non-availability of the deviceassociated memory within the interface to be written into or, alternatively, writeprotected, and finally, a "hachured" wire allowing a number to be assigned to each interface.

FIG. 8 represents schematically an interface connected, on the one hand, to a source and/or a peripheral receiving device 66 and, on the other hand, to bus 6. The interface has two distinct parts: a "listener" portion which makes it possible to receive by means of the receivers R data coming from the bus and a "talker" portion making it possible to transmit information on bus 6 by means of transmitters E. In FIG. 8, transmitters E and receivers R are each shown schematically by a single triangle. A more detailed, but quite schematic representation has been given in FIG. 7. Each "listener" or "talker" portion has identical device-associated memories, namely a listener memory 70 associated with an information receiver or a talker memory 72 associated with an information source, word counters 74 or 76 connected to the respective memories and a flip-flop 78 or 80 having one output Q and two inputs S (set) and R (reset). These different elements are connected to the bus 6 by means of a logic circuit 82.

In general, every computer bus has inputs and outputs enabling the transmission of information to and from a peripheral device.

To transmit information, peripheral devices usually have at least output data wires 84, with as many output wires as there are bits in its information word (sixteen in the described example), an optional signal FTD (file transmitted) left at the disposal of the user, a signal wire TFLG (talker flag) to indicate that it has sent information, and finally, a wire WTD (word transmitted) on which is sent a signal whenever the device sends a word. For the reception of information, the device has inputs 86, the number of which is equal to the number of bits there are in its information word (sixteen in our example), a signal FAD (file accepted) left at the disposal of the user, a signal wire LFLG (listener flag) to indicate that it has received the information and, finally, a wire WAD (word accepted) on which is sent a signal whenever the device reads an information word.

Assuming that peripheral device 66 requests transmitting a file to one or several receivers through the bus 6; then device 66, acting as a source, first examines the logic state of the input TFLG: if TFLG is in logic state 1 this means, for example, that the talker memory 72 is empty. If TFLG is in logic state 0 this means, on the contrary, that the talker memory 72 is still protected from being written into. Assuming that the talker memory 72 is not write-protected and is available (TFLG= 1), it will be automatically preset at the address 0.

Device 66 then transmits an information word on its outputs 84 to talker memory 72.

A signal is also sent by device 66 at this time on its output WTD to logic circuit 82, indicating "word transmitted". This signal allows the writing of the word transmitted by the device into talker memory 72. Moreover, for each WTD signal received by logic circuit 82, a signal TINC (talker increment) is transmitted by circuit 82 which increments memory-word counter 76 by one row.

Thus, since the talker memory 72 was initially preset at address 0, and the WTD signal results in a TINC signal which increments counter 76, counter 76 then indicates address 1. When device source 66 has finished sending its information file, it supplies a signal FTD which is applied to the input R of flip-flop 80, thereby placing the output Q; i.e., the signal line TFLG, in logic state 0.

The output Q of the flip-flop 80 is placed in the logic state 0 by the source 66 when it has finished writing in the talker memory 72, as described above, and placed in the logic state 1 by a signal transmitted by the logic circuit 82 on the wire RFW (ready for writing) when the content of the talker memory 72 has been transmitted via the bus to the listener(s). The wire TPL (talker parallel load) of memory-word counter 76 allows an externally-determined address in the memory 72 to be chosen. Circuit 82 output and input labeled "TALK" which is connected to transmitters E correspond to an additional flip-flop, not shown. If the latter is in a logic state 1, for example, the transmitters E are connected to the bus 6 (in FIG. 7, this means that the switches I are closed) and if it is in a logic state 0, this means that the transmitters E are disconnected from the bus 6. The result is that if TALK =0, a signal appears on wire RFW to indicate to source 66 by the setting of flip-flop 80 that it can write into talker memory 72 after the signal TFLG (output Q of flip-flop 80) switches from the logic state 0 (memory 72 protected) to the logic state 1 (memory 72 available to be written). The signal TMR (talker memory reset) resets counter 76 and presents memory 72 address to 0.

Let us now assume that the interface shown in FIG. 8 has a file to receive (listener portion). If the output Q of flip-flop 78, and hence the input listener flag LFLG signal to device 66, is in a logic state 1, this means by convention that the listener or receiver memory 70 still contains information not yet transmitted to device 66, that the device 66 can read from this memory, and that the part of the interface is not available to the bus 6. On the other hand, if the logic state of output Q of flip-flop 78 is 0, the contents of memory 70 have been received by device 66 and the memory 70 is available for input. Whenever device 66 has read a word from listener memory 70, it sends a signal WAD (word accepted) to logic circuit 82 which leads to the appearance of a signal LINC (listener increment) which increments memory-word counter 74 by one row. When device 66 has finished reading the file contained in memory 70, it sends a signal FAD (file accepted) to the input R of flip-flop 78 whose output Q then switches over to logic state 0. In this case, memory 70 is available and a new file can be written into memory 70 through receivers R. Output and input, indicated LSTN, of the listener portion of logic circuit 82 symbolize a flip-flop: if LSTN is in logic state 1, this means that memory 70 associated with device 66 is available and a file can be received by listener memory 70. If LSTN is in logic state 0, this means that the listener memory 70 is not available to bus 6. When the signal LSTN switches from the logic state 1 to the logic state 0 following the instruction EOF (end of file) sent by the supervisor, logic circuit 82 causes the signal RFR (ready for reading) to appear and indicate to device 66 that it can receive the contents of listener memory 70. The signal LMR (listener memory reset) also generated by circuit 82 resets counter 74 to 0.

FIG. 9 represents schematically an interface intended to be associated with device 88 transmitting and receiving a single word only. Device 88 can be, for example, a voltmeter transmitting only one measurement at a time. It is noted that the interface shown in FIG. 9 is nothing other than a simplification of the interface shown in FIG. 8. In fact, signals FTD (file transmitted) and FAD (file accepted) are no longer necessary since it is now no longer of use to indicate that the information file has been either transmitted to or from the device-associated memory.

Elements of the interface as shown in FIG.

9, which are identical to the elements of the interface of FIG. 8, have been assigned the same reference numbers. It is noted that the receiver-associated memory 70 and the source-associated memory 72 are no longer associated with memory-word counters (74 or 76), since the information to be transmitted contains only one word, and word counters are not required. Resetting of flipflops 78 and 80 (input R) is performed respectively by signals WAD and WTD.

Operation of the interface of FIG. 9 is merely the simplified operation of the interface shown in FIG. 8. For the talker portion, device 88 scans the logic condition of signal TFLG to determine whether memory 72 is available. Note that memories 70 and 72 contain only one word. If talker memory 72 is available, device 88, acting as an information source, sends a word to be transmitted which is written into memory 72 and signal WTD to the reset input of flip-flop 80, which changes its Q output and the logic state of signal TFLG. Subsequently, input S (set) of the flip-flop 80 is placed in logic state 1 by logic circuit 80 and signal TFLG returned to its former state 0 when the content of memory 72 has been transferred to the bus.

The listener portion of the interface shown in FIG. 9 functions substantially in the same manner. Device 88 knows that there is information in memory 70 when signal LFLG is in logic state 1. The information is transferred from receiver-associated memory 70 to device 88 through inputs 86. Device 88 sends a signal WAD when receiving the contents of memory 70 which resets flip-flop 78 and changes the logic state of signal LFLG.

FIG. 10 represents in detail an embodiment of a part of the interface shown in FIG. 8. The right-hand part represents the "listener" part and the left-hand part represents the "talker" part. Memory 70 of the "listener" part is represented by four mem ory stages 90, 92, 94 and 96. Counter 74 of the "listener" part is represented by the two counter stages 98 and ]00. The large horizontal rectangle 102 represents schematically the connection of listener memory 70 to the receiving portion of a device by means of the sixteen information input terminals 104 in the device. The sixteen inputs 106 in memory 70 in the form of 4 bit counters are connected to receivers in circuits 134 indicated by R. Counter 74 in the form of 4 bit counter stages 98-100 has eight output wires 108 representing the eight address wires of memory 70. Wire LMR is used for resetting counter stages 98-100 as previously discussed in regard to counter 74. Whenever counter 74 is to be incremented by one row, a signal LINC is sent on the corresponding wire to the counter. Input LR/W is used to preposition talker memory 70 in the reading or writing position. When the bus transmits information to be entered in the memory, the memory is prepositioned in the writing position.

When the receiving device reads from the memory the reading position is chosen. The large horizontal rectangle 110 represents connections between the interface and the bus. To each of the 16 data line connections 112 between the interface and the bus are connected a transmitter E and a receiver R.

The receivers R are connected permanently to the bus.

The four rectangles 114, 116, 118 and 120 of Fig. 10 represent talker memory 72 of FIG. 8. The two 4-bit counter stages 122 and 124 represent counter 76 of FIG. 8. Counter stages 122124 have eight output wires connected to eight address wires 126 of memory 72.

This memory is connected to sixteen information outputs in the source portion of the device by means of the connector 128 and sixteen terminals 130. Sixteen outputs 132 of memory stages 114--1166-1118-120 of memory 72 are connected to transmitters E in circuits 134. Input TMR to counter stages 122-124 of counter 76 makes it possible to reset counter 76 and thereby choose the address 0. Input TPL to counter stages 122-124 allows prepositioning of counter 74 at a given address. This input TPL is particularly advantageous when the transmitting and receiving system has several buses. Receivers indicated by information stored at memory addresses corresponding to the bus through which the file stored in the memory is to be transmitted, can be selected by means of the signal TPL. Input TR/W to memory 72 makes it possible to preposition memory 72 in the reading or writing position.

The four circuits 134 shown connected to bus 6 in FIG. 10 act as switches I (FIG.

7) allowing the connection of transmitters E to bus 6. When input 136 of circuits 134 are in logic state 1, transmitters E are disconnected from the bus and are connected when their logic state is 0. The connection of transmitters E to the bus depends also on the logic state of the outputs of OR gate 140 and AND gate 138. For transmitters E to be connected to the bus, it is necessary that four instructions FIT, GRL, GPL and OLF all be present in addition to a signal designated as TALK. The meaning of these first four signals, which correspond to instructions sent by the supervisor, was briefly described in regard to FIG. 6 and will be described further with reference to FIG. 12.

By way of example, transmitters E can be made up of open-collector NAND gates and receivers R can be simple inverters or adapters. Circuits 134 can be integrated circuits of the MC 3443 type; memory stages 90, 92, 94, 96, 114, 116, 118 and 120 can be integrated circuits of the 5101-2 type, and counter stages 98, 100, 122 and 124 can be integrated circuits of the 74 LS 197 type.

FIGS. llA, 11B, llC, 11D and llE represent in detail embodiments of logic circuits 82 of an interface. These logic circuits allow generation of the previously described signals LINC, TINC, LR/W, TR/W, TPL, LMR and TMR indicated in FIGS. 8, 9 and 10.

FIG. 11A represents decoding circuit 150 equipped with three inputs 152 to which are applied the instructions coming from the supervisor. Referring to FIG. 7, it was indicated that the instructions from the supervisor are conveyed through wires 16, 17 and 18. From logic instruction signals applied to inputs 152, circuit 150 provides signals corresponding to instructions TAC, GRL, OLF, GFL and FIT in negative logic, as indicated by lines or bars over these designations, as for example, GRL. The latter four instructions were discussed in regard to inputs to AND gate 138 shown in FIG.

10. Where positive logic or the inverse of one of these signals is required, an inverter may be employed, as is well known by those skilled in digital logic circuitry.

FIG. 11B represents a part of logic circuit 82 allowing the generation of signal LMR used generally as listener memory reset but also for resetting a memory-word counter (counter 74 or its stages 98-100 respectively in FIG. 8 or 10) associated with the listener memory of an interface. The "listener"memory reset LMR signal is generated when certain events occur, as achieved by means of NOR gate 154 and AND gate 156, as for example, when the transmission system is reset to its initial state (this is accomplished by instruction INI sent by supervisor as discussed in regard to FIG. 6 at block 43), and when the listener memory is placed at its initial write address 0 (instruction GFL) but here only when the listener memory has been authorized by the supervisor to receive (signal LSTN), the latter two signals being inputs to AND gate 156. Circuit 158 shown in FIG. llB is a differentiator circuit which delivers a signal when input level LFLG goes from logic state 1 to logic state 0, (see timing shown in FIG. 18AND), which corresponds to the instant the listener memory finishes receiving information (or an EOF instruction, for example). Its output to NOR gate 154 also can result in gate 154 generating the listener memory reset signal LMR by changing its output from LMR to LMR.

Circuit of FIG. 1 1C is similar to that part of logic circuit 82 shown in FIG. 11B but concerns the "talker" part of an interface. The circuit represented in FIG. 11C, including NOR gate 160 and AND gate 162, allows generation of signal TMR utilized generally as "talker"-memory reset but also to reset talker-memory word counter 76 shown in FIG. 8 or its stages 122-124 as shown in FIG. 10. This counter is reset when instruction INI is transmitted by the supervisor; i.e., when the transmission system is placed in its initial state. The TMR signal is also desired to reset the talker-memory at its initial read address 0 when instruction GFL is present but here only when the "talker" part of the interface has been authorized to transmit (signal TALK) as indicated by the use of GFL and TALK inputs to AND gate 162. Moreover, it is necessary for the talker memory to be reset to zero when its reading has just been completed (EOF), this being accomplished by differentiator circuit 164. Like differentiator circuit 158 shown in FIG. llB, circuit 164 is a differentiator circuit which delivers a signal when its input signal (here TFLG) changes from logic state 1 to 0 (see FIG.

18AND).

FIG. 11D shows how signal TPL is obtained in logic circuit 82. This signal is delivered by NAND gate 166 receiving, on one of its two inputs, logic signal TALK which indicates that the transmitters of the "talker" part of the interface have been connected to the bus, and on the other input instruction GRL transmitted by the supervisor and corresponding to the selection of the addressee interfaces for receiving a bus transmission.

FIG. 1 lE represents an embodiment of a part of interface logic circuit 82 making it possible to write or read in listener memory 70 (FIG. 8 or 9) or its stages 90--96 (FIG. 10). This circuit delivers logic signals LR/W and LINC respectively to listener memory 70 and word counter 74. The signal LR/W is used to enable writing into the listener memory and LINC to increment its address. To read from listener memory 70; i.e., when information has already been transmitted along the bus into memory 70 and now is to be transmitted from the interface to its associated receiving device, signal LINC is delivered by logic circuit 82 and used for incrementing word counter 74 of listener memory 70 whenever a signal WAD (word accepted) is delivered by the receiving device associated with the considered interface; i.e., whenever an information word has been accepted from the receiver-associated memory by the receiver.

To write into listener memory 70; i.e., when information is being transmitted along the bus to the receiver device associated with the interface, the logic signal LSTN must be present authorizing the listener to receive. Then, with each transmission of a word onto the bus, the supervisor sends instruction FIT for transmission of the word. Thus, in the presence of the LSTN authorization signal, each instruction FIT results in a set signal appearing at the output of NAND gate 170 shown in FIG. 11E.

This will occur, of course, only for each peripheral device authorized to listen by signal LSTN. With this set signal, output Q of C-D flip-flop 172 will change over to logic state 1. Flip-flop 172 has its terminals Q and R connected to each other by means of a 500-nanosecond delay line 174. The result is that output Q of flip-flop 172 is a signal of 500-nanosecond duration (see FIG.

18E > J). This Q output is applied to one of the two inputs of NAND gate 176, the other input receiving signal LSTN. Thus, if LSTN and FIT are both present, a 500-nanosecond signal LR/W is transmitted to memory 70, thereby enabling the writing of information then on bus 6. Output Q of the flip-flop 172 is also transmitted by transmitter 177 to delay 178 where it is delayed by 200-nanoseconds. Logic signal LINC results from use of this delayed signal input to differentiator circuit 180. This type of circuit was described in regard to FIGS.

11B and 11 C. Consequently, 200-nanoseconds after the appearance of signal LR/W, signal LINC appears. Signal LINC increments counter 74 associated with listener memory 70. On the other hand, if logic signal LSTN is in the logic state not allowing generation of signal LR/W, this means that the listener memory 70 is not available for receiving and writing information from the bus and that the device associated with the considered interface may be still reading a prior transmission from that memory. Signal LR/W must not yet be sent or it may allow destructive writing into the memory. Signal LSTN thus controls the output of the NAND gate 176, protecting the contents of memory 70 when appropriate.

However, it is still necessary for counter 74 associated with listener memory 70 to be incremented by signal LINC (shown in FIGS. 8 and 10) whenever an information word has been transmitted from memory 70 to the receiving device. It will be recalled from the description of FIGS. 8 and 9, that for each word transmitted, signal WAD is sent by the receiving device. In this case, it is NAND gate 182, shown in FIG. llE, receiving on its two inputs signal LSTN and WAD (in negative logic, LSTN and WAD, respectively) which causes the appearance of the 500-nanosecond signal at output Q of flip-flop 172. Thus, the sending of signals WAD by the receiving device, in the absence of enabling signal LSTN, now causes the appearance of signal LINC, and not the supervisor's FIT signals as in the case where signal LSTN enabled writing into memory 70.

FIG. 1 lF represents an embodiment of a part of logic circuit 82 making it possible to write or read information in "talker" memory 72 (FIGS. 8 and 9) or stages 11y' 120 (FIG. 10). As shown in FIG.

11F, C-D flip-flop 184 is connected: to receive on its C input, NAND gate 186 output which receives logic signal TALK and WTD; to receive on its S input NAND gate 188 output, which receives on its two input signals TALK and FIT; to output at Q to NAND gate 190 and transmitter 195; and to output at Q to a 500-nanosecond delay line 192. Transmitter 195 output is connected to a 200-nanosecond delay line 196 which inputs to differentiator circuit 198 (like that already described) to deliver signal TINC. NAND gate 190, which delivers signal TR/W on its output, receives on its two inputs the signal TALI( and the 500nanosecond signal transmitted from output Q of the flip-flop 184. Differentiator circuit 198 transmits signal TINC at its output 200nanoseconds after TR/W as with LINC and LR/W for the similar circuits shown in FIG. 11E.

Assuming that TALK =1, which means that "talker" memory 72 has information to transmit on the bus, it is necessary to protect memory 72 from being written into and changed. To achieve this, signal TR/W is left in logic state 1, protected by the TALK=0 input to gate 190. To transfer a word from the "talker" memory 72 to bus 6, the supervisor sends instruction FIT, which in the presence of the TALK=1 signal at gate 188 results in output Q. In this case, signal TR/W is left in logic state 1 because logic state TALK =1 necessary to cause TR/W is not present as input to NOR gate 190. However, logic signal TINC is delivered by logic circuit 82 each time a word is transmitted to bus 6 so as to increment counter 76 associated with "talker" memory 72.

On the other hand, when the logic state for signal TALK indicates that the source device can transmit information to "talker" memory 72, memory 72 is then placed in the enable writing position by the change-over of signal TR/W to the appropriate logic state. This occurs when signal WTD is applied to one of the two inputs of the NAND gate 186. Signal WTD is sent by the source device whenever it has transferred a word to be written into the "talker" memory as described in regard to FIG. 8. After the appearance of signal TR/W, signal TINC is delivered after a 200-nanosecond delay caused by delay line 196. Signal TINC thus increments memory-word counter 76 associated with talker memory 72 but now during a write process.

The logic of the bus supervisor will now be described. The supervisor sends instructions to the different interfaces so as to control the transfer of files between interfaces.

These instructions are represented schematically in FIG. 12. Referring to FIG. 7, it was mentioned that bus 6 has, notably, three wires 16, 17 and 18 to carry the instructions transmitted by the supervisor.

These wires are represented schematically again by 16, 17 and 18 in FIG. 12.

To control the transfer of files between the different interfaces, the supervisor sends instructions to these interfaces. Eight such instructions are described in this illustrative embodiment, the list of which is given in FIG. 12. These instructions are conveyed by bus 6 on the electrical wires 16, 17 and 18. Instruction INI (initialization) corresponds to logic states 0, 0, 0 on electrical wires 16, 17 and 18 respectively and causes the general resetting of the system. This is accomplished when, for example, the communication system is started up or by actuation of a reset control. In response, all transmitters E (see FIG. 7) of the different interfaces are disconnected from the bus by the opening of switches I in the interfaces as already described.

Instruction TAC (talker acknowledgement) is transmitted to allow the supervisor to determine whether one of the interfaces has information to transmit. This instruction also opens, again, switches I of trans mitters E on the data wires e15. To determine whether one of the interfaces has a message to transmit, the supervisor closes switch I of the "hachured" wire (previously described in regard to FIG. 7) of all the interfaces. This "hachured" wire is represented on the far right in FIG. 7. It was mentioned that this hachured wire is used to assign a number to the interface (in FIG.

7, the hachured wire has been connected to the data wire 13 which means that the interface is assigned the number 13). When a device wishes to transmit information, it places the transmitter E for the hachured wire of its interface in a logic state 1. If, for example, by closing switch ] of the hachured wire of all the interfaces, the supervisor notices that wires 13 and 15 of the bus are in logic state 1, it concludes that devices associated with interfaces 13 and 15 have information to transmit. Devices having no information to transmit will have logic state 0 on transmitter E of the wire corresponding to their interface.

Instruction OTF (open talker file) allows the supervisor to choose, by applying a strategy, the source (TALKER) which is to transmit first from among several possible source having information to be transmitted at a given moment. For this purpose, the supervisor sends a logic state 1 on the bus wire corresponding to the number of the chosen interface. Thus, the R of the interface shown in FIG. 7. As with the interfaces, receivers R can be adapters and transmitters E can be open-collector NAND gates. Transmitters E at block 202 of FIG. 13 are connected to the information wires 0--15 of the bus and are associated with switches I as in the case of FIG. 7, represented schematically in FIG. 13 by arrow 204. By contrast, transmitters E at block 206 of FIG. 13 are connected to instruction wires 16, 17 and 18 of bus 6. Initially, logic circuit 208 of the supervisor sends instruction INI on bus 6 by means of transmitters E shown at block 206. Logic 208 then increments instruction counter 210.

This instruction counter is associated with instruction memory 214 in which have been written the instructions shown in FIG. 12.

Thus, whenever an increment signal is input at 212 to counter 210 by logic 208, a new instruction address in memory 214 is generated and its instruction sent on wires 16, 17 and 18 of the bus. An example of the possible content of memory 214, showing instructions in code form is given in FIG. 12.

It will be recalled that the selected source file length is present on the bus during the GFL instruction. At this time, the file length is recorded in counter 216 shown in FIG.

13 by a signal applied to its input 218. When several interfaces have a message to be transmitted at the same moment, logic circuit 208 calls on strategy circuit 220 which determines a priority as already discussed and as will be described in regard to FIG.

17. The timing for sending the different instructions, as well as for the transmission on the bus, is performed by clock H connected to bus 6.

Initially, instruction INI is sent on instruction wires 16-18 by transmitters E at 206 to the different interfaces. Then, instruction counter 210 is incremented and instruction TAC appears at the output of the memory 214 and is sent on transmitters E at 206.

If none of the interfaces wishes to transmit information, instruction counter 210 is not incremented and the supervisor will thus continue to send the instruction TAC. When an interface has information and makes a request to transmit, instruction counter 210 is incremented and the instruction sequence continues to instruction OTF which is sent on the bus from memory 214. In the same manner, instruction GRL is sent when instruction counter 210 is again incremented.

Now, if instruction GRL shows that the requested transmission is not possible because one cf the addresses for the transmission is not available, instruction counter repositions the memory at its address corresponding to previous instruction TAC (see FIG.

6 at blocks 52, 54 and 56). On the other hand, when the transmission is possible, the address of memory 214 will be incremented and instruction OLF sent so as to "open" the addresses of the requested transmission.

Next, instruction GFL is sent so as to get the length of the file to be transmitted from the source (stored in word 1 of its associated memory). This length is then read into counter 216 of the supervisor. Word-byword transmission is then performed by reseating instruction(s) FIT, each docrementing counter 216 via input 218, until counter 216 reaches zero. A "done" signal is then sent from counter 216 to input 222 of logic 208.

FIG. 14 represents in detail a particular embodiment of logic circuit 208, instruction counter 210, and memory 214 of supervisor 8. In FIG. 14, circuit 224 shows the equivalent of the memory 214 as well as part of logic circuit 208, the rest of logic circuit 208 being represented by decoding circuit 226 shown in F1G. 14. Instruction counter 210 is represented in detail. Circuit 224 shown in FIG. 14 is made up of an assembly of AND gates 230, NAND gates 232, OR gates 234 and inverters 236. The different instructions applied to the input of these logic gates are represented in FIG. 14 using the terminology of FIG. 12. Signal BR indicates that all the interfaces requesting to transmit information at a given moment have in fact transmitted their information (this will be explained in the description given with reference to FIG. 17). Signal DONE is applied to the input 222 of the logic circuit 208 (FIG. 13) by counter 216 when its count has been decremented to zero at the end of the transmission of a file. The logic used can be negative: this is the reason for the presence of lines over certain instructions to indicate that it is the inverse of the logic signal shown which is considered. The inverse of a logic signal is obtained easily by means of an inverter such as inverter 236.

Instruction counter 210 includes essentially three identical flip-flops 238 which can be, for example, integrated circuits of the 74 LS 74 type. On inputs 240 of flip-flops 238 are applied clock signals H. On second inputs 242 of flip-flops 238 are applied signals coming from circuit 224, as represented in FIG. 14. Output of each flip-flop 238 represents one of three transmitters E at 206 (FIG. 13) of the memory 214 which are connected to the three instruction wires 16-18 of bus 6. Outputs 244 of flip-flops 238 in instruction counter 210 are thus used to generate the instructions as represented schematically in FIG. 12. Outputs 244 of instruction counter 210 are also applied to three inputs of decoding circuit 226 which furnishes at its eight outputs 246 instruction signals, both positive and negative, for the eight instructions shown in FIG. 12. Circuit 226 can be, for example, an integrated cir cuit of the 74 LS 42 type. Inverters 248 make it possible to obtain the inverse of the input logic signals. Circuit 250 of instruction counter 210 represents a device for initialization upon the switching on of the system and applying electric power to circuit 250 at terminal 252.

FIG. 15 represents in detail an embodiment of file length counter 216 (FIG. 13).

This counter makes it possible for supervisor 8 to store the length of the file to be transferred. Counter 216 includes mainly three elementary counters 254, 256 and 258 which can be, for example, integrated circuits of the 54 LS 191 type. Each elementary counter has four inputs 260. For files of a length of 256 words or less, only the first input 260 of counter 258 is used the other three being connected to the ground as shown in FIG. 15. The length of file information is applied to the inputs 260 not connected to the ground. Three elementary counters and nine inputs are used because the file may include, in the described embodiment, up to two hundred and fifty-six words. The eight inputs 260 of the two counters 254 and 256 make it possible to count from zero up to 255; i.e., 2s1. The third counter 258 has been added for convenience to count up to 256 and beyond.

Counters 254, 256 and 258 shown in FIG. 15, which make up counter 216 shown in FIG. 13, are prepositioned at a count corresponding to the length (in words) of the file to be transmitted; i.e., the data present on the nine inputs 260 are entered in the counters when instruction GFL (get file length) is present on their inputs 262. Thus, when instruction GLF is complete, counter 216 is set equal to the number of words to be transmitted from the source device.

Whenever a file word is transmitted, instruction FIT is sent on input 264 of elementary counter 264 as it is in the least significant bit position, and thereby decrements counter 264 by one unit each time. Counter 256 is decremented in turn via line 265 each time counter 254 reaches zero, and similarly for counters 258 and 256, respectively. Instruction FIT can decrement the counters only when bus timing signal PLS is present on the inputs 266 to the counters. When the content of all the counters Is zero; i.e., at the end of the transmission of the file, a signal is sent on the output 268 of each counter to NAND gate 270 and signal DONE is transmitted at its output to logic circuit 208 shown in FIG. 13.

FIG. 16 illustrates schematically strategy used by bus supervisor 8 to give priority to a source device requesting to transmit information when several sources make their request at substantially the same time. The column on the left represents the successive moments 1, 2, 3, 4 . . ., 9. The second column from the left represents occurrences of instruction TAC which, as already indicated, is transmitted by the supervisor to ask the interfaces of different possible sources whether they request to transmit.

Here, TACM means that the answer from interfaces responding to instruction TAC has been stored. In the middle column are shown the devices which made a request to transmit followed by the addresses (receivers) of the transmission. Thus, 1 (2, 3) means that device number 1 (acting as a source) requests to transmit to receivers associated with interfaces 2 and 3; the notation 2 (3) means that device 2 has requested to transmit to receiver 3; the notation 3 (4) means that device 3 requests to send to receiver 4; and so forth. The figures shown in brackets indicate the available receivers at the considered instant. Thus, ![1, 2, 3, 4] means that at the considered instant addresses 1, 2, 3 and 4 are available. Finally, the right-hand column indicates the device selected as the source by application of the principles used by the strategy. It should be borne in mind that a given device can perform as a source or as a receiver. Due to separate logic and associated memories in the interface associated with each device, a device can be performing as a source and yet be available as a receiver.

The strategy principles are as follows: At a given moment, review all devices requesting to transmit and store the result. No other review is carried out as long as all requesting devices thus stored have not transmitted their information. Furthermore, highest priority is assigned to the requesting device having the lowest number, provided however, that this device has requested to transmit to available addressees. The advantage of this strategy is that all requesting devices will be authorized to transmit between reviews.

At moment 1 shown in FIG. 16, devices 1, 2 and 3 have information to transmit respectively to addressees 2 and 3, to addressee 3 and to addressee 4. The available addressees are 1, 2, 3 and 4. The result of the strategy is that the selected source is device 1. At moment 2, device 2 still requests to transmit to 3, and device 3 requests to transmit to 4. Available addressees are 1 and 4. Device 1 is in the process of transmitting its information to 2 and 3 and, consequently, the latter are not available at this moment.

Thus, the above strategy selects device 3 as the next source at moment 2. At moment 3, only the request of device 2 to transmit to addressee 3 remains from the first review.

Available addressees are 1, 2 and 3; addressee 4 not being available since device 3 is transmitting to it. The result is that at moment 3, device 2 is selected as the source and all requests from the first illustrated review have been granted.

At moment 4, a new review is made by sending instruction TAC and storing the responses (TACM). The stored result shows that device 1 requests to transmit to receiver 4 and device 3 requests to transmit to receivers 2 and 1. The available addressees are 1, 2 and 4. The result is that device selected as source is device 1. At the following moment, there remains the request of device 3 requesting to transmit to receivers 2 and 1. Available addressees are 1 and 2 since device 1 is in the process of transmitting to receiver 4. Device 3 is selected as the last source.

At moment 6, instruction TAC is transmitted for a new review and its result is stored. Devices 1 and 2 request to transmit respectively with receivers 2 and 3 and 1 and 3. The available addresses are 3 and 4 since the source or talker part of device 3 is in the process of transmitting to receivers 2 and 1 which are thus no longer available. Thus, the request of the device 1 can not be satisfied since receiver portion of device 2 is no longer available. Likewise, the request of device 2 cannot be satisfied, since receiver 1 is not available (still receiving from 3), although address 3 (the receiver portion of device 3) is available. This results in a "PAUSE" in the strategy for the moment.

Then, following at moment 7, the same requests are found as at moment 6 but the available addresses are changed, in this case; 1, 2, 3 and 4 are now available. The result is that the device selected as the next source is device 1. At moment 8, there remains the request of device 2 requesting to transmit to addresses 1 and 3. Available addresses are 1 and 4. The address 3 is no longer available because device 1 is in the process of transmitting to it. There is thus another PAUSE.

Finally, at moment 9, the request of device 2 is satisfied.

FIG. 17 shows, as an example, an embodiment of the above-described strategy (220 in FIG. 13). Strategy circuit 220 of supervisor 8 includes sixteen J-K flip-flops 280; i.e., as many flip-flops as there are data wires in bus 6. Each data wire is associated with one flip-flop and is connected to input 282 of AND gate 284 having a second input 286. Outputs of AND gates 284 are connected to the J input of flip-flops 280. The Q output is connected to input 288 of the two inputs of NOR gate 290. The second input 292 of NOR gates 290 receives in a cyclic manner an authorization signal from logic circuit 208, as shown in FIG. 13. In other words, inputs 292 each receive separate authorization signals, one after the other.

Outputs 294 of NOR gates 290 are connected to the transmitters E (202 as shown in FIG. 13) of supervisor 8. Outputs 294 of NOR gates 290 are also connected, on the one hand, to the K inputs of flip-flops 280 and, on the other hand, to the inputs of NAND gate 296 via inverters 298.

Each R input of flip-flops 280 is connected to switch 300 making it possible to connect the R input either to ground or to the output of NAND gate 302 which receives on its two inputs instruction INI and the bus signal PLS. Switches 300 indicate whether or not requests from the corresponding interfaces should be considered. If the R input of a flip-flop 280 is connected to ground, output Q is held in logic state 1 and, in this case, if an authorization signal should be present on input 292 of gate 290, the logic state of the output from gate 294 will remain at 0. Considering that a logic state 1 on this output means that the corresponding interface is selected, grounding of R input by switch 300 corresponds to disconnecting the interface corresponding to this flip-flop and data wire.

Each output Q of the flip-flops 280 is connected to one of the inputs of NAND gate 304 whose output is connected, via inverter 306, to one of the two inputs of AND gate 308. The second input of this gate receives instruction TAC. The output of gate 308 is connected in parallel to inputs 286 of AND gates 284.

The operation of strategy circuit 220 is the following: the initial state of output Q of flip-flop 280 is logic state 1 (permanent state if switch 300 grounds R input). When all Q outputs are in logic state 1 (this corresponds to no requesting devices), NAND gate 304 outputs logic state 0, which is inverted to logic state 1 by inverter 306 and applied to one of two inputs of AND gate 308. Instruction TAC then can enable AND gate 308 to output logic state 1 which enables one input to AND gates 284. If a request remains (the yet unauthorized device will have its flip-flop output Q still in logic state 0), at least one output Q will not be in logic state 1, causing NAND gate 304 output to be in logic state 1 and in turn AND gate input 286 to be in logic state 0.

This thereby disables input J to all flipflops 280 and prevents storage of further requests until all Q outputs are returned to state 1. At this time, instruction TAC brings all inputs 286 to enabling state 1 and flipflops 280 can again store the logic state present on their individual inputs 282. Thus, this TAC instruction has the meaning TACM shown in FIG. 16. The individual inputs 282 will be stored and reflected, in a negative sense, by the corresponding output Q, e.g., those having input 286=1 will have Q=0 and those with input 282=0 will have Q remain at state 1. In the above manner, J-K flip-flops 280 function as memory to store transmission requests when all previous requests have been authorized. The stored requests are reviewed and authorized one-by-one according to a priority, while at the same time, preventing new requests by different devices or the same device, from entering into the review until all stored requests are processed.

When a device requests to transmit, the logic state of its hachured transmitter (FIG.

7) is 1. When supervisor 8 transmits instruction TAC; i.e., when the supervisor checks for interfaces requesting to transmit, the hachured wire of an interface corresponds to a corresponding data wire of the bus, which is connected to input 282 of AND gates 284 of that wire. If a request is present, the output of AND gate 284, as well as the J input of flip-flop 280, will be logic state 1.

This state corresponds to logic state 0 of output Q of this flip-flop. If logic signal 0 (state of Q) is applied to input 288 of NOR gate 290 and if input 292 is also in logic state 0, output 294 is then in logic state 1, and the interface corresponding to this output 294 is then selected. Furthermore, application of output 294 in logic state 1 to the K input of flip-flop 280 changes its state and its output Q switches to state 1.

Signal BR obtained at the output of NAND gate 296 takes on logic state 0 when all outputs 294 are in logic state 0. It will be recalled that BR corresponds to requests remaining to be authorized. In this case, the supervisor continues to send instruction TAC along with an authorization signal to input 292. With each instruction TAC, a different device will be authorized by sending logic state 0 to the corresponding NOR gate 290. Because both inputs 292 and 288 of NOR gate 290 will be in logic state 0, its output will be state 1, signalling the selection of the corresponding interface, and when input to input K of flip-flop 280 changes its state and output Q from state 0 to 1, erasing the stored request. As long as stored transmission requests from the interfaces are not all satisfied, no additional storage takes place. If a current request remains, this means that output Q of at least one flip-flop 280 is in logic state 0. In this case, the output of NAND gate 304 is in logic state 1. The result is that the output of AND gate 308, as well as inputs 286 of AND gates 284, are in logic state 0. New transmission requests from the interfaces, corresponding to a logic state 1 applied to inputs 282, thus cannot be taken into account by flip-flops 280 and stored. On the other hand, when all the requests are satisfied, the Q outputs of flip-flops 280 are in logic state 1 and the result is logic state 0 at the output of NAND gate 304. When an instruction TAC is then applied to one of two inputs to AND gate 308, the output of this gate, and hence subsequent inputs 286 of AND gates 284, go over to logic state 1.

The result is that, at the moment the instruction TAC is transmitted, new transmission requests from the devices associated with the interfaces are stored by flip-flops 280, as was indicated by the notation TACM in FIG. 16.

The authorization signals applied to terminals 292 of NAND gates 290 can be obtained by any conventional means, for example, by means of integrated circuits of the 74 LS 42 and 74 LS 90 type.

FIG. 18 has been already mentioned in regard to the timing details of various circuit embodiments illustrated in other figures.

The differentiator circuit timing illustrated by FIGS. 18A-D occurs at several points in the interface as shown in FIGS. 11B-F, for example. The flip-flops whose input and output timing is illustrated by FIGS.

18E-M occurs also in these figures. These timing diagrams are merely exemplary aids to the description of these circuits. As the specific circuits shown are illustrative, the corresponding timing can also be expected to vary accordingly.

The present invention can be applied to many industrial uses and is applicable whenever digital data transmissions between several devices have to be carried out. As an example of an industrial application, the invention can be used in acquisition systems for data transmitted by devices located in logging sondes lowered into boreholes.

Obviously, the present invention is not limited to the illustrative embodiment described herein. In particular, where circuits using a positive or negative logic were described, it is understood that circuits implementing an opposite logic can be used. Likewise, by way of example, the number of words contained in a data file, as well as the number of bits contained in a word, were given only for illustrative purposes, it being understood that many variations are possible.

There has been described apparatus for transmitting digital information from an information source device to at least one receiver device selected from several devices interfaced to a common transmission bus.

Each device transmits asynchronously at its own rate, independent of the transmission rate of the bus. Each device having information to transmit first transmits at its own rate to its interface, and in particular to an associated memory within its interface.

When this transmission is complete, the device requests the transmission of the contents of this memory to specified receiving devices. A bus supervisor periodically polls the devices for such requests and determines which requesting device will act as an information source. Transmission is then initiated from the source-device associated memory along the bus at bus rates to memory(ies) associated with the specified receiver device(s). When this transmission is complete, transmission occurs from the receiver-associated memory(ies) to the receiving device(s) at rates and times particular to each receiving device. In this manner, maximum ,advantage is made of the transmission capability of the bus system.

WHAT WE CLAIM IS: 1. A digital information exchange system comprising a multiplicity of information sources and information transmitting means, said information sources including at least two emitting sources and at least one receiving source, and said information transmitting means interconnecting said information sources and including: a bus having transmission wires for transmitting both data and source control words; a multiplicity of interfaces, each of which connects an associated one of said information sources to said bus and is provided with a memory in which information to be transmitted from the associated source to said bus, or vice versa, can be temporarily stored, said information being stored in the memory in the form of an information file comprising at least one control or data word; and a supervisor connected to said bus for controlling the information transfer via said bus, said information being transmitted along said bus asynchronously with respect to said sources, wherein said supervisor comprises means for storing system operating instructions, each interface comprises means responsive to said system operating instructions, and said bus comprises instruction wires for transmitting instructions between said instruction storing means and said instruction responsive means, one of said instructions allowing said supervisor to check the interface of each emitting source simultaneously to determine whether it has a data file to transmit.

2. The system of claim 1, wherein at least one of said information sources is a computer.

3. The system of claim 1 or claim 2, wherein said information file includes several words each made up of the same number of bits.

4. The system of claim 3, wherein each information file includes the address of the source or the addresses of the sources to which said information file is to be sent.

5. The system of claim 4, wherein said addresses are contained in the same word, each of said sources corresponding to one of said bits constituting said word.

6. The system of any one of preceding claims, wherein said information file includes the indication of the number of words to be transmitted.

7. The system of any one of the preceding claims, wherein said supervisor in cludes: - reception means connected to said bus to receive signals transmitted by said interfaces; and - transmission means capable of being connected to said bus to send instructions to said interfaces; said means for storing the instructions being connected to said transmission means and said reception means and including a memory for storing and supplying said instructions, a logic circuit for selecting said instructions in said memory and a program counter incremented whenever an instruction is supplied to said transmission means.

8. The system of claim 7, wherein said supervisor further includes means for storing the number of words to be transmitted by information file, said number being included in one of the words of said information file supplied by the emitting source which has emitted the file, said means furnishing an end-of-file signal to said logic circuit when said number of words has been transmitted.

9. The system of any one of the preceding claims, further comprising a strategy logic circuit to determine an order of priority for connecting to said bus each of said interfaces having data to be transmitted at the same time, said strategy circuit comprising means for sequentially storing the requests from said interfaces which are in a condition to transmit at said instant, means for assigning an order of priority to said interfaces, and means for not taking into account any new data transmission request, at another moment, as long as said interfaces whose requests have been stored have not transmitted their data.

10. The system of claim 9, wherein said means for storing said requests from said interfaces which are in a condition to transmit include an assembly of J-K flip-flops, each corresponding to one of said interfaces and receiving on one of its two inputs a signal characteristic of the presence or of the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (19)

**WARNING** start of CLMS field may overlap end of DESC **. information source device to at least one receiver device selected from several devices interfaced to a common transmission bus. Each device transmits asynchronously at its own rate, independent of the transmission rate of the bus. Each device having information to transmit first transmits at its own rate to its interface, and in particular to an associated memory within its interface. When this transmission is complete, the device requests the transmission of the contents of this memory to specified receiving devices. A bus supervisor periodically polls the devices for such requests and determines which requesting device will act as an information source. Transmission is then initiated from the source-device associated memory along the bus at bus rates to memory(ies) associated with the specified receiver device(s). When this transmission is complete, transmission occurs from the receiver-associated memory(ies) to the receiving device(s) at rates and times particular to each receiving device. In this manner, maximum ,advantage is made of the transmission capability of the bus system. WHAT WE CLAIM IS:

1. A digital information exchange system comprising a multiplicity of information sources and information transmitting means, said information sources including at least two emitting sources and at least one receiving source, and said information transmitting means interconnecting said information sources and including: a bus having transmission wires for transmitting both data and source control words; a multiplicity of interfaces, each of which connects an associated one of said information sources to said bus and is provided with a memory in which information to be transmitted from the associated source to said bus, or vice versa, can be temporarily stored, said information being stored in the memory in the form of an information file comprising at least one control or data word; and a supervisor connected to said bus for controlling the information transfer via said bus, said information being transmitted along said bus asynchronously with respect to said sources, wherein said supervisor comprises means for storing system operating instructions, each interface comprises means responsive to said system operating instructions, and said bus comprises instruction wires for transmitting instructions between said instruction storing means and said instruction responsive means, one of said instructions allowing said supervisor to check the interface of each emitting source simultaneously to determine whether it has a data file to transmit.

2. The system of claim 1, wherein at least one of said information sources is a computer.

3. The system of claim 1 or claim 2, wherein said information file includes several words each made up of the same number of bits.

4. The system of claim 3, wherein each information file includes the address of the source or the addresses of the sources to which said information file is to be sent.

5. The system of claim 4, wherein said addresses are contained in the same word, each of said sources corresponding to one of said bits constituting said word.

6. The system of any one of preceding claims, wherein said information file includes the indication of the number of words to be transmitted.

7. The system of any one of the preceding claims, wherein said supervisor in cludes: - reception means connected to said bus to receive signals transmitted by said interfaces; and - transmission means capable of being connected to said bus to send instructions to said interfaces; said means for storing the instructions being connected to said transmission means and said reception means and including a memory for storing and supplying said instructions, a logic circuit for selecting said instructions in said memory and a program counter incremented whenever an instruction is supplied to said transmission means.

8. The system of claim 7, wherein said supervisor further includes means for storing the number of words to be transmitted by information file, said number being included in one of the words of said information file supplied by the emitting source which has emitted the file, said means furnishing an end-of-file signal to said logic circuit when said number of words has been transmitted.

9. The system of any one of the preceding claims, further comprising a strategy logic circuit to determine an order of priority for connecting to said bus each of said interfaces having data to be transmitted at the same time, said strategy circuit comprising means for sequentially storing the requests from said interfaces which are in a condition to transmit at said instant, means for assigning an order of priority to said interfaces, and means for not taking into account any new data transmission request, at another moment, as long as said interfaces whose requests have been stored have not transmitted their data.

10. The system of claim 9, wherein said means for storing said requests from said interfaces which are in a condition to transmit include an assembly of J-K flip-flops, each corresponding to one of said interfaces and receiving on one of its two inputs a signal characteristic of the presence or of the

absence of information in said interface, and wherein said means for not taking into account any information transmission request as long as said interfaces whose requests have been stored have not transmitted their information include a first AND gate having its inputs connected to the outputs of said flip-flops and a second AND gate having one input connected to the output of the first AND gate and the other input receiving a signal for taking into account the requests from interfaces having data to be transmitted.

11. The system of any one of the preceding claims, wherein at least one of said interfaces comprises a "listener" part including an information reception circuit connected permanently to said bus, a memory having its inputs connected to said reception circuit and its outputs connected to the source to which said interface is assigned, means for indicating the content of said memory, and means for authorizing or prohibiting the writing of information in said memory.

12. The system of any one of the preceding claims, wherein at least two of said interfaces comprises a "talker" part including an information transmission circuit capable of being connected to said bus, a memory having its inputs connected to the source to which said interface is assigned and its outputs connected to said transmission circuit, means for indicating the content of said memory, and means for authorizing or prohibiting the transfer of the content of the memory toward said bus.

13. The system of either of claims 11 and 12, wherein at least one of said interfaces includes a "listener" part and a "talker" part.

14. The system of any one of claims 11 to 13, further comprising means for selecting the addresses in said memories.

15. The system of any preceding claim, comprising two such buses each connected to a respective such supervisor, and, via respective such interfaces, to respective such information sources, and further comprising an intermediate interface connecting said two buses to each other, said intermediate interface comprising means for receiving the information from an emitting source of one of said two buses under the control of the supervisor of said one of said two buses and for transmitting said information to one or more receiving sources of the other of said two buses under the control of the supervisor of said other of said two buses.

16. A method for transmitting digital information between at least two information emitting sources and at least one information receiving source via a bus, comprising the steps of: assigning a supervisor to the bus; assigning a respective memory to each of said sources; writing the information from each source having information to transmit into the memory which is assigned to that source, under the control of that source; causing said supervisor to check the memory assigned to each said information emitting source simultaneously to determine whether it has information to transmit; transferring the information thus written via said bus to the memory or memories assigned to the source or sources to which the information is addressed, under the control of said supervisor; and transferring the information thus received to the source or sources to which the receiving memory or memories is or are assigned, under the control of the receiving source; wherein an order of priority is determined for the transfer of said information via said bus with the application of a strategy.

17. The method of claim 16, wherein said strategy comprises the steps of: (a) determining at a given moment and storing the memories having informa tion to be transmitted and the sources to receive said information; (b) assigning to each of said memories having information to be transmitted an order of priority depending on a predetermined order and on the avail ability of the addressee(s); and (c) not performing a new determination as defined in step (a) as long as all the memories of step (b) have not transmitted their information.

18. A system for transmitting digital information between at least two information emitting sources and at least one receiving source comprising at least one bus, the transmission taking place asynchronously with respect to said sources, the system being substantially as herein described with reference to the accompanying drawings.

19. A method for transmitting digital information between at least two information emitting sources and at least one receiving source via at least one bus, the method being substantially as herein described with reference to the accompanying drawings.