GB1591148A

GB1591148A - Circuit arrangement for evaluating a digital pulse train

Info

Publication number: GB1591148A
Application number: GB713778A
Authority: GB
Original assignee: Licentia Patent Verwaltungs GmbH; Licentia Oy
Current assignee: Licentia Patent Verwaltungs GmbH; Licentia Oy
Priority date: 1977-02-22
Filing date: 1978-02-22
Publication date: 1981-06-17
Also published as: DE2707610C3; DE2707610B2; DE2707610A1

Description

(54) CIRCUIT ARRANGEMENT FOR EVALUATING A DIGITAL PULSE TRAIN (71) We, LICENTIA PATENT VER- WALTUNGS G.M.B.H., of 1 Theodor Stern-Kai, 6 Frankfurt/Main 70, Federal Republic of Germany, a German body corporate, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a circuit arrangement for evaluating a digital pulse train.

Digital pulse trains are preferably used today when transmitting information since this type of signal can be transmitted comparatively simply and processed.

Information to be transmitted selectively from a central station to separate personal call receivers is transmitted in the form of digital signals for example in radio personal call systems, whereby a respective low characteristics frequency is transmitted as a characteristic for each of the two digital conditions. In order to safeguard the information to be transmitted against transmission faults and from interference during transmission the information to be transmitted is represented as specific code words for which special recognition circuits are provided in the receiver in order to correctly recognize them. In this way incorrect information is substantially eliminated.

However, it has been shown that for example because of the non-ideal refinement of the receiving devices and because of the influence on the receivers of the noise, which is connected therewith, apparently correct information is also received even if this information is not sent out from the central transmitter of the personal call system.

In order to suppress these faults it is possible to precede the useful signals by a pretrigger pulse which is longer than most apparent useful pulses which may arise.

The invention seeks to create a circuit which can be simply produced in order to evaluate digital pulse trains provided with a pre-trigger pulse.

According to one aspect of the invention, there is provided a circuit arrangement for evaluating a digital pulse train having an initial pulse of predetermined length, the arrangement comprising a retriggerable monostable trigger stage to the set input of which the pulse train is fed so that a front flank will trigger it and which has a time span in its unstable state shorter than the length of the initial pulse and a resettable linking circuit which provides a control signal and is formed by a D-trigger stage to the clock input of which the pulse train is fed and to the D-input of which an output of the monostable trigger stage is connected such that the D-trigger stage may be set by the rear flank of an initial pulse, an output of the D-trigger stage being connected to the blocking input of the monostable trigger stage to block it when an initial pulse has been detected.

In order that the invention and its various other preferred features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the drawings, in which: Figure 1 shows a block diagram of a personal call receiver constructed in accordance with the invention, Figure 2 shows pulse diagrams for explaining operation of the receiver of Figure 1.

In Figure 1 a receiver for a personal call system is represented as a block circuit diagram as an example of application of the invention. The personal call system operates with digitally coded signals whereby a respective low-frequency characteristic frequency is assigned to each of the two digital conditions in a central transmitter of the personal call system. A high-frequency carrier signal is modulated by the two characteristic frequencies for the purpose of radio transmission.

The carrier frequency signal mentioned is received by an antenna 1 of the personal call receiver. A low-frequency signal is derived at the output of an input stage 2 fed by the antenna 1 having an amplifier and a demodulator, and this signal is supplied to a band-pass filter 3. The band-pass filter 3 is arranged so that it just permits the passage of a frequency spectrum containing the two characteristic frequencies. The frequency mixture obtained in this way is supplied to a digital demodulator 4 which is constructed so that it produces digital signals 5 at its output depending on the characteristic frequencies mentioned.

The digital pulse train 5 contains the information which was transmitted, in coded form. A decoder 6 serves for decoding of the pulse train 5 and supplies, via its output ]0 and via a separating amplifier 11, a loudspeaker 12 and/or a display unit 13 for reproducing the transmitted information.

The decoder 6 is constructed so that it only evaluates those pulse trains which the transmitter can produce. Therefore incor rect pulse trains are not evaluated at all. The decoder 6 can therefore distinguish to a certain extent between authentic and incorrect pulse trains. Similarly it is not possible initially to prevent apparently correct information at the input 7 of the decoder 6 from appearing because of transmission faults or because of interference signals.

In order to ensure that the decoder 6 only recognizes as correct those pulse trains 5 which with a great degree of probability were sent out as those pulse trains from the central transmitter of the personal call system are provided with a pre-trigger pulse of a certain minimum length.

In order to recognize the correct pulse trains characterized in this way a circuit arrangement is provided having a D-bistable trigger stage 1 5 and a monostable trigger stage 21. The output signal of this circuit arrangement with the 1)-bistable trigger stage 15 and the monostable trigger stage 21 is supplied to a control input 8 or the decoder 6. The decoder 6 is constructed so that it only decodes a pulse train when it has been triggered at the control input 8.

The pulse trains to be processed by the decoder 6 are constructed so that the decoder 6 can recognize the end of a correct pulse train. A control signal then appears at the auxiliary output 9 of the decoder 6.

The circuit mentioned and provided for control of the decoder 6 comprises the D-bistable trigger stage 1 5 with a D input 16, a "clock" input 17, a R ("reset") input 20 and a non-inverting Q output 19 and an inverting Q output 18. The bistable trigger stage 15 is constructed in known manner so that a jump from "0" to "1" at its input 17 only permits a "1" to appear then at the output 1 9, if a "1" is present at the input 16 of the bistable trigger stage 15. The bistable trigger stage 15 can be reset by the input 20 i.e. a "0" appears at the output 19, if a "1" is applied to the input 20.

The monostable trigger stage 21 can be retriggered and is otherwise constructed as is usual, i.e. after triggering of the monostable trigger stage 21 by a jump from "0" to "1" at the "clock" input 22, a "1" appears at its Q output which is not connected in the circuit shown, for a predetermined (unstable) period of time. If a further trigger signal appears at input 22 during the unstable period of time then this period of time begins again from the last trigger signal. If a "1" is present at the R ("reset") input 24 of the monostable trigger stage 21 then this means that the monostable trigger stage cannot be triggered and that a "1" is present therefore at its Q output 23.

The assemblies described above with the bistable trigger stage 1 5 and the monostable trigger stage 21 are connected together as follows. The pulse train 5 to be evaluated is connected on the one hand direct to the input 22 of the monostable trigger stage 21 and on the other hand via an inverter 14 to the input 17 of the bistable trigger stage 15.

The output 23 of the monostable trigger stage 21 is connected to the input 16 of the bistable trigger stage 15. The output 19 of the bistable trigger stage 15 is connected on the one hand to the control input 8 of the decoder 6 and on the other hand to the input 24 of the monostable trigger stage 21.

The input 20 of the bistable trigger stage 15 is finally connected to the auxiliary output 9 of the decoder 6.

The circuit described operates as follows.

If a jump appears from "0" to "1" in the pulse train 5 then the monostable trigger stage 21 is triggered by this jump via its input 22 so that a "ü" appears at the output 23 of the monostable trigger stage 21. The jump mentioned from "0" to "1" does not have any effect on the bistable trigger stage 15 since this jump appears at the input 17 of the bistable trigger stage 15 as a jump from "1" to "0" because of the inverter 14. During the time predetermined by the periodic time of the monostable trigger stage 21 a "0" remains at the input 16 of the bistable trigger stage 15. This means that a jump from "0" to "1" at the input 17 of the bistable trigger stage 15 will make no change during the mentioned period of time itself since a "0" was present previously at the output 19 of the bistable trigger stage 15 and with the mentioned jump from "0" to "1" at the input 17 only the digital value (here a "0") present at the input 16 can be transmitted to the output 19.

During the condition described the mentioned "0" at the output 19 of the bistable trigger stage 15 is connected at the same time at the control input 8 of the decoder 6 thus the decoder does not evaluate the pulse trains 5 appearing at its input 7.

The periodic time that the monostable trigger stage 21 stays in its unstable state is selected so that it is shorter than the pretrigger of a correct digital pulse train of useful signals which is described above. Thus it follows that all of the interference signals which are shorter than the periodic time of the monostable trigger stage 21 are not decoded from the outset by the decoder 6.

Only if a pulse of the pulse train 5 is longer than the periodic time of the monostable trigger stage 21 can the bistable trigger stage 15 be switched and thus the decoder 6 can be connected. This is explained by the fact that in the case of a pulse having a longer period of time than the unstable period of time of the monostable trigger stage 21 this monostable trigger stage trips back after the period of time mentioned and thus a "1" appears at the output 23 or the monostable trigger stage 21 and accordingly also at the input 16 of the bistable trigger stage 15. If the said pulse of the pulse train 5 terminates now, i.e. passes from "1" to "0" then this causes, because of the inverter 14, a jump from "0" to "1" at the input 17 of the bistable trigger stage 15. Thus the "1" present at the input 16 of the bistable trigger stage 15 is passed on to the output 19.Thus a signal connecting this decoder appears at the control input 8 of the decoder 6, i.e. the "1".

The process described is explained in greater detail together with the pulse diagrams in Figure 2. Figure 2a shows the example of the pulse train 5 in Figure 1. The pulses shown change between the digital values of "0" and "1". During the first pulse 25 no pulse arises which is longer than the unstable period of time of the monostable trigger stage 21. This period of time is designated At in Figure 2b. With the first jump from "0" to "1" of the pulse 25 or with a preceding and corresponding jump the monostable trigger stage is set i.e. a jump from "1" to "0" appears at its output 23 as is shown in Figure 2b. By each successive jump from "0" to "1" of the pulse train 25 in Figure 2a the monostable trigger stage 21 is retriggered.In the example assumed in Figure 2a this takes place lastly at the beginning of the pulse 26 which is longer than the unstable period of time At of the monostable trigger stage. After expiry of the period of time At the monostable trigger stage 21 flops back so that a"1" appears at is output 23 as is shown by the pulse 28 in Figure 2b. If the end of the pulse 26 in Figure 2a then appears this causes switching of the bistable trigger stage 15 so that a "1" appears at the output 19 of the bistable trigger stage 15 as is shown by the pulse 29 in Figure 2c. The pulse 29 at the output 19 of the bistable trigger stage 15 serves as a switching signal for the decoder 6 in Figure 1. In this way it is ensured that the useful pulse 27 following subsequent to the pulse 26 in Figure 2a actually is decoded by the decoder 6 or can be recognized.The pulse 29 at the output 19 of the bistable trigger stage 15 furthermore serves to block the monostable trigger stage 21 via its input 24.

This blocking of the monostable trigger stage 21 during a "recognized" useful pulse train prevents a jump from "0" to "1" in the useful pulse train from triggering the monostable trigger stage in an undesirable manner which would cause disconnection of the decoder 6 via its input 8.gbove 8.

As already described above the decoder 6 is constructed moreover so that it can recognize the end of a useful pulse train. If a "1" then appears accordingly at the end of this useful pulse train at the auxiliary output 9 of the decoder 6 then this signal causes the bistable trigger stage 15 to switch over at the input 20 of the bistable trigger stage 15 so that a "0" appears again at the output 19 and on the one hand the decoder 6 is disconnected via its control input 8 and on the other hand the monostable trigger stage 21 previously blocked during the useful pulse train via the input 24 is released again. The monostable trigger stage 21 can then be triggered again by a jump from "0" to "1" at its input 22. Thus the circuit described is then prepared again to recognize and evaluate a useful pulse train in the pulse train 5.

The inverter 14 in front of the input 17 of the bistable trigger stage 15 can be dispensed with if its function is taken over by the input circuit of the input 17 of the bistable trigger stage 15. In the case where the input 16 of the bistable trigger stage 15 has inverting properties this input must be connected instead of to the Q output 23 of the monostable trigger stage 21 to its Q output.

Furthermore it is possible to trigger the decoder 6 with the output 18 instead of with the output 19 of the bistable trigger stage 15.

The unstable period of time At of the monostable trigger stage 21 is selected advantageously so that it is slightly longer than the half time period of the pretrigger 26 in Figure 2a. If, when using the circuit arrangement in accordance with the invention in a personal call system of the type described a band filter is used corresponding to the band filter 3 with a certain lower limit frequency then it is advantageous to select the unstable period of time of the monostable trigger stage 21 at least as long as the period duration corresponding to the lower limit frequency of the band-pass filter 3.

Application of the circuit arrangement in accordance with the invention is not limited to a personal call system of the type described. But rather it can be applied anywhere pulse-shaped signals are to be evaluated and where a pretrigger pulse of a predetermined length is assigned to a pulse train for recognition of useful signals.

WHAT WE CLAIM IS: 1. A circuit arrangement for evaluating

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. follows that all of the interference signals which are shorter than the periodic time of the monostable trigger stage 21 are not decoded from the outset by the decoder 6. Only if a pulse of the pulse train 5 is longer than the periodic time of the monostable trigger stage 21 can the bistable trigger stage 15 be switched and thus the decoder 6 can be connected. This is explained by the fact that in the case of a pulse having a longer period of time than the unstable period of time of the monostable trigger stage 21 this monostable trigger stage trips back after the period of time mentioned and thus a "1" appears at the output 23 or the monostable trigger stage 21 and accordingly also at the input 16 of the bistable trigger stage 15. If the said pulse of the pulse train 5 terminates now, i.e. passes from "1" to "0" then this causes, because of the inverter 14, a jump from "0" to "1" at the input 17 of the bistable trigger stage 15. Thus the "1" present at the input 16 of the bistable trigger stage 15 is passed on to the output 19.Thus a signal connecting this decoder appears at the control input 8 of the decoder 6, i.e. the "1". The process described is explained in greater detail together with the pulse diagrams in Figure 2. Figure 2a shows the example of the pulse train 5 in Figure 1. The pulses shown change between the digital values of "0" and "1". During the first pulse 25 no pulse arises which is longer than the unstable period of time of the monostable trigger stage 21. This period of time is designated At in Figure 2b. With the first jump from "0" to "1" of the pulse 25 or with a preceding and corresponding jump the monostable trigger stage is set i.e. a jump from "1" to "0" appears at its output 23 as is shown in Figure 2b. By each successive jump from "0" to "1" of the pulse train 25 in Figure 2a the monostable trigger stage 21 is retriggered.In the example assumed in Figure 2a this takes place lastly at the beginning of the pulse 26 which is longer than the unstable period of time At of the monostable trigger stage. After expiry of the period of time At the monostable trigger stage 21 flops back so that a"1" appears at is output 23 as is shown by the pulse 28 in Figure 2b. If the end of the pulse 26 in Figure 2a then appears this causes switching of the bistable trigger stage 15 so that a "1" appears at the output 19 of the bistable trigger stage 15 as is shown by the pulse 29 in Figure 2c. The pulse 29 at the output 19 of the bistable trigger stage 15 serves as a switching signal for the decoder 6 in Figure 1. In this way it is ensured that the useful pulse 27 following subsequent to the pulse 26 in Figure 2a actually is decoded by the decoder 6 or can be recognized.The pulse 29 at the output 19 of the bistable trigger stage 15 furthermore serves to block the monostable trigger stage 21 via its input 24. This blocking of the monostable trigger stage 21 during a "recognized" useful pulse train prevents a jump from "0" to "1" in the useful pulse train from triggering the monostable trigger stage in an undesirable manner which would cause disconnection of the decoder 6 via its input 8.gbove 8. As already described above the decoder 6 is constructed moreover so that it can recognize the end of a useful pulse train. If a "1" then appears accordingly at the end of this useful pulse train at the auxiliary output 9 of the decoder 6 then this signal causes the bistable trigger stage 15 to switch over at the input 20 of the bistable trigger stage 15 so that a "0" appears again at the output 19 and on the one hand the decoder 6 is disconnected via its control input 8 and on the other hand the monostable trigger stage 21 previously blocked during the useful pulse train via the input 24 is released again. The monostable trigger stage 21 can then be triggered again by a jump from "0" to "1" at its input 22. Thus the circuit described is then prepared again to recognize and evaluate a useful pulse train in the pulse train 5. The inverter 14 in front of the input 17 of the bistable trigger stage 15 can be dispensed with if its function is taken over by the input circuit of the input 17 of the bistable trigger stage 15. In the case where the input 16 of the bistable trigger stage 15 has inverting properties this input must be connected instead of to the Q output 23 of the monostable trigger stage 21 to its Q output. Furthermore it is possible to trigger the decoder 6 with the output 18 instead of with the output 19 of the bistable trigger stage 15. The unstable period of time At of the monostable trigger stage 21 is selected advantageously so that it is slightly longer than the half time period of the pretrigger 26 in Figure 2a. If, when using the circuit arrangement in accordance with the invention in a personal call system of the type described a band filter is used corresponding to the band filter 3 with a certain lower limit frequency then it is advantageous to select the unstable period of time of the monostable trigger stage 21 at least as long as the period duration corresponding to the lower limit frequency of the band-pass filter 3. Application of the circuit arrangement in accordance with the invention is not limited to a personal call system of the type described. But rather it can be applied anywhere pulse-shaped signals are to be evaluated and where a pretrigger pulse of a predetermined length is assigned to a pulse train for recognition of useful signals. WHAT WE CLAIM IS:

1. A circuit arrangement for evaluating

a digital pulse train having an initial pulse of predetermined length, the arrangement comprising a retriggerable monostable trigger stage to the set input of which the pulse train is fed so that a front flank will trigger it and which has a time span in its unstable state shorter than the length of the initial pulse and a resettable linking circuit which provides a control signal and is formed by a D-trigger stage to the clock input of which the pulse train is fed and to the D-input of which an output of the monostable trigger stage is connected such that the D-trigger stage may be set by the rear flank of an initial pulse, an output of the D-trigger stage being connected to the blocking input of the monostable trigger stage to block it when an initial pulse has been detected.

2. A circuit arrangement according to Claim 1 for triggering a decoder for evaluating the pulse train, in which an input switch of the decoder is connected to an output of the D-trigger stage and a reset input of the D-trigger stage is connected to a circuit for recognizing the end of a useful pulse train to be evaluated.

3. A circuit arrangement according to Claim 2 in which the pulse train to be evaluated is connected direct to a setting input of the monstable trigger stage and via an inverter to the clock input of the D-trigger stage.

4. A circuit arrangement according to any one of the preceding Claims, in which an inverting output of the monstable trigger stage is connected to the I D-input of the D-trigger stage.

5. A circuit arrangement according to Claim 2, in which the output of the D-trigger stage connected to the input switch of the decoder is formed by the noninverting output of the D-trigger stage.

6. A circuit arrangement according to Claim 1 for a selective call receiver for receiving digital information which is transmitted, modulated on a high frequency carrier, by a transmitter, the circuit arrangement having a filter with a lower limit frequency connected in advance of a circuit for transforming two characteristics frequencies into digital pulses, in which the unstable time period of the monostable trigger stage is longer than the period corresponding to the lower limit frequency of the filter.

7. A circuit arrangement according to any one of Claims 1 to 6, in which the unstable time period of the monostable trigger stage is slightly longer than half the time period of the initial pulse.

8. A circuit arrangement for evaluating a digital pulse train substantially as described herein with reference to the drawings.