GB1590892A - Pulse supply system - Google Patents

Description

(54) PULSE SUPPLY SYSTEM (71) We, Societe' Anonyme dite COM PAGNIE INDUSTRIELLE DES TELE COMMUNICATIONS CITALCATEL, a French Body Corporate of, 12 Rue de la Baume, 75008 Paris, France, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention concerns a system for the supply of electrical current pulses of different characteristics, such as variously used for fee charging rate determination and the timing of various operations and functions. It is applicable in the electrical and electronic engineering industries, and particularly in telecommunications engineering, as a supply of pulses in switching centers for use by incurred charge metering and supervisory circuits.

There is a number of known pulse supplies. In electro-mechanical exchanges, ringing and tone machines have mains-powered motors, which operate a set of mechanical cams to open and close contacts, and thus to determine a number of pulse durations and intervals. There are also electronic pulse supply systems comprising oscillator-driven scalers, which by division and combination produce the required pulses from a basic pulse rate.

All these known systems have the disadvantage of not permitting changes in pulse rates, durations, or spacing without making changes in wiring, and/or mechanical adjustments. Further, the amount of equipment they must comprise increases with the number of "cams" i.e. pulse trains to be made available without the abovementioned rewiring or mechanical changes.

The purpose of the invention is to provide a variable pulse supply with the minimum equipment necessary to obtain the various timing or metering rates simultaneously required in a telecommunications switching center, and permitting changes in pulse characteristics by simple, manually operated means, such as plugs, push-buttons, keyfields, and similar devices.

The present invention provides a pulse supply system for simultaneously providing a plurality of different pulse streams each at individually settable pulse rates and pulse durations, the system comprising a clock, and a sequential control circuit driven by the clock and controlling both time counting means and address counting means, the time counting means serving to provide an output interface with "pulse on" and with "pulse off" signals for each of a plurality of different pulse streams, and the address counting means serving to count simultaneously through addresses in both of two data stores, the first data store comprising an electrically alterable memory of the time counting means, and the second data store comprising marking means for setting data significant of a pulse repetition rate and of a pulse duration in each of a plurality of addresses, said data being in the form of a period word and a duration word with said period word being manually alterable, the pulse supply system further comprising a logic unit associated with the time counting means and arranged to operate at each address count under the control of a cycle counter to compare the value stored in the electrically alterable memory at that address count with an end value, and if the stored value is equal to the end value to provide the output interface with one of said "pulse on" and "pulse off" signals and to load the data from the corresponding address in the marking means into the memory, and if the stored value is different from the end value to change the stored value by a unit step in the direction of said end value.

Preferably the electrically alterable memory is divided into two fields, one containing words determining pulse periods, and the other containing words determining pulse durations.

An embodiment of the invention is described by way of example, with reference to the accompanying drawings, which represent: Figure 1: the general organization of a system embodying to the inven tion Figure 2 : the sequential control and pulse test circuits; Figure 3: a sequential control timing diagram; Figure 4 : the addressing circuit, compris ing an address counter and a cycle counter; Figure 5 : the storages, plug-in diode array matrix, logic circuits and interfaces; Figure 6 : an operation monitoring cir cuit; Figure 7: a timing diagram of monitor operation; Figure 8 : a embodiment of the invention of high reliability.

The embodiment of the invention described is a system simultaneously supplying 32 different pulse trains, each being adjustable in period between 0.1 and 409.5 seconds, in steps of 100 milliseconds. Pulse duration is determined by wiring and is common to all trains. Of these pulse trains, 16 have repetition rates that are determined to remain unchanged, as in application of a single rate for incurred fee charging by a charge metering system, whereas the 16 others may be switched to one of three repetition rates by an external control, as in application of a normal, a reduced, and a "night" rate by a charge metering system.

The system is composed essentially of the following, represented in figure 1 - a memory M of 32 16-bit words capacity, accessed by an addressing circuit CAD, which comprises an address counter operating in a 10 millisecond cycle ; each memory location can contain two words, a 12-bit "period" word, and a 4-bit "dura tion" word; - a 32 word-line x 12 sense-line array MD (matrix) designed to receive plug-in diodes at line intersections, for determina tion of pulse periods in steps of 100 mil liseconds; - an arithmetic and logic circuit AL for memory word writing and reading, output interface control, and input interface read ing; - a pulse output interface IS, with a demul tiplexer DX3 (see figure 5) under the con trol of addressing circuit CAD; - an input interface IE with a multiplexer MX (see figure 5) under the control of addressing circuit CAD, for testing of the status of external devices using or oper ated by the pulses, such as a contact of a charging system relay; and - a sequential control circuit SQ driven by a time-base, to step addressing circuit CAD, and delivering 16 clock phases S0 to S15 for sequential control of logic unit AL, memory M, and output interface IS. SQ also comprises circuits for the testing of selected pulses in step by step operatlon, by means of a test panel TC.

In summary, operation of the system is as follows : a "period" word location CP, is initialized at each period of the pulse train to which it is allocated by loading it with the complement of the value written by the diodes plugged into the word-lines of the matrix array MD, but the corresponding "duration" word location location T is not loaded. For the first 16 locations (fixed rate fee charging) the period word CP is reduced by 1 at 100 millisecond intervals (i.e. at every 10th cycle of the address counter A), while the remaining 16 locations (variable rate fee charging) are reduced at intervals of say 100, 150, or 200 ms, according to the fee charging rate applied at that time of day (automatic rate-switched charge metering). When CP reaches zero, an output signal appears at the output interface and the "duration" location T is loaded with a value of between 1 and 24, determining pulse duration in increments of 10 milliseconds. This content is reduced by 1 at each subsequent address counter cycle, and the signal applied to the pulse output to which T is allocated is cut off when the count reaches a certain value, such as 1.

Now follows a detailed description of the structure and operation of all parts of the system.

Please refer to figure 2 : the time-base comprises oscillator OS1 generating output t at 227 kHz which is fed through a number of gates to counter C1, which divides its input by 4 and drives a 16-bit binary counter C2, of which the outputs Q1 to Q4 drive a demultiplexer DX1. The 16 outputs sO to s15 of the demultiplexer DX1 deliver the signals used for the timing of the pulse on which an address - counter CA operates, the latter being stepped by output s15 (see figure 4).

The 32-step cycle of the address counter CA is therefore determined as follows 4 227x 16x 32 9ms The length of a double cycle is brought to 20 ms by inhibiting oscillator OS1 with 50 Hz generator Ge, connected to 220 volt mains.

Please refer to figure 3 : oscillator OS1 is inhibited at the end of the substract counters cycle (figure 4) on the fall of output Q16, of binary weight 16, of the address counter CA when the output of generator Ge is 1.

The oscillator is re-enabled when the output of Ge reverts to 0. To obtain this, AND gate P1 through which the oscillator signal t passes is controlled by the inverted output Q of flip-flop B1 (type D) s e t by the falling edge of output Q 16 from substract counter CA, via inverter I1. Flip-flop B 1 is cleared by the generator Ge through an inverter I2 and an OR gate P3.

A standby oscillator OS2 is provided as a safeguard against 50 cycles mains failure or failure of oscillator OS1. The frequency of OS2 is less than that of OS1 (9/lOths of its value, for example) so as to obtain a 10 millisecond cycle on the address counter CA without inhibition as by Ge.

A mains failure is detected by a counter C3, driven by the address counter CA (output Q16) and cleared at each cycle of the generator Ge. After 16 steps, for example, of counter C3 (about 150 ms it is blocked (by inverter I3 and AND gate PH), cutting off the output of oscillator OS1 by inhibiting OR gate P2 and preventing the setting of B1 through OR gate P3. Step 16 of the counter enables AND gate P4, to provide access to AND gate P1 of the output of the standby oscillator OS2. Signal FG ("failed generator") appear at the output of gate P2.

A similar arrangement, comprising a counter C4 and control gates P5 and P6, with an inverter I4, cuts in the standby oscillator OS2 on failure of oscillator OS1.

Figure 4 represents addressing circuit CAD, which comprises the address counter CA with its outputs 1 to 16 (Q1 to Q16) for addressing the memory M, the plug-in diode array MD, and the input and output interfaces (IS and IE). The clock input H of the address counter CA is the output s15 of the demultiplexer DX1 via an AND gate P12. At each cycle of the address counter CA, a pulse steps two cycle counters CC1 and CC2. Cycle counter CC1 is allocated to the 16 fixed rate metering pulses : its clock input is output Q16 of the address counter CA via an OR gate P13, and its binary outputs Q are fed to decoder DC1, which develops an output X1 on each tenth input clock pulse, and consequently at every tenth cycle of the address counter CA. Similarly, cycle counter CC2, allocated to the 16 variable rate metering pulses, is driven by output Q16 of the address counter CA via an inverter I3 and an OR gate P14, with a decoder DC2 at the outputs of the cycle counter CC2 delivering an output X2 every 10,15, or 20th cycle or counter CA, according to the metering rates T1, T2, T3 marked on an input group EX of the decoder, which may be connected (for example) to an automatic rate-switching (multi-fee) clock system.

Memory M is shown in figure 5 in four blocks M1 to M4. Blocks M1 and M2 contain respectively the "period" word CP and the "duration" word T for pulses 1 to 16, and blocks M3 and M4, the corresponding words CP and T of pulses 17 to 32. Each block has groups of connecting points for addressing A, for input E, for output S, and for enabling input V; and a write enabling input W.

The addressing (Q1 to Q16 , enabling (s4, s8), and write (X1, X2), commands of these blocks are controlled by a gating circuit CV as follows a) at each sequential control circuit cycle - instant s4 : read block M2 or M4 (word T of the pulse output addressed at Q 1 to Q16 - instant s8 : write the word read at instant s4; b) every 10,15, 20 cycles (X1 orX2 = 1) - instant s4 : read block M1 or M3 (word CP) - instant s8 : write word CP.

For enhanced reliability, a second memory MA, identical to the first M, is loaded, read, and addressed in step with the first.

Words CP and T for the metering pulse addressed and read at instant S4 are loaded into a 16-bit register RG1, enabled at W at instant s4, and cleared at R at instant st.

Similarly, the words read from memory MA are lodged in register RGA. A comparator CM connected at the outputs of these registers, will deliver a "failed" memory signal Fm if there is a discrepancy between the two memories at read instant (s4) and a display AF1 connected at the outputs of memory M then shows the number of the rate metering pulse involved.

The arithmetic and logic circuit AL comprises 2 adders AD1, AD2, for reduction of word CP and word T respectively (by addition of 1 to their complement). Output S of adder AD 1 is connected to the inputs of memories M1 to M3 : the words are complemented at S of the memories and S of the adders, as all these output are inverted. Output S1 or register RG1 (word CP) is connected to the input of adder AD1 by a set of AND gates PE1, for loading into memory from diode array MD, which has 12-senselines connected each to positive supply across a resistor (positive = 1). The 32 word-lines of the array eO to e3 1 are connected to the outputs of demultiplexer DX2 and display AF2. Demultiplexer DX2 is addressed by address counter CA (outputs Q1 to Q16) putting negative (negative = 0) on the addressed output. The sense-lines of the diode array are connected to the inputs of the set of gates Pre 1. Diodes are plugged into the sense-word intersections along the CP word line for a metering pulse, according to the bits in the word desired to be l's.

Demultiplexer DX2 is enabled by output Q of a type D flip-flop B2, the input D of the latter being connected to the output of the set of AND gates PE1, connected at output S1 of register RG1. The flip-flop is cleared at instant st and clocked at instant s6.

Operation is as follows: At the end of a metering pulse or when it is to be sent, the corresponding word CP is empty (0's). Outputs S1 of register RG1 go to 1 at instant s4, and demultiplexer DX2 is enabled at instant s6 by gate PE2 and flipflop B2. The word plugged into the word line of the diode array MD is incremented and complemented by adder AD 1 and written in memory at instant s8.

- for a pulse being formed, and when the CP word must be incremented (X1 or X2 = 1), the complemented word is loaded into register RG1 at instant s4. Outputs St of the register are connected to adder AD 1 by gate PE1, since all the diode array sense-lines are 1, demultiplexer DX2 not having been enabled.

The interfaces are controled by circuit CT, shown in figure 6, which loads word T into memory, when CP is back to 0.

Word T is loaded into register RG2 (figure 6) of which inputs D are connected to a fixed polarity supply PF. the loading command CH is the output of an AND gate P8, enabled at instant s7. An input P of gate P8 is connected to the output of an AND gate P7 (figure 5), which is enabled by the outputs of gates PE2, and that of a group of AND gates PE3, through inverter I4. Gates PE3 are connected to the diode array sense-lines. The register is therefore loaded at instant s7, subject to the dual condition that word CP = 0, (outputs st of RG1 = 1), and that a pulse interval is marked on the diode array, so as not to write the T word if the corresponding metering pulse is not used.

Register RG2 is reset at instant st. The output group S of the register is connected to the first inputs of a set of 4 OR gates PO, with 2 inputs each. The second inputs of these gates are connected to the outputs S2 of register RG1, at which bits tO to t3 of the complemented word T appear. The outputs of these OR gates are connected to inputs El of adder AD2. When input E2 of AD2 is lit adds 1 to the binary word received at El.

Input E2 is connected to the output of an OR gate P9, with 3 inputs connected to the bit wires tl, t2, t3. Consequently, the adder is inoperative, until the word T has been loaded into register RG2.

For control and supervision of the interfaces, circuit CT shown in figure 6 comprises gating logic LP, to which bits t0 to t3 are applied. In the example described, the charge metering system relay is operated by pulses of 120 ms. Polarities PF at the input register RG2 register the value 13, so that the relays, as indicated, are energized during twelve ten-millisecond cycles. Logic LP delivers two types of signal: - command K, to the output interface, during the count-down from 13 to 2 of word T (the corresponding logic equation is K = tlts t3 x (tl + t2 + t3).Please refer to figure 7.

- A supervisory inhibiting command hs.

Supervision is performed by comparator CM2, which compares the status of command signal K with the status of the corresponding relay, as indicated by input interface IE (wire Y). Supervision is inhibited for 20 ms after appearance of the command level K, and for 20 ms after its removal, i.e. during the count 13-12 and 1-0 of word T. The logic equation is hs = tt (t2.t3 + t2.t3).

A "failed register" signal appears at output FR of AND gate P10 which has 3 inputs: - one connected to output hs of LP - one connected to the comparator output, which is = 1 when K = Y - one connected to the inverted output of flip-flop B3, of type D cleared (0) during instants s5 to s15.

The pulses appearing at the outputs of output interface IS are applied by flip-flops type D ZO to Z31 (figure 5), which are clocked by demultiplexer DX3, and receive their inputs in common from command output K of circuit CT.

The device described also has means for the testing of the system in step-by-step operation.

The metering pulse to be tested is selected and displayed on the control panel, its address coded in binary by coder CD, and applied to the data input D of address counter CA (figure 4). The loading command input CH of counter CA is connected to the output of an AND gate P11, with 2 inputs, of which one energized at instant s3, and the other on operation of test key TS, which extends 1 when pressed. Counting input H is inhibited by key TS through an inverter I5 and gate P12 : address counter CA being inhibited, cycle counters CC1 and CC2 are driven from point AC through an OR gate P13 controlled by output Q16 of counter CA, and an OR gate P14 controlled by Q 16 across an inverter I3. Command signal AC is injected by a test circuit shown in figure 2 : Signal FC = O is transmitted at the end of the metering pulse to the test circuit through OR gate P15, of which the inputs are connected to points X1 and X2. The test circuit (fig. 2) comprises a number of gates which are used to block normal transmission of the output of oscillator OS1 to the sequential control circuit (C1, C2, DX1), and to open a second path for the signals, for the purpose of stepping the sequential control circuit and one of the cycle counters to the point at which step-by-step control is to start.

The normal path for the oscillator output signals is through gate P1, and OR gate P16 with 2 inputs, inverter I7, OR gate P17 with 3 inputs, and an AND gate P18 with 2 inputs, which drives the frequency divider C1.

The second path goes from the output of OS1 to AND gate P19, followed by two input OR gate P20, to gate P18.

Step-by-step control is obtained by operating push-button PP, in the circuit of test key TS, and enabling gate P17 each time pressed.

Automatic and subsequently step-by-step control is by two-input AND gate P21, of which the output is connected to gate P17 and to an inverter I8, controlling gate P20.

P21 is under the control of a set of gates P22 to P25, energized across one of 2 keys, of which one must be closed at the same time as test key TS - key AT1 "await end of cycle" with this key engaged, automatic operation continues until input FC wd 1, that is to say, until the end of the word CP writing cycle.

- key AT2 "await end of pulse" : with this key engaged, step-by-step control may start when CP = 0, namely when signal G = 1 (figure 5).

Finally, the stepping command for cycle counters CC1 and CC2 appears at output Q4 (bit value 4) of counter C2, and is transmitted by AND gate P26, enabled by one of the keys 81 or 82.

If it is desired to enhance the reliability of the system, the logic circuit may be duplicated by adding a second identical unit ALA (figure 8) connected to the standby memory MA. In such case, logic unit AL is connected solely to output interface IS, and logic unit ALA monitors signals returned through input interface IE, by means of a comparator CM3, consisting (for example) in a number of exclusive OR gates. A fault signal at the comparator output triggers an alarm ALM and energizes a device to display the number of the faulty metering pulse.

The form of the invention described may also be used to distribute timing signals, either by remote control enabling of the diode array word lines, or by using some other means for recording of part or all metering pulse characteristics, such as registers or a memory.

It is also possible to have several pulse durations, stored in registers such as RG2, and enabled by the address counter.

WHAT WE CLAIM IS: 1. A pulse supply system for simultaneously providing a plurality of different pulse streams each at individually settable pulse rates and pulse durations, the system comprising a clock, and a sequential control circuit driven by the clock and controlling both time counting means and address counting means, the time counting means serving to provide an output interface with "pulse on" and with "pulse off" signals for each of a plurality of different pulse streams and the address counting means serving to count simultaneously through addresses in both of two data stores, the first data store comprising an electrically alterable memory of the time counting means, and the second data store comprising marking means for setting data significant of a pulse repetition rate and of a pulse duration in each of a plurality of addresses, said data being in the form of a period word and a duration word with said period word being manually alterable, the pulse supply system further comprising a logic unit associated with the time counting means and arranged to operate at each address count under the control of a cycle counter to compare the value stored in the electrically alterable memory at that address count with an end value, and if the stored value is equal to the end value to provide the output interface with one of said "pulse on" and "pulse off' signals and to load the data from the corresponding address in the marking means into the memory, and if the stored value is different from the end value to change the stored value by a unit step in the direction of said end value.

2. A system according to claim 1, in which the means for predetermination of pulse periods uses an array designed to receive plug-in diodes, on which pulse periods are written by inserting diodes into appropriate intersections, said array being addressed by addressing circuit throughdemultiplexer which is enabled when the value of the addressed output pulse interval is to be written in the storage location allocated to it.

3. A system according to claim 1 or 2, in which the memory is divded into two blocks simultaneously addressed by the addressing circuit and the first block receiving the period words, the second block receiving the duration words, said two blocks being capable of separate enablement for writing and reading, by a set of memory control gates under the control of the address counter and the cycle counter.

4. A system according to claim 1, 2 or 3 in which a second cycle counter steps at each cycle of address counter and is connected to a decoding circuit to energize a group of outputs of said cycle counter, as determined by external signals received by said decoder, whereby said outputs permit writing and reading of the word determining the interval of the output pulse to be generated.

5. A system according to claim 2 or claim 3 or 4 as dependent on claim 2, supplying pulses divided into two groups, of which the first has periods determined solely by the configuration of the diodes plugged into the word lines of the diode array, and to which a first memory field and a first cycle counter are allocated, and of which the second has periods determined by external signals delivered to the system by a pulse generator such

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (10)

**WARNING** start of CLMS field may overlap end of DESC **. inputs, and an AND gate P18 with 2 inputs, which drives the frequency divider C1. The second path goes from the output of OS1 to AND gate P19, followed by two input OR gate P20, to gate P18. Step-by-step control is obtained by operating push-button PP, in the circuit of test key TS, and enabling gate P17 each time pressed. Automatic and subsequently step-by-step control is by two-input AND gate P21, of which the output is connected to gate P17 and to an inverter I8, controlling gate P20. P21 is under the control of a set of gates P22 to P25, energized across one of 2 keys, of which one must be closed at the same time as test key TS - key AT1 "await end of cycle" with this key engaged, automatic operation continues until input FC wd 1, that is to say, until the end of the word CP writing cycle. - key AT2 "await end of pulse" : with this key engaged, step-by-step control may start when CP = 0, namely when signal G = 1 (figure 5). Finally, the stepping command for cycle counters CC1 and CC2 appears at output Q4 (bit value 4) of counter C2, and is transmitted by AND gate P26, enabled by one of the keys 81 or 82. If it is desired to enhance the reliability of the system, the logic circuit may be duplicated by adding a second identical unit ALA (figure 8) connected to the standby memory MA. In such case, logic unit AL is connected solely to output interface IS, and logic unit ALA monitors signals returned through input interface IE, by means of a comparator CM3, consisting (for example) in a number of exclusive OR gates. A fault signal at the comparator output triggers an alarm ALM and energizes a device to display the number of the faulty metering pulse. The form of the invention described may also be used to distribute timing signals, either by remote control enabling of the diode array word lines, or by using some other means for recording of part or all metering pulse characteristics, such as registers or a memory. It is also possible to have several pulse durations, stored in registers such as RG2, and enabled by the address counter. WHAT WE CLAIM IS:

1. A pulse supply system for simultaneously providing a plurality of different pulse streams each at individually settable pulse rates and pulse durations, the system comprising a clock, and a sequential control circuit driven by the clock and controlling both time counting means and address counting means, the time counting means serving to provide an output interface with "pulse on" and with "pulse off" signals for each of a plurality of different pulse streams and the address counting means serving to count simultaneously through addresses in both of two data stores, the first data store comprising an electrically alterable memory of the time counting means, and the second data store comprising marking means for setting data significant of a pulse repetition rate and of a pulse duration in each of a plurality of addresses, said data being in the form of a period word and a duration word with said period word being manually alterable, the pulse supply system further comprising a logic unit associated with the time counting means and arranged to operate at each address count under the control of a cycle counter to compare the value stored in the electrically alterable memory at that address count with an end value, and if the stored value is equal to the end value to provide the output interface with one of said "pulse on" and "pulse off' signals and to load the data from the corresponding address in the marking means into the memory, and if the stored value is different from the end value to change the stored value by a unit step in the direction of said end value.

2. A system according to claim 1, in which the means for predetermination of pulse periods uses an array designed to receive plug-in diodes, on which pulse periods are written by inserting diodes into appropriate intersections, said array being addressed by addressing circuit throughdemultiplexer which is enabled when the value of the addressed output pulse interval is to be written in the storage location allocated to it.

3. A system according to claim 1 or 2, in which the memory is divded into two blocks simultaneously addressed by the addressing circuit and the first block receiving the period words, the second block receiving the duration words, said two blocks being capable of separate enablement for writing and reading, by a set of memory control gates under the control of the address counter and the cycle counter.

4. A system according to claim 1, 2 or 3 in which a second cycle counter steps at each cycle of address counter and is connected to a decoding circuit to energize a group of outputs of said cycle counter, as determined by external signals received by said decoder, whereby said outputs permit writing and reading of the word determining the interval of the output pulse to be generated.

5. A system according to claim 2 or claim 3 or 4 as dependent on claim 2, supplying pulses divided into two groups, of which the first has periods determined solely by the configuration of the diodes plugged into the word lines of the diode array, and to which a first memory field and a first cycle counter are allocated, and of which the second has periods determined by external signals delivered to the system by a pulse generator such

as an automatic rate-switching real time clock and to which a second memory field and a second cycle counter are allocated.

6. A system according to any previous claim, comprising outputs of output interface which are connected to the external units operated by, or using, the pulses supplied, said system also comprising an input interface, with its inputs connected to said external devices and receiving signals when these devices are or have been operated, and in which the logic unit comprises a monitoring circuit, supervising the status of said external devices by means of comparisons of outputs and inputs as corresponding, said comparison being inhibited at the start and end of each supplied pulse, thereby taking the busying and releasing response of each external device into account in system operation.

7. A system according to any previous claim in which a time-base comprises a first oscillator placed under the control of an alternating current generator receiving current from the commercial power supply, plus a standby oscillator not subjected to control by said generator, and taking over driving control of the sequential control circuit in the event of commercial power cuts or failure of the first oscillator.

8. A system according to any previous claim provided with means for the testing of the pulses supplied which comprise keys and a control signal suppeessor gating circuit whereby the address of the pulse to be tested having been loaded into counter of which the clock input is inhibited, said control signal suppressor will block the normal signal path between a first oscillator and the sequential control circuit, opening a second path on which the output of the first oscillator will step sequential control automatically up to the start of a cycle selected by keys such as the period word address cycle or write cycle, subsequently permitting the stepping of the sequential control one step at a time, by means of button.

9. A system according to claim 8, which comprises a second storage connected to receive and receiving the same data as memory and connected to a second logic circuit identical to logic unit, and carrying out the same operations as the latter, a comparator being provided to check for discrepancies between signals returned to the system through input interface and signals delivered by the second logic circuit.

10. A pulse supply system substantially as herein described with reference to the accompanying drawings.