GB1588177A

GB1588177A - Level selectors

Info

Publication number: GB1588177A
Application number: GB4271477A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1976-10-14
Filing date: 1977-10-13
Publication date: 1981-04-15
Also published as: DE2646501C3; DE2646501B2; FR2368182A1; IT1087063B; FR2368182B3; DE2646501A1

Description

(54) LEVEL SELECTORS (71) We, SIEMENS AKTIENGESELL SCHAFT, a German company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to level selectors Level selectors using externally controlled switching diodes in symmetrical arrangements are of use as test signal transmitters for testing logical electronic circuit arrangements by means of automatic logic testers or quite generally as output driver stages for pulse generators. Such selectors are generally required to output very steepflanked and high-frequency rectangular signals at variable high and low levels. It is generally desirable that such selectors can produce high amplitudes without amplification and provide short-circuit current limitation together with low internal resistance.

They are also desired to have optimum transient response.

German Patent Specification 2233 612 proposes a final stage for a test signal transmitter which uses externally controlled switching diodes in a symmetrical arrangement. As is apparent from the description and drawings of that specification, the proposed test signal transmitter is unsuitable for a four-quadrant operation, the season being that one stage can receive only current and the other stage can output only current. In the "Archiv für technisches Messen", Blatt Z 52-9 of October 1949, Page T 89, Figure 1, there is proposed a diode quartet (a fourdiode symmetrical arrangement) controlled as an electronics switch of an isolating transformer, Unfortunately, in this system the diodes can be controlled only at the cadence of a periodic a.c. voltage.

According to the present invention there is provided a level selector operable to deliver from a selector output an electrical pulse train of two independent voltage levels with controllable timing of switching between the voltage levels, the selector com- prising two switching diode quartets having respective input connection points connected to respective inputs of the selector to which the independent voltage levels are applied when the selector is in use, and respective output connection points connected for providing the respective. independent voltage levels to the selector output, and further comprising respective control stages, connected to control connection points of the respective quartets and operable to control switching timing, which control stages are operable at operating voltages the levels of which are independent of the voltage levels applied to the input connection points of the quartets and are independent as between one stage and the other.

An embodiment of the present invention can provide a rapid level selector which, in addition to having the desirable properties mentioned above can receive current and deliver current at both of the two independent voltage levels of the pulse train i.e., which is suitable for four-quadrant operation. In embodiments of the present invention two diode quartets are driven completely independently of one another as regards the operating potentials of their respective control stages. As Figure 2 of the accompanying drawings makes readily apparent, a level selector embodying this invention can have the required properties.

Control current and load current heterodyne with one another in every arm of a diode quartet. In the event of load current becoming excessive because of an external short circuit, one pair of diodes returns to the non-conductive state so that short-circuit current is limited to the level of the control current Compensation of the forward voltage of the diodes is improved in a level selector embodying the present invention since the same current flows through the two diodes of any one arm of a diode quartet, resulting jn reduced voltage error even though the diode inputs vary.

More particularly, control connection points of the diode quartets are connected to respective switchable die. sources which are completely independent as regards their operating potentials. The input connection points (see below with reference to Figure 1) of the quartets are connected to two independently adjustable voltage sources and the output connection points of the quartets are commoned to a common terminal. The control electrodes of the transistors which switch the d.c. current sources are connected to outputs of two flip-flops driven in pushpull through the agency of pulse transformers. Conveniently, each d.c. supply is fed from a transformer-fed rectifier bridge, to provide potential independence.

In a preferred embodiment of the invention, the primary windings of the pulse transformers are connected by way of resistances to outputs of respective single NOR gates, the NOR gates being connected each by way of one of their inputs to a pulse input in inverse parallel manner. An inhibit signal can be connected to one other input each of the two NOR gates. pnp transistors are used as transistors for the power supply and as the transistors of the flip-flops of the control stage for the higher pulse train voltage level whereas npn transistors are used for the transistors and the flip-flop transistors for the control stage for the lower pulse train voltage level.

Connecting together two similar diode gates (diode quartets) which have completely independent drives from the point of view of operating potential in a selector can provide not only load-current limiting but also compensating currents, as a result of the current limitation provided by the diode quartets, in the event of a superimposed drive between the two levels to be switched.

The selection of changeover rate can be rapid and relatively little power may be needed for control purposes. Also, the switch may be of low internal resistance. The nature of the control electronics used is such that, as well as pulse operation being possible, d.c. levels can be adjusted for any required length of time.

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a basic circuit diagram of a diode switch having a diode quartet as used in an embodiment of this invention, and Figure 2 is a circuit diagram of an embodiment of the present invention.

Referring to Figure 1, the connecting points of oppositdy connected diodes of a diode quartet D are connected to two output terminals of a control electronics system St.

The connecting points of two consecutive diodes of the quartet D that are connected the same way round as one another form input E and output A of the diode switch.

The control electronics system is connected by way of transformers U1 and U2 to a voltage supply U and to a control signal I.

The transformers isolate the control electronics system from the source of the voltage supply U and the source of control signal I.

The operating voltages of the control electronics system can thus be set independently of the potentials of the supply and control signals. The quartet D is driven by an impressed current which is output by the control electronics facility and switched by the control signal I.

Referring to Figure 2, two diode quartets or diode gates G1, G2 each consist of four diodes, D9-D12 and D13--D16 respectively, the diodes being interconnected after the fashion of the known Graetz bridge circuit. The connection parts of the quartets between diodes connected the same way round as one another serve as switching connections. Accordingly, the connection points between the diodes D10 and D12 of gate G1 and between the diodes D14 and D16 of gate G2 -are commoned to an output terminal TRA. The point of connection between the two diodes D9 and Dli of the gate G1 is connected via a choke Drl to a high logic-level input terminal HI. The point of connection between the two diodes Dl3 and D15 of gate 62 is connected by way of a choke Dr2 to an input terminal LO for a logically lower level. The control connections of the gate Gi-i.e., the points of connection between the oppositely directed diodes D9 and D10, D11 and Dl 2-are connected to a switchable power supply embodied by a transistor T1, a resistance R1 and a voltage supply Q1.

Similarly, in the case of the gate G2 the points of connection between the diodes D15 and 16, D13 and D14 are connected to a switchable power supply embodied by a transistor T2 and a resistance R2 and fed by a voltage supply Q2. The voltage supplies each take the form of a respective transformer Trl, Tr2 whose primary windings are connected to an a.c. voltage of, for example; 6 volts at a frequency of 3 MHz; and conventional rectifier bridge circuits which provide full-wave rectification . and which are connected to secondary windings of the transformers Trl, Tr2. The outputs of the rectifier bridge circuits are interconnected by way of smoothing capacitors C1 and C2 respectively. The voltages supplied by transformers Trl and Tr2 from their secondary windings are thus independent of one another and may differ from the a.c. voltages supplied to the primary windings of Trl and Tr2. The base electrode of transistor T1, which is a pnp transistor, is connected to one output of a flip-flop embodied by pnp transistors T3, T5. The emitters of the two. transistors T3, T5 are connected in parallel to one terminal of the voltage supply Q1. Their collectors are connected by way of collector resistances R3, R9 respectively to the other terminal of the voltage supply Q1. Similarly, the base electrode of transistor T2, which is an npn transistor, is connected to the output of a second flip-flop embodied by two other npn transistors T4, T6. The emitters of the flipflop transistors T4, T6 are connected in parallel to one output terminal of the voltage supply Q2 and their collectors are connected by way of collector resistances R4, R10 respectively to the other output terminal of the voltage supply Q2. Each transistor T3, T5 and T4, T6 of the respective flip-flops is fed back conventionally by way of resistance-capacitor combinations from the collectors to the base electrode of the other transistor of the flip-flop concerned (T5, T3 and T6, T4). The same are driven symmetrically by way of pulse transformers Tr3, Tr4; a secondary winding of the transformer Tr3 is connected by way of two capacitors C7, C9 to the base electrodes of the transistors T5, T3 respectively and a secondary winding of the transformer Tr4 is similarly connected by way of capacitors C8, C10 to the base electrodes of the transistors T6, T4 respectively. Primary windings of the pulse transformers Tr3, Tr4 are connected by way of resistances R11, R12 to outputs of two NOR gates NOR 1, NOR 2 and are also commoned to earth. Respective second inputs of the NOR gates NOR1, NOR2 are connected in parallel to a terminal INH adapted to be supplied with an inhibit signal.

A first input of NOR gate NOR1 is directly connected-and a first input of the NOR gate NOR2 is connected by way of an inverter IN-to a terminal INF adapted to be supplied with a control signal.

By way of the two inversely driven NOR gates NOR1, NOR2, the control signal goes from terminal INF to the primaries of the pulse transformers Tr3, Tr4 respectively, where the control signal is differentiated so that the flip-flops are driven symmetrically.

Consequently, both the positive flank and the negative flank of the input control signal change over the flip-flops. A rectangular signal whose amplitude is determined by voltage dividers embodied by resistances R3, R5 and R4, R6, respectively, is therefore produced at the collectors of the transistors T3, T4 respectively. The rectangular signal prescribes the pattern of the control current which acts via the transistors T1, T2 respectively to open the gates G1, G2 respectively.

The level inputs hi and lo are passed through to the output TRA by way of the respective diode quartets G1 and G2. An inhibit signal acting by way of the input INH on the NOR gates NOR1, NOR2 brings the flip-flops simultaneously into a state such that no current flows through either of the diode quartets G1, G2, with the result that the selector goes into a neutral condition in which the output TRA is highly ohmic. This feature facilitates connecting the selector up together with other circuits.

On the hypothesis, true for normal operation, that the output voltage at the output TRA is always between the higher and lower logic levels, the control circuits are always at potentials corresponding to the latter levels.

Consequently, the earth capacitances of the control circuits need not be changed over during a switching operation, so that a very high switching speed is obtainable.

It will thus be appreciated that in the embodiment of Figure 2, the diode quartets G1 and G2 are completely separate from the point of view of their potentials. The terminals HI, LO, and TRA are independent, from the point of view of their potentials, from terminals INF and INH. Moreover HI, LO and TRA are independent of power supply potential (e.g. 6v in Fig. 2).

WHAT WE CLAIM IS:- 1. A level selector operable to deliver from a selector output an electrical pulse train of two independent voltage levels with controllable timing of switching between the voltage levels, the selector comprising two switching diode quartets having respective input connection points connected to respective inputs of the selector to which the independent voltage levels are applied when the selector is in use, and respective output connection points connected for providing the respective independent voltage levels to the selector output, and further comprising respective control stages, connected to control connection points of the respective quartets and operable to control switching timing, which control stages are operable at operating voltages the levels of which are independent of the voltage levels applied to the input connection points of the quartets and are independent as between one stage and the other.

2. A selector as claimed in claim 1, wherein the respective control stages comprise respective switchable power supplies which comprise respective transistors and which are operable to deliver the said operating voltages.

3. A selectors as claimed in claim 2, wherein respective control electrodes of the said respective transistors of the respective switchable power supplies are connected to outputs of respective flip-flops controlled in push-pull by means of respective pulse transformers.

4. A selector as claimed in claim 2 or 3, wherein the said respective switchable power supplies comprise respective transformer-fed rectifier bridges.

5. A selector as claimed in claim 3 or claim 4 when read as appended to claim 3,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. by way of collector resistances R3, R9 respectively to the other terminal of the voltage supply Q1. Similarly, the base electrode of transistor T2, which is an npn transistor, is connected to the output of a second flip-flop embodied by two other npn transistors T4, T6. The emitters of the flipflop transistors T4, T6 are connected in parallel to one output terminal of the voltage supply Q2 and their collectors are connected by way of collector resistances R4, R10 respectively to the other output terminal of the voltage supply Q2. Each transistor T3, T5 and T4, T6 of the respective flip-flops is fed back conventionally by way of resistance-capacitor combinations from the collectors to the base electrode of the other transistor of the flip-flop concerned (T5, T3 and T6, T4). The same are driven symmetrically by way of pulse transformers Tr3, Tr4; a secondary winding of the transformer Tr3 is connected by way of two capacitors C7, C9 to the base electrodes of the transistors T5, T3 respectively and a secondary winding of the transformer Tr4 is similarly connected by way of capacitors C8, C10 to the base electrodes of the transistors T6, T4 respectively. Primary windings of the pulse transformers Tr3, Tr4 are connected by way of resistances R11, R12 to outputs of two NOR gates NOR 1, NOR 2 and are also commoned to earth. Respective second inputs of the NOR gates NOR1, NOR2 are connected in parallel to a terminal INH adapted to be supplied with an inhibit signal. A first input of NOR gate NOR1 is directly connected-and a first input of the NOR gate NOR2 is connected by way of an inverter IN-to a terminal INF adapted to be supplied with a control signal. By way of the two inversely driven NOR gates NOR1, NOR2, the control signal goes from terminal INF to the primaries of the pulse transformers Tr3, Tr4 respectively, where the control signal is differentiated so that the flip-flops are driven symmetrically. Consequently, both the positive flank and the negative flank of the input control signal change over the flip-flops. A rectangular signal whose amplitude is determined by voltage dividers embodied by resistances R3, R5 and R4, R6, respectively, is therefore produced at the collectors of the transistors T3, T4 respectively. The rectangular signal prescribes the pattern of the control current which acts via the transistors T1, T2 respectively to open the gates G1, G2 respectively. The level inputs hi and lo are passed through to the output TRA by way of the respective diode quartets G1 and G2. An inhibit signal acting by way of the input INH on the NOR gates NOR1, NOR2 brings the flip-flops simultaneously into a state such that no current flows through either of the diode quartets G1, G2, with the result that the selector goes into a neutral condition in which the output TRA is highly ohmic. This feature facilitates connecting the selector up together with other circuits. On the hypothesis, true for normal operation, that the output voltage at the output TRA is always between the higher and lower logic levels, the control circuits are always at potentials corresponding to the latter levels. Consequently, the earth capacitances of the control circuits need not be changed over during a switching operation, so that a very high switching speed is obtainable. It will thus be appreciated that in the embodiment of Figure 2, the diode quartets G1 and G2 are completely separate from the point of view of their potentials. The terminals HI, LO, and TRA are independent, from the point of view of their potentials, from terminals INF and INH. Moreover HI, LO and TRA are independent of power supply potential (e.g. 6v in Fig. 2). WHAT WE CLAIM IS:-

1. A level selector operable to deliver from a selector output an electrical pulse train of two independent voltage levels with controllable timing of switching between the voltage levels, the selector comprising two switching diode quartets having respective input connection points connected to respective inputs of the selector to which the independent voltage levels are applied when the selector is in use, and respective output connection points connected for providing the respective independent voltage levels to the selector output, and further comprising respective control stages, connected to control connection points of the respective quartets and operable to control switching timing, which control stages are operable at operating voltages the levels of which are independent of the voltage levels applied to the input connection points of the quartets and are independent as between one stage and the other.

wherein respective primary windings of the pulse transformers are connected by way of respective resistances to outputs of respective NOR-gates, and in that the NOR-gates are each connected by way of inputs thereof to receive a switching timing control signal input in inverse parallel relationship.

6. A selector as claimed in claim 5, wherein one further output of each of the said respective NOR-gates are connected to receive an inhibit signal.

7. A selector as claimed in claim 3, wherein those transistors of the said respective transistors and those transistors of the said respective flip-flops that are connected to one diode quartet are pnp transistors and those transistors of the said respective transistors and those transistors of the said respective flip-flops connected to the other diode quartet are npn transistors.

8. A level selector substantially as hereinbefore described with reference to the accompanying drawings.