GB1587339A - Digital control apparatus - Google Patents

Description

(54) DIGITAL CONTROL APPARATUS (71) We, VSESOJUZNY NAUCHNO-ISSLEDOVATELSKY INSTITUT VAGONOSTROENIA, of ulitsa Pushkinskaya 11, Moscow, USSR, a USSR corporate body, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This present invention relates to digital control apparatus and, particularly, to digital control apparatus for thyristor-pulse d.c. regulators.

According to the present invention there is provided digital control apparatus arranged to produce pairs of control pulses of which the relative timing varies in accordance with a controlling parameter, said apparatus comprising a transducer and arranged to apply a voltage representative of said parameter to a control unit which in response to said controlling parameter traversing a threshold level develops a digital signal that is applied to set a first counter to a condition representative of a predetermined value of said parameter, a pulse generator arranged to apply pulses at a repetition rate representative of said parameter to drive said first counter, at least one control channel comprising a decoder fed with the first counter output signal and arranged to develop a digital output predeterminedly related thereto, a digital-to-analog converter arranged to develop from said digital output a voltage representative thereof, a comparator arranged to compare said voltage with a voltage representative of said parameter and to develop, in response to clock signals applied to said comparator from a clock generator, pulse signals of which the polarity differs in accordance with the sign of the difference between the compared voltages, a distributor arranged to apply said pulses of one polarity to an add input of a reversible counter and said pulses of the opposite polarity to the subtract input of said reversible counter, a pulse counter arranged to be driven by a master oscillator and to develop periodic pulses of fixed timing, a matching decoder arranged to compare the output of said reversible counter with the output of said pulse counter and to develop in response to coincidence therebetween output pulses of which the timing with respect to the pulses of fixed timing varies in accordance with the state of count of said reversible counter.

The control device of this invention is advantageous in that it may be arranged automatically to control thyristor-pulse regulators with due regard for limitations imposed by the switching conditions and potential conditions at the commutator of a motor controlled by the device. In the case of a traction electric motor drive, the use of the invention helps to shorten the braking distance, to increase the speed of the rolling stock and to improve the reliability of electric motors.

A better understanding of the present invention will be had from a consideration of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a digital control apparatus for a thyristor pulse d.c. regulator, in accordance with the invention as applied to the control of a train traction motor; Figure 2 comprises graphs illustrating the adjustment of the field attenuation factor versus the braking resistance at different actual speed levels and with due regard for switching and potential limitations at the motor commutator, which is used to illustrate the operation of the present invention as applied to control of a train traction motor.

Figure 1 shows a digital control apparatus for a thyristor-pulse d.c. regulator used for control of a train traction motor and comprising a master oscillator 1, which is conveniently a relaxation oscillator, having its output connected to a clock pulse counter 2. The counter 2 is a binary counter whose multidigit logic ouputs 3 are connected to multidigit logic inputs of two matching decoders 4 and 5, whose function is conveniently performed by diode matrices. The number of digits of the multidigit logic input 3 is 2n, where n is the digit capacity of the counter 2. The multidigit inputs 6 and 7 of the matching decoders 4 and 5 are connected to the multidigit outputs of respective reversible binary counters 8 and 9.The number of digits of the multidigit inputs 6 and 7 is 2n, whereas the number of flip-flops in each of the reversible counters 8 and 9 and in the clock pulse counter 2 is n.

An add input 10 and a subtract input 11 of the reversible counter 8 are connected to respective outputs of a distributor 12. An add input 13 and a subtract input 14 of the reversible counter 9 are connected to respective outputs of a second distributor 15. The inputs of the distributors 12 and 15 are connected respectively to the outputs of comparators 16 and 17, advantageously constructed as ring modulators. The distributors 12 and 15 are conveniently formed by diode separators arranged to distribute control signals to the add inputs 10 and 13 and subtract inputs 11 and 14, respectively, depending upon the polarity of the signals applied to their inputs from the comparators 16 and 17. Clock inputs 18 and 19 of the comparators 16 and 17 respectively, are connected to an output of a clock pulse generator 20 which is conveniently a relaxation oscillator.A reference signal input 21 of the comparator 16 and a reference signal input 22 of the comparator 17 are connected in common to the output of a voltage transducer 23. The output signal level of the voltage transducer 23 is proportional to the speed of the train.

A control input 24 of the comparator 16 and a control input 25 of the comparator 17 are respectively connected to the outputs of digital-analog converters 26 and 27. The comparator 16 is arranged to compare the voltage levels of signals applied to it from the voltage transducer 23 and from digital-analog converter 26. When the absolute levels of these signals do not coincide, the comparator 16 passes pulses from the clock pulse generator 20 to the input of the distributor 12. The comparator 17 serves a corresponding purpose. The inputs of the digital-analog converters 26 and 27 are connected to the outputs of coders 28 and 29, respectively. The inputs of the coders 28 and 29 are connected to the outputs of control decoders 30 and 31, respectively. Decoders 30 and 31 are conveniently formed by diode matrices.The coders 26 and 27 and control decoders 30 and 31 have multidigit inputs with m digits, where m=4, 5, ..., 12. The number of digits is chosen to suit specific operating conditions.

The diode matrix of the control decoder 30 is designed to appropriately adjust the braking resistance, whereas the diode matrix of the control decoder 31 is designed to appropriately adjust the magnetization field attenuation factor. The multidigit inputs of the control decoders 30 and 31 are connected to the multidigit outputs of a binary counter 32.

The multidigit input 33 of the binary counter 32 is connected to a multidigit control output of a control unit 34. The input of control unit 34 is connected to an output of a velocity transducer 35 and is arranged, apart from other functions, to apply to the multidigit input 33 of the binary counter 32 a binary code signal corresponding to the initial braking speed. A single-digit input 36 of the binary counter 32 is connected to an output of a pulser 37 arranged to form a train of pulses of which the number is proportional to the speed of the train. An inhibiting output 38 of the control unit 34 is connected to inhibit and reset inputs of the master oscillator 1, clock pulse generator 20, counter 2, reversible counters 8 and 9, and to similar inputs of the pulser 37 and of the voltage transducer 23.

The binary pulse counter 32 is arranged to apply a binary code, corresponding to the actual train speed, to the control decoders 30 and 31; as a result, a signal in the form of a position code is produced at one of the outputs of each of the control decoders 30 and 31, the selection of output being determined by the input binary code. The coders 28 and 29 and digital-analog converters 26 and 27 are arranged to convert the position codes received from decoders 30 and 31 into multidigit codes and then into signal voltages corresponding to a desired pattern of adiustment of the field attenuation factor and of the braking resistance. Control outputs 39 and 40 of the clock pulse counter 2 are connected to the respective main thyristors of two thyristor-pulse regulators. An output 41 of the matching decoder 4 and an output 42 of the matching decoder 5 are connected to the respective switching thyristors (not shown) of the thyristor-pulse regulators.

Figure 2 is a graph illustrating the adjustment of the field attenuation factor p versus the brake resistance value RT. Curves 43, 44, 45, 46, 47, 48 and 49 are plotted with due regard for limitations on Umax imposed by potential conditions at the commutator at speeds of 100, 90, 80, 70, 65, 60 and 57.2 km per hour, respectively.

where: emaX=maximum inter-bar voltage; Umax=current value of the inter-bar voltage; K=number of commutator pitches; a=pole overlapping; p=field attenuation factor; number of turns of the field winding; p=number of pairs of the motor poles; and IP p IA where: IB=current through the exciting winding; IR=armature current.

Curve 50 is plotted with due regard for limitations resulting from switching conditions: 8iNw2AlV P,(V-q/p+y+E) where: e=reactive e.m.f. of the motor; i=current through the parallel branch; N=number of commutator bars; w=number of turns within a section; ph=commutator pitch; y=number of bars overlapped by a brush; E=shortening of the winding in commutator pitches; V=speed of rotation; l=length of steel lamination A=conductivity of the stray flux path with regard to the frontal parts (per unit length of the steel lamination); p=number of pairs of the motor poles; q=number of pairs of parallel branches of the armature winding.

The points of intersection between curves 43 to 49 and curve 50 indicate optimum values of p and RT for each speed.

The thyristor-pulse d.c. regulator digital control device described above operates as follows. Let it first be assumed that the train is running at a constant speed without braking. In such a case, a blocking signal is continuously applied from output 38 (Figure 1) of the control unit 34, which inhibits the operation of the voltage transducer 23, pulser 37, reversible counters 8 and 9, counter 2, master oscillator 1 and clock pulse generator 20. As a result, signals are not produced at the outputs of the comparators 16 and 17, and braking does not take place. At the same time the velocity transducer 35 continuously sends a signal to the control unit 34; the level of this signal being proportional to the speed of the train.When braking is to occur, a signal in the form of a binary code, corresponding to the initial braking speed, is applied from the multidigit control output of the control unit 34 to the multidigit input 33 of the binary counter 32.

The signal applied to the binary counter 32 resets the counter flip-flops to a state which corresponds to the point of intersection between curves 43 and 50, this being appropriate for an initial braking speed of 100 km per hour. When this takes place, the inhibiting signal is no longer applied from the output 38 of the control unit 34 to the inputs of the master oscillator 1, counter 2, reversible counters 8 and 9, voltage transducer 23 and pulser 37. As a result, the flip-flops of the reversible counters 8 and 9 are reset to predetermined initial states which do not coincide; the counter 2 is reset to zero and the pulser 37 starts sending to the binary counter 32 pulses at a frequency proportional to the speed of the train. Each new pulse changes the state of the stages of the binary counter 32.

From the output of the binary counter 32, signals in the form of binary code combinations are applied to the control decoders 30 and 31, one in each of the two control channels, one of which adjusts the field attenuation factor p, while the other adjusts the braking resistance RT. According to the logic of the matrices of the control decoders 30 and 31, which correspond respectively to the desired patterns of adjustment of Rt (the control decoder 30) and of p (the control decoder 31), there is produced at the output of each of the control decoders 30 and 31 a signal in the form of a position code, which is applied to the coders 28 and 29, respectively, to be converted by these into binary code signals.The binary code signals are applied to the digital-analog converters 26 and 27 which convert them to signal voltages proportional to the digital values of the binary code input signals.

From the outputs of the digital-analog converters 26 and 27, the signal voltages are applied to the control inputs 24 and 25, respectively, of the comparators 16 and 17.

Simultaneously, clock pulses are applied from the generator 20 to the clock inputs 18 and 19 of the comparators 16 and 17. The clock pulses are produced at a preset add or subtract frequency which is appropriate to the dynamic and static characteristics of the whole control system. In addition, a signal voltage proportional to the speed of the train is applied from the speed transducer 23 to the respective reference signal inputs 21 and 22 of the comparators 16 and 17. If this voltage is greater than the voltage applied to the control inputs 24 and 25, there are produced at the outputs of the comparators 16 and 17 pulses of positive polarity whose repetition frequency is equal to that of clock pulses of the generator 20.If the reference voltage applied to the inputs 21 and 22 is lower than the voltage applied to the comparators 16 and 17 from the digital-analog converters 26 and 27, pulses of negative polarity are produced at the outputs of the comparators 16 and 17. In each case, the two compared voltages are equal, no pulses are produced at the outputs of the comparators 16 and 17; hence, no braking takes place.

Output pulses from the comparators 16 and 17 are applied to the distributors 12 and 15, respectively. Depending upon the polarity of the pulses arriving from the outputs of the comparators 16 and 17, the distributors 12 and 15 apply positive output pulses to the add inputs 10 and 13 of the reversible counters 8 and 9, or negative output pulses to the subtract inputs 11 and 14 of these counters. In the former case, the reversible counters perform addition; in the latter case, they subtract. The master oscillator 1 applies clock pulses to drive the counter 2 at a frequency F.From the control output 39 of the counter 2, pulses which occur at constant frequency: F f= 2(n} where: F=repetition frequency of clock pulses from the output of the master oscillator; n=digit number of the clock pulse counter are applied to the main thyristors of the thyristor-pulse field regulator (not shown); from the control output 40, pulses which also occur at constant time intervals are applied to the main thyristors of the thyristor-pulse braking resistance regulator (not shown). The control outputs 39 and 40 are the outputs of the highest-order stage of the counter 2. At the same time signals in the form of a binary code are applied from the multidigit logic output 3 of the counter 2 to the multidigit logic inputs of the matching decoders 4 and 5, to whose multidigit information inputs 6 and 7 signals in the form of a binary code are applied from the reversible counters 8 and 9, respectively. As pointed out above, the initial states of the reversible counters 8 and 9 are different and determine the initial duration of pulses developed by the thyristor-pulse field regulator and by the thyristor-pulse braking resistance regulator.When coincidence occurs between the binary code combinations applied from counter 2 to the multidigit logic inputs of the matching decoders 4 and 5 and those applied to their information inputs 6 and 7, pulses that are shifted in time with respect to the pulses developed at outputs 39, 40 are produced at the outputs 41 and 42, respectively, of the decoders 4 and 5.

These latter pulses are applied to the switching thyristors of the thyristor-pulse field regulator and of the thyristor-pulse braking resistance regulator (not shown). The time interval at between the pairs of pulses developed at outputs 39, 42 and 40, 41 and hence the duration of the output pulse of each thyristor-pulse regulator is dependent upon the number and repetition frequency of the control signals applied to the add inputs 10 and 13 and to the subtract inputs 11 and 14 of the reversible counters 8 and 9.

T where: time shift between the moments of the occurring of two subsequent pulses from the output of the time-shiftable pulses decoder; T=switching period for the main and switching thyristors; i, j=the number of control signals applied to the add and subtract inputs of the reversible counter, respectively.

When control signals are applied to the add inputs 10 and 13, the difference in the timing of the time-fixed and time-shifted pulses increases: when control signals are applied to the subtract inputs 11 and 14, this difference decreases. In the former case, the duration of output pulses of the thyristor-pulse regulators increases by b; in the latter case, the difference decreases by 8.

When the braking speed is reduced to 57.2 km per hour (see Figure 2) and the limitation imposed by the switching conditions is no longer in force (this value differs with different types of motor), the thyristor-pulse field regulator stops operating, and further braking is only effected by changing the value RT of the braking resistance.If this is the case, no more pulses are sent from the control ouput 42 (Figure 1), because the matrix of the control decoder 31 is designed for a speed range of 100 to 57.2 km per hour, whereas the matrix of the control decoder 30 is designed for a speed range of 100 to 5 km per hour, which range is advantageous for effective adjustment of the braking resistance value RT. Timefixed and time-shifted pulses are provided from the control output 40 and from output 41 respectively until the speed is reduced to5 km per hour, when electric braking is discontinued.

To summarise, the proposed digital control device for controlling thyristorpulse regulators automatically controls thyristor-pulse regulators with due regard for limitations imposed by switching and potential conditions at the motor commutator, and adjusts RT and p simultaneously. The invention provides for the fullest utilization of the installed capacity of the motors and improves their reliability. When applied to traction motors, it helps to reduce the braking distance and thus to speed up traffic.

WHAT WE CLAIM IS: 1. Digital control apparatus arranged to produce pairs of control pulses of which the relative timing varies in accordance with a controlling parameter, said apparatus comprising a transducer and arranged to apply a voltage representative of said parameter to a control unit which in response to said controlling parameter traversing a threshold level develops a digital signal that is applied to set a first counter to a condition representative of a predetermined value of said parameter, a pulse generator arranged to apply pulses at a repetition rate representative of said parameter to drive said first counter, at least one control channel comprising a decoder fed with the first counter output signals and arranged to develop a digital output predeterminedly related thereto, a digital-to-analog converter arranged to develop from said digital output a voltage representative thereof, a comparator arranged to compare said voltage with a voltage representative of said parameter and to develop, in response to clock signals applied to said comparator from a clock generator, pulse signals of which the polarity differs in accordance with the sign of the difference between the compared voltages, a distributor arranged to apply said pulses of one polarity to an add input of a reversible counter and said pulses of the opposite polarity to the subtract input of said reversible counter, a pulse counter arranged to be driven by a master oscillator and to develop periodic

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. the matching decoders 4 and 5 and those applied to their information inputs 6 and 7, pulses that are shifted in time with respect to the pulses developed at outputs 39, 40 are produced at the outputs 41 and 42, respectively, of the decoders 4 and 5. These latter pulses are applied to the switching thyristors of the thyristor-pulse field regulator and of the thyristor-pulse braking resistance regulator (not shown). The time interval at between the pairs of pulses developed at outputs 39, 42 and 40, 41 and hence the duration of the output pulse of each thyristor-pulse regulator is dependent upon the number and repetition frequency of the control signals applied to the add inputs 10 and 13 and to the subtract inputs 11 and 14 of the reversible counters 8 and 9. T where: time shift between the moments of the occurring of two subsequent pulses from the output of the time-shiftable pulses decoder; T=switching period for the main and switching thyristors; i, j=the number of control signals applied to the add and subtract inputs of the reversible counter, respectively. When control signals are applied to the add inputs 10 and 13, the difference in the timing of the time-fixed and time-shifted pulses increases: when control signals are applied to the subtract inputs 11 and 14, this difference decreases. In the former case, the duration of output pulses of the thyristor-pulse regulators increases by b; in the latter case, the difference decreases by 8. When the braking speed is reduced to 57.2 km per hour (see Figure 2) and the limitation imposed by the switching conditions is no longer in force (this value differs with different types of motor), the thyristor-pulse field regulator stops operating, and further braking is only effected by changing the value RT of the braking resistance.If this is the case, no more pulses are sent from the control ouput 42 (Figure 1), because the matrix of the control decoder 31 is designed for a speed range of 100 to 57.2 km per hour, whereas the matrix of the control decoder 30 is designed for a speed range of 100 to 5 km per hour, which range is advantageous for effective adjustment of the braking resistance value RT. Timefixed and time-shifted pulses are provided from the control output 40 and from output 41 respectively until the speed is reduced to5 km per hour, when electric braking is discontinued. To summarise, the proposed digital control device for controlling thyristorpulse regulators automatically controls thyristor-pulse regulators with due regard for limitations imposed by switching and potential conditions at the motor commutator, and adjusts RT and p simultaneously. The invention provides for the fullest utilization of the installed capacity of the motors and improves their reliability. When applied to traction motors, it helps to reduce the braking distance and thus to speed up traffic. WHAT WE CLAIM IS:

1. Digital control apparatus arranged to produce pairs of control pulses of which the relative timing varies in accordance with a controlling parameter, said apparatus comprising a transducer and arranged to apply a voltage representative of said parameter to a control unit which in response to said controlling parameter traversing a threshold level develops a digital signal that is applied to set a first counter to a condition representative of a predetermined value of said parameter, a pulse generator arranged to apply pulses at a repetition rate representative of said parameter to drive said first counter, at least one control channel comprising a decoder fed with the first counter output signals and arranged to develop a digital output predeterminedly related thereto, a digital-to-analog converter arranged to develop from said digital output a voltage representative thereof, a comparator arranged to compare said voltage with a voltage representative of said parameter and to develop, in response to clock signals applied to said comparator from a clock generator, pulse signals of which the polarity differs in accordance with the sign of the difference between the compared voltages, a distributor arranged to apply said pulses of one polarity to an add input of a reversible counter and said pulses of the opposite polarity to the subtract input of said reversible counter, a pulse counter arranged to be driven by a master oscillator and to develop periodic

pulses of fixed timing, a matching decoder arranged to compare the output of said reversible counter with the output of said pulse counter and to develop in response to coincidence therebetween output pulses of which the timing with respect to the pulses of fixed timing varies in accordance with the state of count of said reversible counter.

2. A digital control apparatus in accordance with claim 1 and including a further said control channel arranged to develop further output pulses of which the timing with respect to further pulses of fixed timing varies with change of said parameter in a manner different from the mutual timing of the output pulses and the pulses of fixed timing of said one control channel.

3. Digital control apparatus in accordance with claim 2 wherein the pulse pairs of said one control channel are arranged to control the operation of a thyristor pulse regulator which alters the field strength of an electric traction motor of a vehicle and the pulse pairs of said further control channel are arranged to control the operation of a thyristor pulse regulator which alters an electric braking resistance of said vehicle, said parameter being the vehicle speed.

4. Digital control apparatus in accordance with claim I and substantially as herein described with reference to Figure 1 of the accompanying drawings.