SU1203481A1 - Digital regulator of angular velocity of arc-stator induction motor - Google Patents

Description

the outputs of the cathode pulse amplifier, the outputs of the inverter are connected respectively to the outputs of the first and fourth quad keys, the third and

the sixth keys, the fifth and second keys, as well as respectively with the first, second and third inputs of the inductor motor, and (i- 1) bit outputs of the memory register

Connected to the information inputs of the fifth and sixth counters, the output of the fifth counter is connected directly to the first inputs of the fourth and fifth elements AND, and through series-connected first elements NOT and NAND to their preliminary recording input, the output of the sixth counter is directly connected with the first inputs of the sixth and seventh elements AND, and through successively connected second elements NOT and NAND - with their preliminary recording input, the counting inputs of the fifth and sixth counters are connected with the second inputs the first and second elements of the NAND and the output of the pulse generator, the second inputs of the fourth and seventh elements AND are connected to the direct output of the highest bit of the memory register, the inverse output of the high level of the memory register is connected to the second inputs of the fifth and sixth elements And, The first and second inputs of the second element OR are connected respectively with the outputs of the fourth to the sixth elements AND, and the output with the account. The invention relates to automatic control and can be applied in radio engineering systems, instrument engineering and machine tool troenii i

The purpose of the invention is to increase the accuracy of the controller in operation and to expand the range of angular velocity control.

FIG. 1 shows the structural scheme of the proposed digital regulator of the angular velocity of an arc-controlled asynchronous motor; in fig. 2 - flow chart six03481

the third input, the output of which is connected directly to the counting input of the controlled frequency divider and through serially connected third elements NOT and NAND to its preliminary recording input, the second input of the third element NAND is connected to the output of the second element OR, the first and second inputs of the third element OR are connected respectively to the outputs of the fifth and seventh elements AND, and the output to the counting input of the fourth Counter, the information inputs of the controlled frequency divider are connected to the second bits and the outputs of the speed setting block, and the output of the controlled divider is often connected directly to its preliminary recording input and through the seventh counter to the first inputs of the first and second decoders, the second inputs of which are connected respectively to the forward and inverse outputs of the high order register memory, and the outputs, respectively, of the first and second inputs of the driver of control pulses, the first and second outputs of which are connected respectively to the input of the cathodic pulse amplifier and through the modulator to the input nodnogo pulse amplifier, a second input of the modulator connected to the output of the second RS-trigger strobiruyush; s. the input of the limiting unit is connected to the direct output of the first RS trigger.

channel driver control pulses; in fig. 3 is a block diagram of the regulator modulator. The proposed controller contains

inductors 1, rotary element 2, induction motor 3, speed sensor 4, first 5, second 6, third 7 and fourth 8 pulse shapers, first 9, second 10 and

third 11 RS-triggers, first 12, second 13, third 14, fourth 15, fifth 16, sixth 17, seventh 18, eighth 19, ninth 20, tenth 21, eleventh 22, twelve 23,

the thirteenth 24 and fourteenth 25 elements And, the first 26, the second 27, the third 28, the fourth 29, the fifth 30, the sixth 31 and the seventh 32 counters, the memory register 33, the block 34 is limited, the first 35, the second 36, the third 37 and the fourth 38 elements OR, speed setting unit 39, pulse generator 40, controlled frequency divider 41, first 42, second 43 and third 44 AND-NOT elements, first 45, second 46 and third 47 NOT elements, first 48 and second 49 decoders, 50 control pulse generator, modulator 51, anode 52 and cathode 53 pulse amplifiers, DC source 54, three-phase power tovoy inverter 55, anode 56 and cathode 57 klchey inverter group, straight 58 and inverted outputs of the most significant bit 60, register 33, the memory, the first 61, second 62 and third 63 conditioners control pulses, a delay element 64

As a decoder 48 and 49, you can use any shift register or a decoder that distributes control pulses into six independent channels and has a gate input. When used as the seventh counter 32 divider counter 12 K155IE4 (a divider by six is used) it is convenient to use as a decoder 48 and 49 a dual K155VD4 decoder-multiplexer (K155IDZ).

As a three-phase bridge inverter 55 with anode 56 and cathode 57 groups, a transistor inverter with a DC link is used, each of the six keys of which consists of an opposite-connected power transistor and a reverse current diode providing power to the three-phase arcuate asynchronous motor power voltage with adjustable frequency. I

As a direct current source 54, any uncontrolled rectifier bridged by a capacitor can be used to supply the applied inverter 55,

As a six-channel driver 50 control pulses, you can use any driver control pulses, you-. Completing the functions of forming six 180-degree pulses to control the inverter keys in accordance with their switching algorithms (forward and reverse phase rotation) and providing the necessary delay between turning off and on two inverter keys related to one phase

(the prohibition of their simultaneous switching on due to the possibility of short-circuiting the DC source).

One of the possible embodiments of the six-channel shaper 50 of the sending pulses (Fig 2) contains the first 61, the second 62 and the third 63 shapers of the control pulses, performed according to the same scheme.

As a delay element 64, a short pulse of the one-shot type can be used.

The delay element 64 is controlled by the leading edge of a positive pulse from the output of the OR 38 element when zero impulses from AND 19 and 20 are applied to its inputs. The output (zero) pulse of the delay element 64 blocks the signal from the direct or inverse RS outputs for the delay time the trigger 11 to the output, respectively, of the tenth of the 21 or eleventh 22 elements And, creating the necessary time delay between the inclusion of one key and the inclusion of another. As a modulator 51, any modulator that modulates the control pulses from the driver 50 to the anode pulse amplifier can be used with working pulses tp (from the output of the second flip-flop 10). One

Among the possible embodiments of the modulator 51 (Fig. 3), there are three AND 23-25 elements (according to the number of control signals), in which MS K155 OR1 are applied.

As the anodic 52 and cathodic 53 pulse amplifiers, you can use any three-channel amplifiers that amplify the control signals from the output of the former 50 or

the modulator 51 to the velgchin region, necessary for controlling the transistor switches of the inverter, and the galvanically separating control and power circuits

inverter circuits. For low-frequency converters, it is convenient to use pulse amplifiers that use modulation of the control signal with a high-frequency square-wave signal.

The speed setting unit 39 is any contact switches or contactless switches that allow the information inputs of the first counter 26 and the controlled frequency divider 41 to be supplied as a number code associated with setting the required speed.

When a controlled frequency divider 41 is used as the first counter 26 with the same counting direction, the direction of change of the conversion factor and the division factor with a given speed are the same.

In this case, in the entire range of speeds, each value of the given speed corresponds to a certain value of the conversion factor m, and the coefficient Nypij varies in steps along the subbands of the speed variation, i.e. a certain subrange constant for a given subband corresponds to a certain subband. Therefore, for speed setting unit 39, it is convenient to use two analog-to-digital converters controlled by one adjustable value (for example, one input voltage): to form a conversion factor change code (the first the outputs of the speed setting unit 39) —Analog-to-digital converter based on a reversible counter and a digital-to-analogue converter, and to form a change code the coefficient and dividing N ((04 (second bit outputs of the speed setting unit 39)) is an analog-to-digital parallel-converter with the use of comparison circuits.

To facilitate the explanation of the digital controller operation, we assume that the second 27, fifth 30 and seventh 32 counters are connected to the direct account, and the first 26, third 28, fourth 29 and sixth 31 counters and

controlled frequency divider 41 counters are counted down.

The regulator measures the duration of the interval TC 1 / proportional to the angular velocity coming from the speed sensor 4. The measurement is carried out by filling the interval with pulses of the reference frequency from the pulse generator 40 and counting them with the first 26 and second 27 counters. °

Before the start of the regulator

5, in the speed setting unit 39 (first bit outputs), a number is set as a code equal to the number of generator pulses 40 arriving at the first counter 26 in time

0 from the beginning of the measured interval to the upper limit of the selected zone of control of the angular velocity.

Depending on the selected angular velocity, a code is established at the second bit outputs of the speed setting unit 39, which determines the division factor Jt) c of the controlled frequency divider 41.

Codes set at first

and the second bit outputs of the speed unit 39 depend on the selected control zone, the set values of the motor angular velocity and the parameters of the input intervals received from the speed sensor 4.

The digital controller works as follows.

The pulse coming from the speed sensor 4, which sets the beginning of the measured interval and formed in the first pulse shaper 5, transfers the task recorded in the speed reference block 39 (the first bit outputs) to counter 26. Through the delay time required to set the counter 26 , a zero pulse from the second driver 6 switches the first RS-trigger 9. At the same time, the enabling (single) potential is supplied to the first input of the first element 12 and the generator 40 starts to flow to the subtraction input of the first counter 26. The delay time, determined by the third driver 7, sets the initial code from the fourth driver 8 to the zero driver.

Depending on the ratio between the actual angular velocity of the engine Jg and the onset speeds of the end of the control zone uJxip, the measurement of the error and the generation of the control signal of the regulator are performed as follows:

1) About

one)

output of the second rator

about uJ

When the input of the first counter 26 of a given number of pulses, it is set to the zero state and the first RS-trigger 9 switches to zero state with the zero output pulse. At the same time, the first element And 12, closes the zero pulse from the direct output of the RS-flip-flop 9 stopping the flow of the generator pulses 40 to the first counter 265 and gating the operation of the restriction unit 34 is permitted. A single signal from the inverted RS flip-flop 9 opens element I 13 and the gene 40 pulses begin to flow through the second 13 and third 14 elements And to the input Direct account of the second counter 27 (before installing the limit code 27 on the output outputs of the second counter 27 limiting, the resolving single signal is supplied to the second input of the third element I 14).

When installed on the bit output of the second counter 27, the restriction code is triggered (in this case, a zero signal is sent to its gate input from the direct output of the flip-flop trigger 9), and the third element closes the second input with a zero pulse And 14, stopping the flow of generator 40 pulses the counter input of the counter 27. At the same time, the output pulse of the restriction unit 34 through the information OR 35 information element from the bit outputs of the second counter 27 (the restriction code) is transferred to the memory register 33. The error measurement cycle is over.

The next pulse from the speed sensor 4, formed in the first driver 5, transfers the task recorded in the speed task unit 39 to counter 26. The pulse from the second driver 6 switches 203481

first Y5 trigger 9 is transmitted. With a zero pulse from the Inverse output of the first RS flip-flop 9, the second element I 13 is blocked, and with a single

5, the limiting unit 34 is blocked by a pulse from its direct output, and through the first element 12, the receipt of the generator 40 pulses is allowed to the counting input of the first counter

10 26. Through the delay time determined by the third controller 7, im-. The pulse from the fourth driver 8 is set to the start 5 code by the installation input in the second counter 27, preparing it to receive the information of the next error measurement cycle.

“IuJ iZPZR.

2)

I.O

Hip

0

five

0

five

0

five

The regulator error measurement elements work in the same way as for О uJ ,, -uJH3p 5 with the exception that the next impulse from the speed sensor 4 comes during the operation of the second counter 27 (before the limit code is set on its outputs). A pulse from the output of the first shaper 5, the task from the speed setting unit 39 is transferred to the first counter 26, a pulse from the output of the second shaper 6 of the pulses switches the first RFl-trigger 9. At the same time, the second element I 13 is blocked by a signal from its inverse output the output allows the passage of pulses from the generator 40 through the first element AND 12 to the subtractive input of the first counter 26, the pulse from the output of the third driver 7 through the OR element 35 information from the bit outputs of the second counter 27 is transferred to the re ISTR memory 33, and the pulse output from the fourth driver 8 in the second counter 27 is set to an initial code, preparing it for the next measurement error reception cycle information.

3)

iZ - (

In this case, the next pulse from the speed sensor 4 arrives during the operation of the first counter 26 (before setting it to the zero state). The impulse from the output of the first organizer 5, the task from the speed setting unit 39 is transferred to the first counter 26, the impulse from the output of the second generator 6 is held

8 unit state first R5 - trigger 9 (direct output 1). In this case, the second element 13 and 13 (generator 40 pulses do not pass into counter 27) continue to block the zero potential from the inverse output of the first RS trigger, and the first input of the first element 12 of the direct output of the first RS trigger 9 is applied to the first input a) the potential and the input of the subtraction of the first counter 27 receive impulses of the generator 40 (new cycle. error measurement). The pulse from the output of the third driver 7 through the ShZh 35 element of information from the bit outputs of the second counter 27 is transferred to memory register 33 (the start code), and the pulse from the output of the fourth driver 8 in the second counter 27 confirms the setting of the initial code, preparing it to receive information the next error measurement cycle.

Thus, with uJa 4, the restriction code of the second counter 27 is overwritten in the memory register 33.

at

oJa ijJ

 - start code

the second counter 27, and with uJ - "- the information klr information from the second counter 27 is located; and c therein at the moment of arrival of the next pulse from the speed sensor 4 (intermediate code between the initial code and the restriction code) The values of the initial code and the restriction code are set according to the required frequency control frequency in the traction and braking modes; the information in memory register 33 is updated with a frequency equal to the frequency of the pulses coming from speed sensor 4. The information found in memory register 33 is converted into rotating The engine torque 3 is as follows.

The state of the senior (nth) bit 60 of memory register 33 determines the mode of operation of the asynchronous machine (direction of torque):

state 1 (direct output 58 - 1, inverse output 59 - O) - engine mode (the direction of the torque coincides with the direction of rotation of the engine shaft (thrust mode) 5

O state (direct output 58 - O, inverse output 59 - 1),

20348 10

electromagnetic brake mode (the moment is directed against the direction of rotation of the motor shaft - braking mode.

5 The state (h - 1) of the lower bits of the memory register 33 determines the magnitude of the moment in the pull or braking modes.

Suppose that the old 10 state of the 60 bit of the register is 33 memory 1 (output 58 - 1, output 59 - O). In this case, the fourth element AND 15 through the second element OR 36 connects to the counting input of the third

15 of the counter 28, the output of the fifth counter 30, the seventh element AND 18 through the third element OR 37 connects to the counting input of the fourth counter 29 the output of the sixth counter 31.

20.1.

To the second (strobe) input

The second decoder 49 receives a zero signal, allowing it to work, and the second signal (strobe 1st)

The 25 input of the first decoder 48 receives a single signal blocking it. The summing input of the fifth counter 30 and the subtracting input of the sixth counter 31 are constantly fading with the impulses of the generator 40.

When the fifth counter 30 is filled, the zero signal from its output through the first element HE 45 is applied to the first one. the input of the first element AND-HE42.

5 Another pulse generator 40

through the first element IS-NE 42 is fed to the input of the preliminary recording of the fifth counter 30, recording a number in it (setting the conversion factor N504 according to the information in the register 33 of the memory. The output of the fifth counter 30 is set to a single signal, which first element is NOT 45

 blocks the passage of pulses

generator 40 to the input of the preliminary recording of the fifth counter 30, permitting its operation at the counting input. Upon admission to the counting entrance

50 fifth counter 30 is the number of pulses of the generator 40, in accordance with the established conversion factor. M (its output is again set to zero and produced

55 Set the recalculation coefficient Nsc4 according to the information currently in memory register 33.

II

Thus, depending on the information recorded in the memory register 33, the conversion factor Njcq changes and at the output of the fifth counter 30 a pulse l is formed with the following period (t rv NSCH) which through the fourth element AND 15 and the second element OR 36 served on the subtracting input of the third counter 28.

When the sixth counter 31 is set to the zero state, the zero signal from its output through the second element NOT 46 is supplied to the first input of the second element NAND 43. The next pulse of the generator 40 through the second element NAND 43 is fed to the input of the preliminary recording of the sixth counter 31 by writing a number in it (setting the conversion factor according to the information in memory register 33. At the output of the sixth counter 31, a unit signal is set which, through the second element NOT 46, blocks the passage of the generator 40 pulses to the input of the Record the sixth counter 31 by allowing it to work at the counting input.When the sixth counter 31 receives the number of pulses of the generator 40, the zero signal is set again according to the set conversion factor Mesch, and the conversion factor is set to 4g, c4 according to the information, currently in register 33 of memory

Thus, depending on the information recorded in the memory register 33, the scaling factor changes and at the output of the sixth counter 31 pulses are generated with a period of (1 j.,) That are transmitted through the seventh element AND 18 and the third element OR 37 subtractive input of the fourth counter 29.

When the number of pulses of the fifth counter 30 arrives at the subtracting input of the third counter 28 in accordance with the conversion factor, it is set to the zero state. The zero signal from its output at the pre-installation input writes the starting code into the fourth counter 29 (sets the recalculation coefficient M1, n,),

03481. 12

S -init installs a second RS -. the trigger 10 is in the unit (operating) state and through the third element NOT 47 is applied to the first input of the third to the 5th element AND-NOT 44.

This element of time is taken as the beginning of the elementary period Tjj. j- and the beginning of the working impulse

1R.TYAG

 The next impulse from the third counter 28 through the third element IS-HE 44 is fed to the input of the preliminary recording of the third counter 28, the number in it is recorded in accordance with the established recalculation coefficient.

At the output of the third counter 28, a single signal is set that permits operation of the fourth

20 counter 29 by counting platoon, as well as through the third element NOT 47 blocks the passage of counting pulses to the input of the preliminary recording of the third counter 28, allowing

25 his work on the counting entrance.

I

Upon admission to the subtractive

the input of the fourth counter 29 of the number of pulses of the sixth counter 31 in accordance with the conversion factor Ni, c4 ° is set to the zero state and the output zero signal at the R input sets the second RS trigger 10 to the zero state. At the output of the second RS - 5 trigger 10, a working pulse is generated. T, ..

When the number of pulses of the fifth counter 30 arrives at the counting input of the third counter 28, a zero signal is again set in accordance with the set conversion factor of the output and the initial installation of the fourth counter 29 is performed again,

45 installation of the second RS trigger 10 in working condition and preparation for the initial installation of the third counter 28.

At the same time, the formation of an elementary period of t of Nic4 f is completed during which one working impulse i is formed.

thirty

rt g

The pulses from the output of the third counter 55 are fed to a controlled frequency divider 41, the division factor of which is set by the speed setting unit 39 (second

ry output outputs). The preset Nyny division factor is set by the output pulses of a controlled frequency divider 41 at the pre-recorded input.

Thus, at the output of the controlled divider 41 frequencies, impulses are formed from a peoiop of the following T-urch.r g--. T "r-Mut, h; e-Tv,. where Tg, is the period of the inverter output voltage

When pulses with a period of the following Tour are sent, the doctor at the seventh counter 32 (a counter with a recalculation factor of 6), an inverter switch key code is generated at its outputs, which is fed to the parallel-connected information inputs of the first 48 and second 49 decoders. Such a construction of the inverter control system provides the same number of pulses in both half-waves of the three phases of the output voltage.

However, in the state of the higher bit of register 33 of memory 1, the first decoder 48 is blocked by the second (scramble; it) input, and the enabling (zero) signal is fed to the gate input of the second decoder 49, the outputs of which form a six-phase pulse (zero) signal. ) lasting 60 each.

The generation of pulses controlling the keys of the three-phase bridge inverter is performed by the inverter 50 of the control pulses (Fig. 2).

Consider the generation of control pulses for the keys 56-1 and 37-4 of phase A of the inverter driver 50 of control pulses. (Designation of the outputs of the first 48 and second 49 decoders (Fig. 2) the following is adopted: 48: 1 - the first output of the first decoder, 49: 3 - the third output of the second decoder, etc.

Each of the inverter switches conducts for 180.

The key 57-4 of the inverter 55 is turned on (the key 56-1 is turned off).

When the eighth element I 19 is supplied to the input zero zero from the output (49: 3) of the second decoder 49 via the S input, the third Rs trigger 11 is set to state 1, i.e. control signal is turned off

0

:

203481. 1 /

from the key 57-4 (the signal O from the inverse output of the third Rs trigger 11 is fed to the input of the eleventh element I 22), and the enabling signal to switch on the key 56-1 is sent (the signal f from the forward output of the third RS flip-flop 11 to the input the tenth element And 21),

However, a zero pulse from the output of the eighth element AND 19 through the fourth element OR 38 triggers the delay element 64 at time tj at the inputs of the tenth 21 and eleventh 22 elements and a signal is set to prohibit {turn on) At the end of the delay tj of the delay element 64, the tenth element is locked And 21 (signal 1 is sent from the code of the delay element 64) and from its code the key 56-1 is supplied with the switching signal

After 1 VO, the zero signal comes from the output (49: 6) d, the decoder 49 and through the ninth element I 20 to

.- "S R-input it sets the third RS-flip-flop 11 to the state O and through the fourth element OR 38 turns on the element 64 delay, - the trigger 11 turns off the key 56-1 and

30 gives the enable signal to power up20

cue key (signal 1 with the inverse output to the input of the eleventh element And 22). However, the eleventh element And 22 blocked

the zero signal of the delay element 64 and the activation of the key 57-4 will occur - after a time of 1 after the lock of the eleventh element is removed

And 22.

Similarly, pulses from the outputs (49: 1) and (49: 4) of the second decoder 49 in the driver 62 generate control pulses.

56-3 and 57-6 and pulses with the output (49: 5) and (49: 2) of the decoder 49 in the control puller 63, the key control pulses are formed 56-5

57-2 inverter 55.

Thus, the driver 50 of the control pulses performs the following functions: the formation, through 180 control pulses, of the key inverter 55; blocking the simultaneous activation of two keys of the same phase (elimination of the through short-circuit of the power source

or) a delay of ± j on the second switch on when the first switch is turned off and vice versa (the delay time tj is chosen from the condition where 1 1 off. the maximum possible turn-off time for the keys of the inverter 55).

Control pulses to the keys 57-2, 57-4, and 57-6 of the cathode group 57 of the inverter 55 are delivered through a cathode pulse amplifier 53, where they are amplified and galvanically isolated.

Control pulses for keys 56-1, 56-3 and 56-5 of the anode group 56 of the inverter 55 are fed through the modulator 51 and the anode Pulse amplifier 52.

In the modulator 56 (Fig. 3), the first inputs of the twelfth 23, thirteenth 24, and fourteenth 25 I elements are fed to the control pulses of the keys 56-1, 56-3 and 56-5 with the driver 50 of the control pulses, and to the second inputs And 23-25 - working impulses ip. from the output of the second RS trigger 10. Thus, in the modulator 51 using the twelfth 23, thirteenth 24 and fourteenth 25 elements And, the modulation of the control pulses of the keys of the anode group of 56 pulses of frequency

 e t g -:;:

 3f .t

The keys of the inverter 55, switching in accordance with a predetermined switching algorithm determined by the second decoder 49 and the driver 50, control pulses are generated. on the windings of inductor 1 of an arc-emitting asynchronous motor (/ - TNTG,.,

l 3 tension ber.t g-g-

 .Ruard

the frequency of Lt r -:;: and directly

Tet g

order of phase alternation, where gi bpii ghcH period of the output voltage of the inverter 55 in traction

mode, esch N

SCS

t,

N,

N,

 “.Tr-gi-m5sch sck; - the amplitude value of the inverter output voltage (in the absence of regulation).

Inductors 1 create a traveling magnetic field of a certain direction, which, interacting with the rotor15

03481 6

element 2, creates a torque of the required size. With

 - bs t g, / ,. ., this is the ratio of N ti l-Mcssch NVJ V.

; - V-TRAG

5 N t4 7C i rH - ln characterizes the magnitude of the torque of the engine 3.

Since the information inputs of the first 30 and sixth 31 meters are connected to the bit outputs

| memory register 33, and the fifth 30 and sixth 31 counters are switched synchronously with the generator 40 pulses fed to their opposite counting inputs (to the summing input of the fifth counter 30 and to the subtracting input of the sixth counter 31), then the code change to (h 1) the lower bits of the memory register 33 lead to the opposite change in the conversion factor NJ5t ((and with an increase in the code at the outputs of the memory register 33, the Nsc4 coefficient decreases, and the Enhance 2 coefficient decreases, and, conversely, as the code decreases, the MBFS coefficient increases and coeff Cycle N is reduced.

Thus, when increasing the code of the register of the 33 memory in the traction mode (the state of the most significant bit is 60 of the register of the 33 memory 1) the frequency

ivr. t

20

: V t g

and attitude

bt g.

5 increases, and consequently, the angular velocity and torque of the engine 3 increase, and, conversely, as the code decreases, the frequency

L / l p -g g

0 f p, T-YAR ratio decreases, and consequently, the angular velocity and rotational moment of the engine 3 decrease.

Consider the transformation of information located in memory register 33 at the torque of engine 3 at zero state of the senior (nth) bit 60 of memory register 33 (output 50 - O, output 59 0 1 (braking mode).

While the sixth element And 17 through the second element OR 36 connects to the counting input of the third counter 28 output of the sixth counter

5 31, and the fifth element AND 16 through the third element OR 37 connects to the counting input of the fourth counter 29 an output of the fifth counter 30..

17

Nl the second (gating) input of the first decoder 48 receives a zero signal permitting its operation, and a second signal to the second (gating) input of the second decoder 49 receives a single signal blocking it.

Further conversion of information located in the memory register 33 in the high-bit state 60 O is similar to information conversion in the memory register 33 in the high bit state 60 1. In this case, the duration of the elementary period T:, f gorm -tru bsh Sword J duration of the working impulse tpropM t. 5СЧ М i.

The keys of the inverter 55, switching in accordance with a predetermined switching algorithm determined by the first decoder 48 and the control pulse shapers 50,

form on the windings of the inductor 1 I1

motor 3 voltage uft.cp toripp. ropm-

and.

by frequency

f.

TaeGorm T'TORM

and reverse phase rotation, where Tg, -t.rf, -N6C4 Msc the period of the output voltage of the inverter 55 in the braking mode.

Inductors 1 create a running magnetic field of the opposite direction, which, interacting with the rotor element 2, creates a braking moment of the required magnitude.

gti oh wed tori

With this attitude

i. 9.10РГЛ

 (Mticii Muotz. Gi - -Ju) characterizes the amount of engine brake torque 3.

When the code is increased by (h - 1) lower bits of the memory register 33, the N504 coefficient decreases, and the M coefficient (-c increases, and, conversely, as the code decreases, the Mch. Coefficient increases, and the coefficient decreases. Thus, memory register 33 in the braking mode (state of the highest bit 60 of memory register 33 O) frequency and idsrlro ratio (b increase, and consequently, the braking torque of the engine 3 increases, and, conversely, with increasing code frequency and rpm. trot

0348118

and, consequently, the braking torque of the engine 3 decreases.

Consider the dependence of magnitude 5 and the direction of torque of the engine 3 on the magnitude of the actual angular velocity of the output shaft of the regulator, ij OfecJ, p (the error of the regulator is positive, (A –J 0),

to

t, e, angular. engine speed

less than the specified).

In this state, the senior (h-ro) bit 60 of memory 33 block 1, and the (h - 1) lower bits set the restriction code "The engine develops the maximum torque M MTNR (ififr.msc with - moment of resistance); increasing angular velocity.

2) (jJujp- Jg - - IQ. (Given the angular velocity, the error of the regulator is positive AuJ 0).

In this case, the high bit of 60 bit of block 33 of memory 1, and

(h 1) the lower bits set the code, the smaller the code limit; -: and. The moment of the engine M M. tg. Lx increases the angular velocity.

3) (-Jo 53, (oL jHOKa of the regulator 4uJ 0).

In this state, it is from the first division 60 block 13. Memory 1. Engine torque Ml. t, e „the angular speed of the engine is constant,

  -i -i3 6 uJnp. where oJnp

the speed at which a change in the state of the most significant bit of the 60 block of the 33 memory from 1 to 0 occurs, i.e. the rate of change of the engine's operating mode from traction to brake (the error of the regulator is negative - O, i.e. the angular velocity of the engine is greater than the specified one)

In this condition, the old starter is on bit 60 of block 33 of memory 1 Motor torque O Md. those. engine angular speed decreases. f

5) oJnp uJ (control error is negative),

In this state, the high-order bit is 60 register 33 of memory O. Moment of the motor OM M p. those. the motor operates in an electromagnetic brake mode and the motor torque is directed against the shaft rotation, reducing the angular velocity of 6-J iJa kz.r.

191203481

In this state, the high-order bit is 60. The register has 33 memory, O, and the initial code is set on (and - 1) low-order bits.

The engine develops a maximum: the braking moment of M. ORM THERMAL ID reducing angular.

Thus, in the controller, the frequency and voltage of the inverter are regulated in two ways:

Depending on the set angular speed of the motor, the frequency and voltage of the inverter are set by the speed setting unit 39 with the help of the first 26, 30 and sixth 31 counters and controlled 80

20

frequency frequency (change in the duration and number of elementary

and the duration of the work

periods Tj intervals tp);

when the angular velocity changes relative to the frequency and voltage of the inverter set during the adjustment, the fifth 30 and sixth 31 counters control the third, the second 28 and fourth 29 counters and the second RS trigger 10 change the duration of the working intervals t p and the duration of the elementary periods T.5. ( with a constant number of them over the period of the inverter voltage (constant division factor of the controlled frequency divider 41).

Fy-g f

to 50k 52

Fi.Z

VNIIPI Order 8415/50 Circulation 862 Signature {th branch IPP Patent, Uzhgorod, Proektna St., 4

Claims (1)

DIGITAL ANGULAR SPEED REGULATOR OF THE ARCTIC ASYNCHRONOUS MOTOR, comprising inductors connected in series and a rotor element of the arcing asynchronous motor, the output of which is through the series-connected speed sensor, the first and second pulse shapers, the first RS-flip-flop, the first AND element and the first counter are connected to the R-input of the first RS-flip-flop, whose inverse output is connected through the second and third AND elements in series to the counting input of the second counter connected by the bit outputs to the information inputs of the memory register and restriction unit, connected by the output directly to the second input of the third AND element and through the first OR element to the synchronization input of the memory register, the third pulse shaper, the input of which is connected to the output of the second shaper pulses, and the output is directly to the second input of the first OR element and through the fourth pulse shaper to the pre-recording input of the second counter, a speed setting unit, the bit outputs of which are connected to the information inputs of the first counter connected by the pre-recording input to the output of the first pulse shaper, a pulse generator, the output of which is connected to the second inputs of the first and second elements AND, the third counter, the output of which is connected to the 5 input of the second RS-trigger and the input pre recording of the fourth counter connected to the R-input of the second RS-flip-flop, characterized in that, in order to increase the accuracy of the controller in operation and expand the range of regulation of angular velocity, a controlled frequency divider, fifth, sixth and seventh, are introduced into the controller counters, first, second_and third elements AND NOT, first, second. swarm and third elements NOT, fourth, fifth, sixth and seventh AND elements, second and third OR elements, first and second decoders, control pulse shaper, modulator, anode and cathode pulse amplifiers, direct current source and three-phase bridge inverter containing six keys , the power inputs of the inverter are connected to the output of the DC source, the first, third and fifth keys are connected to its positive pole, and the fourth, sixth and second keys are connected to the negative pole, the control inputs of the first group of keys are connected respectively, with the outputs of the anode pulse amplifier, and the second group of keys with SU <. „1203481 outputs” of the cathode pulse amplifier, the inverter outputs are connected respectively to the outputs of the first and fourth keys, third and sixth keys, fifth and second keys, and also respectively to the first, second and third inputs of the motor inductor, (and - 1) the bit outputs of the memory register are connected to the information inputs of the fifth and sixth counters, the output of the fifth counter is connected directly to the first inputs of the fourth and fifth elements AND and through the series-connected first elements NOT and AND-NOT - with its input ohm of the preliminary recording, the output of the sixth counter is connected directly to the first inputs of the sixth and seventh AND elements and through the second elements HE and NAND NOT connected in series with its preliminary recording input, the counting inputs of the fifth and sixth counters are connected to the second inputs of the first and the second AND-NOT elements and the output of the pulse generator, the second inputs of the fourth and seventh elements AND are connected to the direct output of the high order of the memory register, the inverse output of the high order of the memory register is connected to the second by the moves of the fifth and sixth AND elements, the first and second inputs of the second OR element are connected respectively to the outputs of the fourth and sixth AND elements, and the output is connected to the counting input of the third counter, the output of which is connected directly to the counting Input of the controlled frequency divider and through the third elements connected in series NOT and AND-NOT - with its pre-recording input, the second input of the third AND-NOT element is connected to the output of the second OR element, the first and second inputs of the third OR element are connected to the outputs, respectively of the fifth and seventh elements And, and the output is with the counting input of the fourth counter, the information inputs of the controlled frequency divider are connected to the second bit outputs of the speed setting unit, and the output of the controlled frequency divider is connected directly to its preliminary recording input and through the seventh counter to the first inputs of the first and second decoders, the second inputs of which are connected respectively to the direct and inverse outputs of the high-order bit of the memory register, and the outputs, respectively, to the · first and second inputs are formed control pulse generator, the first and second outputs of which are connected respectively to the input of the cathode pulse amplifier and through the modulator to the input of the anode pulse amplifier, the second input of the modulator is connected to the output of the second RS-trigger, the gate input of the restriction unit is connected to the direct output of the first RS - trigger.