GB1586846A - Signal analysis arrangement for a communications transmission system - Google Patents
Signal analysis arrangement for a communications transmission system Download PDFInfo
- Publication number
- GB1586846A GB1586846A GB24042/78A GB2404278A GB1586846A GB 1586846 A GB1586846 A GB 1586846A GB 24042/78 A GB24042/78 A GB 24042/78A GB 2404278 A GB2404278 A GB 2404278A GB 1586846 A GB1586846 A GB 1586846A
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- United Kingdom
- Prior art keywords
- signal
- input
- integrator
- auxiliary signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 44
- 230000000737 periodic effect Effects 0.000 claims abstract description 8
- 230000000903 blocking effect Effects 0.000 claims description 7
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 230000004044 response Effects 0.000 claims description 2
- 230000001629 suppression Effects 0.000 claims description 2
- 230000037431 insertion Effects 0.000 abstract 1
- 238000003780 insertion Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 230000001419 dependent effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/06—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
- H04B14/062—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation using delta modulation or one-bit differential modulation [1DPCM]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/06—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
- H04J3/125—One of the channel pulses or the synchronisation pulse is also used for transmitting monitoring or supervisory signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
Abstract
The circuit arrangement is used for suppressing switching interference during the insertion of a periodic bit pattern, generated by an n-stage shift register (Si) with feedback, into the bit stream of the useful signal. The signal evaluating circuit (As) at the receiving end, which is permanently connected to the incoming transmission channel and has an n-stage shift register (Si) using a combinational logic (O), also contains a comparator (O1), the first input of which is connected to the output of the combinational circuit and the second input of which, together with the input of the shift register, forms the input of the signal evaluating circuit. The signal evaluating circuit furthermore comprises an integrator (IR) with a threshold circuit at the output, the input of which can be optionally connected via a change-over switch (Se) at the receiving end to the output of the comparator (O1) or a clock source (T). The change-over switch at the receiving end is controlled by means of a coincidence circuit (KZ) via the shift register, in such a manner that it connects the clock source (T) to the integrator input with at least n+1 equal successive bits for the duration of this state. <IMAGE>
Description
(54) SIGNAL ANALYSIS ARRANGEMENT FOR A
COMMUNICATIONS TRANSMISSION SYSTEM
(71) We, SIEMENS AKTIENGES
ELLSCHAFT, a German Company, of
Berlin and Munich, Federal Republic of
Germany, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: - The invention relates to a signal analysis arrangement for a communications transmission system (particularly, though not exclusively those employing delta modulation,-in particular t.d.m. communications transmission systems) comprising a transmitting-end auxiliary signal generator which produces a periodic bit pattern, wherein, where required, the auxiliary signal generator can be connected in place of the useful signal source via a transmitting-end change-over switch to the transmission channel, and wherein, at the receiving end, the signal analysis circuit is permanently connected to the incoming transmission channel.
A delta modulation communications transmission system of this type is disclosed by the
US Patent 3 727 005. In order to avoid an additional outlay in bandwidth, the auxiliary signals normally required in such systems are transmitted not in a separate transmission channel but within the useful signal channel to which the auxiliary signals are assigned.
The auxiliary signals are in this case gated into a predetermined time slot in place of the useful signal at the output end of the transmitting-end delta modulator. No loss of useful signal need occur since, for example in the case of a speech transmission system, the auxiliary signals representing ringing signals and dialling signals occur at times in which it is unnecessary to transmit speech.
Ïn order to recognise the auxiliary signals at the receiving end it is necessary for the signal analysis circuit provided for this purpose to be constantly connected to the transmission channels, i.e. in other words it is necessary to additionally process the useful signals. Practice has indicated that under these conditions the useful signal influences the signalling information in such a way that signal distortion occurs in the auxiliary signals.
According to one aspect of the present invention there is provided a communications transmission system including: a transmittingend auxiliary signal generator comprising an n-stage shift register and logic gating means responsive to the content of the register, the output of the logic gating means being fed back to the serial input of the shift register whereby to produce a periodic bit pattern having a maximum period length of 2"--1 bits; a transmitting-end change-over switch whereby, where required, the auxiliary signal generator can be connected to the transmission channel in place of the useful signal source; a switching device at the transmitting end which, in use, replaces the useful signal by a continuous signal for a predetermined length of time when the useful signal is reconnected following transmission of the auxiliary signal; a signal analysis circuit at the receiving end permanently connected to the incoming transmission channel, the signal analysis circuit comprising an n-stage shift register which receives the incoming signal at its serial input, logic gating means responsive to the content of the register in the same way as that of
the auxiliary signal generator, comparator means whose first input is connected to the output of the logic-gating means of the signal analysis circuit and whose second input is connected to receive the incoming signal, an integrator having an output-end threshold value circuit, which integrator can at its input be selectively connected via a receiving-end change-over switch to the output of the comparator means or a pulse train source; the receiving-end change-over switch being controlled by means of the shift register via a coincidence detector in such manner that on the occurrence of at least n + 1 identical, consecutive bits, for the duration of this state it connects the pulse train source to the integrator input.
In another aspect, the invention provides a signal analysis arrangement for a communication system as described above, the arrangement comprising an n-stage shift regis ter which receives the incoming signal at its serial input, logic gating means responsive to the content of the register in the same way as that of the auxiliary signal generator, comparator means whose first input is connected to the output of the logic gating means of the signal analysis circuit and whose second input is connected to receive the incoming signal, an integrator having an output-end threshold value circuit, which integrator can at its input be selectively connected via a receiving-end change-over switch to the output of the comparator means or a pulse train source; the receiving-end change-over switch being controlled by means of the shift register via a coincidence detector in such manner that on the occurrence of at least n+l identical, consecutive bits, for the duration of this state it connects the pulse train source to the integrator input.
In a preferred embodiment, the transmitting-end switching device consists of a bistable trigger stage having an additional blocking input at which, when the auxiliary signal generator is connected to the transmission channel, a blocking signal is active which remains active for a predetermined length of time when the next switch-over takes place.
The substantial decoupling of the useful signal from the auxiliary signal, relative to the receiving-end analysis circuit, advantageously produces the possibility of establishing the threshold value of the threshold value circuit, arranged at the output-end of the integrator, to be such that the system-related distortions in the mean value of the pulse duty factor which occur in the entire transmission path are largely reduced.
Furthermore, in the interests of satisfactory operation, it is effective to select the value of the time constant of the integrator in dedependence upon the period length of the
bit pattern to be sufficient to prevent the useful signal from simulating an auxiliary signal.
In the following, an exemplary embodiment of the invention will be explained in further detail with reference to the accompanying drawing, in which: Figure 1 is a partial block circuit diagram of the transmitting end and receiving end of a communications transmission system in accordance with the invention; and
Figure 2 shows various time diagrams of the voltages occurring in the block circuit diagram in figure 1.
The left-hand side of the block circuit diagram illustrated in figure 1 shows a transmitter S and the right-hand side thereof shows a receiver E of a communications system for the transmission of speech which has a communications transmission channel ÜK and employs delta modulation. For a plurality of transmission channels operated in t.d.m., the transmitter S at its output end arid the receiver E at its input end would each have to be supplemented by a multiplexer to which further channel assemblies would be connected, to the input of the multiplexer at the transmitting end and to the output of the multiplexer at the receiving end. The transmitter S has an auxiliary signal oscillator HG which, however, would only have to be provided once as it could be used for all the channels.This is indicated in figure 1 by the broken line at the output end of the auxiliary signal generator HG.
In addition to a subscriber circuit Tln, the transmitter S possesses a low-frequency
terminal circuit ES which is connected on the one hand to the input of a delta modulator
DM and on the other hand to a signal converter ZU. The output end of the delta modu lator is adjoined by a bistable trigger stage
K whose output is connected to one terminal of a transmitting-end change-over switch Ss.
The other terminal of this change-over switch is connected to the auxiliary signal generator
HG. The latter consists of a four-stage shift register Si and of logic gating means in the form of an EXCLUSIVE-OR-gate 0 which provides feedback for the shift register Si.
The output of the signal converter ZU controls a disabling input of the bistable trigger stage K and the transmitting-end changeover switch Ss. From the common contact of the transmitting end change-over switch Ss, the items of information from the transmitter S pass via a transmission channel UK to the receiver. As it is only the analysis device for the auxiliary signal which is of interest in the context of the present invention, the block circuit diagram shows only the relevant blocks.In addition to a signal analysis circuit AS, the receiver E possesses at its output end a signal converter ZU, a low-frequency terminal circuit ES and an adjoining subscriber station Tln. Similarly to the auxiliary signal generator HG at the transmitting end, the signal analysis circuit
AS comprises a four-stage shift register Si with a logic gating means in the form of an EXCLUSIVE-OR-gate 0. However, here the output of the EXCLUSIVE-OR-gate 0 is not fed back to the input of the shift register but is connected to one input of a further EXCLUSIVE-OR-gate 01. The other input of this further EXCLUSIVE-OR-gate and the input of the shift register Si together form the signal input of the signal analysis circuit AS. The further EXCLUSIVE-OR- gate 01 is connected via an inverter I to one connection contact of a receiving-end changeover switch Se, whose other connection contact is connected to a pulse train source T.
The common contact of the receiving-end change-over switch Se is connected to the input of an integrator which at its output feeds a threshold value circuit which has not been shown in detail. The signal converter
ZU is controlled via the output of the integrator IR and from its output supplies the subscriber Tln with the recognised ringing signals and dialling signals via the lowfrequency terminal circuit ES. As can be also seen from figure 1, the signal analysis circuit AS also comprises a coincidence circuit KZ which is controlled from the output of the shift register and which, in dependence upon at least five consecutive identical bits, switches over the receiving-end change-over switch Se into the second switching position illustrated in broken lines in figure 1.
In further explanation of the circuit illustrated in figure 1, figure 2 shows several time diagrams a, b, c and d on the basis of which the mode of - operation of the circuit in figure 1 will now -be explained further.
The letters a - to d may be found in figure 1 at the points at which the voltage curves represented in the correspondingly designated time diagrams occur. Firstly however we shall briefly discuss the interplay between the transmitting-end auxiliary signal generator and the receiving-end shift register and its linking logic.
The shift register Si of the auxiliary signal generator has n stages and the feedback via the EXCLUSIVE-OR-gate 0 is effected in such a manner that a periodic bit pattern having a maximum length 2n~1 occurs as auxiliary signal Hs, in time of a pulse control unit (not shown in detail in figure 1). As can be seen, when inserted into the shift register
Si of the signal analysis circuit AS at the receiving end, the auxiliary signal Hs obtained in this way will, when at least n bits have occurred at the output of the EXCLUSIVE- OR-gate 0, supply the same signal as is present at this instant of time at the input of the shift register Si.Via the further logiclinking of the further EXCLUSIVE-OR- gate 01, at the output of this gate a continuous d.c. signal appears in the form of a "0" which is inverted via the inverter I into a "L". In other words, at the receiving end in the signal analysis circuit, a transmitted auxiliary signal
HS is represented as a continuous signal which is analysed via the integrator IR as a switching signal.
In the event of a call emitted from the subscriber Tln at the transmitting end, the signal converter ZU is caused to respond at the time tl in accordance with diagram a in figure 2, and consequently a signal becomes active - at the disabling input of the bistable trigger stage K and at the control input of the transmitting-end change-over switch Ss.
Here the transmitting-end change-over switch
Ss is brought from the switching position illustrated in figure 1 into the second switching position represented in broken lines and in this way the auxiliary signal generator HG is connected to the transmission channel ÜK.
The transmission of the auxiliary signal Hs in place of the useful signal Ns is now carried out, as can be seen from diagram b in figure 2, in the interval of time between tl and t3. During this interval of time, the bit pattern of the auxiliary signal Hs is repeated with the period P. At the time t3 the call is terminated and consequently the signal converter ZU is reset into its original state (signal level "L"). At the same instant the ,transmitting-end change-over switch Ss is reset into its switching position illustrated in figure 1 and consequently the useful signal is reconnected to the transmission channel.
The signal at the blocking input of the bistable trigger stage K is still operative for the interval of time r by means of an RCelement (not illustrated in figure 1) so that it is not transmitted again until the end of this time section at the time t5. In other words, during the time interval r the useful signal is a continuous signal having the value "0", the effects of which upon the receivingend signal analysis circuit AS will be explained in detail in the following.
The diagram c illustrates the voltage course across the integrator. With normal speech transmission in the time zone until tl, the integrator input is alternately supplied with bits of the value "0" and "L" which on average produce a voltage U312 across the integrator, where U3 is to be understood as the operating voltage which is equal to the amplitude value of "L". The integrator voltage itself fluctuates about this mean value in dependence upon whether an accumulation
of "L" values or "0" values occurs.
The threshold of the threshold value circuit which forms part of the integrator IR is established at the value 3UBI4. The time t2 at which this threshold is exceeded in accordance with the diagram c in figure 2 is dependent upon the instantaneous value which the integrator voltage exhibited at the time tl. This useful-signal-dependent phase jitter represents a signal distortion. This effect is reduced in that the output of the shift register Si of the signal analysis circuit AS is followed by the coincidence circuit KZ which in the present exemplary embodiment responds and connects the integrator via the receiving-end change-over switch Si to the pulse generator T for such time as at least five identical bits occur consecutively in the incoming signal.The pulse duty factor of the pulse generator T is exactly 1 so that the voltage U31 is set up exactly across the integrator. Here it has been assumed that the amplitude of the pulse train oscillation is likewise equal to the operating voltage UB.
In other words, in the region of the transition of the useful signal into the auxiliary signal the coincidence circuit KZ reduces the possible fluctuations of the voltage across the integrator about the value U312 and con
sequently reduces the signal distortions in this
time zone. The design of the coincidence cir
cuit KZ for five consecutive, identical bits
is achieved in that in this exemplary embodi
ment the auxiliary signal possesses a periodic
bit pattern of 15 bits with which a maximum
of four identical bits can occur in succession.
In this way it is ensured that the coincidence
circuit does not respond on the arrival of an
auxiliary signal. At the end of the transmis
sion of the auxiliary signal at the time t3
the signal, which is continuous for the time
section r, causes the receiving-end change
over switch Se to switch over to connect the
pulse generator T to the input of the integra
tor TR. The outcome is that adulteration of
the rear flank of the auxiliary signal by the
useful signal Ns is suppressed because the
oscillation of the pulse generator exactly es
tablishes the voltage U312 towards which the
integrator voltage strives with the time con
stant of the integrator commencing at the time t3.
As has already been pointed out, the substantial suppression of the phase jitter at the signal boundaries of the auxiliary signal by means of the measures provided by the invention facilitates a substantial compensation of system-related distortions, occurring in the transmission path, of the mean value of the auxiliary signal duration by setting the threshold of the threshold value circuit. In particular, in this way it is possible to compensate distortions which are due to differing response and fall times of the relays provided in the signal converters ZU.
The invention is based on the recognition that the signal distortions occurring in a receiving-end analysis circuit employing an integrator are fundamentally due to a phase jitter which arises as a result of the voltage of the integrator being influenced by the useful signal in the time zone of the transition between useful signal and auxiliary signal and vice versa. The measures provided by the apparatus slightly reduce this influence in the region of the front flank of the auxiliary signal and entirely suppress the influence in the region of the rear flank of the auxiliary signal.
WHAT WE CLAIM IS:- 1. A communications transmission system including: a transmitting-end auxiliary signal generator comprising an n-stage shift register and logic gating means responsive to the content of the register, the output of the logic gating means being fed back to the serial input of the shift register whereby to produce a periodic bit pattern having a maximum period length of 2"1 bits; a transmitting-end change-over switch whereby, where required, the auxiliary signal generator can be connected to the transmission channel in place of the useful signal source; a switching device at the transmitting end which, in use, replaces the useful signal by a continuous signal for a predetermined length of time when the useful signal is reconnected following transmission of the auxiliary signal; a signal analysis circuit at the receiving end permanently connected to the incoming transmission channel, the signal analysis circuit comprising an n-stage shift register which receives the incoming signal at its serial input logic gating means responsive to the content of the register in the same way as that of the auxiliary signal generator, comparator means whose first input is connected to the output of the logic-gating means of the signal analysis circuit and whose second input is connected to receive the incoming signal, an integrator having an output-end threshold value circuit, which integrator can at its input be selectively connected via a receiving end change-over switch to the output of the comparator means or a pulse train source; the receiving-end change-over switch being
controlled by means of the shift register via a
coincidence detector in such manner that on
the occurrence of at least n + 1 identical, consecutive bits, for the duration of this
state it connects the pulse train source to the integrator input.
2. A system as claimed in claim 1, in which the transmitting-end switching device consists of a bistable trigger stage having an additional blocking signal input at which, when the auxiliary signal generator is connected to the transmission channel, a blocking signal is active which remains active for a predetermined length of time when the next switch-over takes place.
3. A system as claimed in claim 1 or 2, in which the threshold value of the threshold value circuit arranged at the output end of the integrator is established to be such that the system-related distortions, occurring in the entire transmission path, of the mean value of the auxiliary signal duration are largely eliminated.
4. A system as claimed in any one of the preceding claims, in which the time constant of the integrator is selected in dependence upon the period length of the bit pattern to be sufficient to ensure that the useful signal is in practice unable to simulate an auxiliary signal.
5. A communications transmission system substantially as herein described with reference to the accompanying drawings.
6. A signal analysis arrangement for a communications system according to claim 1, the arrangement comprising an n-stage shift register which receives the incoming signal at its serial input, logic gating means responsive to the content of the register in the same way as that of the auxiliary signal generator, comparator means whose first input is connected to the output of the logic gating
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (6)
1. A communications transmission system including: a transmitting-end auxiliary signal generator comprising an n-stage shift register and logic gating means responsive to the content of the register, the output of the logic gating means being fed back to the serial input of the shift register whereby to produce a periodic bit pattern having a maximum period length of 2"1 bits; a transmitting-end change-over switch whereby, where required, the auxiliary signal generator can be connected to the transmission channel in place of the useful signal source; a switching device at the transmitting end which, in use, replaces the useful signal by a continuous signal for a predetermined length of time when the useful signal is reconnected following transmission of the auxiliary signal; a signal analysis circuit at the receiving end permanently connected to the incoming transmission channel, the signal analysis circuit comprising an n-stage shift register which receives the incoming signal at its serial input logic gating means responsive to the content of the register in the same way as that of the auxiliary signal generator, comparator means whose first input is connected to the output of the logic-gating means of the signal analysis circuit and whose second input is connected to receive the incoming signal, an integrator having an output-end threshold value circuit, which integrator can at its input be selectively connected via a receiving end change-over switch to the output of the comparator means or a pulse train source; the receiving-end change-over switch being
controlled by means of the shift register via a
coincidence detector in such manner that on
the occurrence of at least n + 1 identical, consecutive bits, for the duration of this
state it connects the pulse train source to the integrator input.
2. A system as claimed in claim 1, in which the transmitting-end switching device consists of a bistable trigger stage having an additional blocking signal input at which, when the auxiliary signal generator is connected to the transmission channel, a blocking signal is active which remains active for a predetermined length of time when the next switch-over takes place.
3. A system as claimed in claim 1 or 2, in which the threshold value of the threshold value circuit arranged at the output end of the integrator is established to be such that the system-related distortions, occurring in the entire transmission path, of the mean value of the auxiliary signal duration are largely eliminated.
4. A system as claimed in any one of the preceding claims, in which the time constant of the integrator is selected in dependence upon the period length of the bit pattern to be sufficient to ensure that the useful signal is in practice unable to simulate an auxiliary signal.
5. A communications transmission system substantially as herein described with reference to the accompanying drawings.
6. A signal analysis arrangement for a communications system according to claim 1, the arrangement comprising an n-stage shift register which receives the incoming signal at its serial input, logic gating means responsive to the content of the register in the same way as that of the auxiliary signal generator, comparator means whose first input is connected to the output of the logic gating
means of the signal analysis circuit and whose second input is connected to receive the incoming signal, an integrator having an outputend threshold value circuit, which integrator can at its input be selectively connected via a receiving-end change-over switch to the output of the comparator means or a pulse train source; the receiving-end change-over switch being controlled by means of the shift register via a coincidence detector in such manner that on the occurrence of at least n+l identical consecutive bits, for the duration of this state it connects the pulse train source to the integrator input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA328,416A CA1129408A (en) | 1978-05-26 | 1979-05-25 | Cephalosporin antibiotics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2729633A DE2729633C3 (en) | 1977-06-30 | 1977-06-30 | Circuit arrangement in a message transmission system with delta modulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1586846A true GB1586846A (en) | 1981-03-25 |
Family
ID=6012841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB24042/78A Expired GB1586846A (en) | 1977-06-30 | 1978-05-30 | Signal analysis arrangement for a communications transmission system |
Country Status (10)
| Country | Link |
|---|---|
| BE (1) | BE868632A (en) |
| CH (1) | CH634697A5 (en) |
| DE (1) | DE2729633C3 (en) |
| DK (1) | DK294278A (en) |
| FR (1) | FR2396464A1 (en) |
| GB (1) | GB1586846A (en) |
| IE (1) | IE46958B1 (en) |
| IT (1) | IT1108744B (en) |
| LU (1) | LU79887A1 (en) |
| NL (1) | NL7806866A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2948307C2 (en) * | 1979-11-30 | 1982-02-18 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement in a communication system with delta modulation |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1033241B (en) * | 1957-04-04 | 1958-07-03 | Siemens Ag | Method for switching a service connection on demand to an operating channel of a time-division multiplex teletype system with automatic error correction |
| NL161323C (en) * | 1968-02-23 | 1980-01-15 | Philips Nv | TIME MULTIPLEX TRANSMISSION SYSTEM FOR SIGNAL TRANSMISSION USING PULSE CODE MODULATION. |
| US3727005A (en) * | 1971-06-30 | 1973-04-10 | Ibm | Delta modulation system with randomly timed multiplexing capability |
| NL155997B (en) * | 1972-06-24 | 1978-02-15 | Philips Nv | TRANSFER SCHEME. |
| DE2517481C3 (en) * | 1975-04-19 | 1978-07-13 | Siemens Ag, 1000 Berlin U. 8000 Muenchen | Method for shortening the synchronization time in time division multiplex systems, in particular data division multiplex systems |
-
1977
- 1977-06-30 DE DE2729633A patent/DE2729633C3/en not_active Expired
-
1978
- 1978-05-30 GB GB24042/78A patent/GB1586846A/en not_active Expired
- 1978-06-02 CH CH604678A patent/CH634697A5/en not_active IP Right Cessation
- 1978-06-26 NL NL7806866A patent/NL7806866A/en not_active Application Discontinuation
- 1978-06-26 FR FR7819013A patent/FR2396464A1/en active Granted
- 1978-06-27 IT IT25008/78A patent/IT1108744B/en active
- 1978-06-28 LU LU79887A patent/LU79887A1/xx unknown
- 1978-06-29 IE IE1305/78A patent/IE46958B1/en unknown
- 1978-06-29 DK DK294278A patent/DK294278A/en not_active Application Discontinuation
- 1978-06-30 BE BE188982A patent/BE868632A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IT7825008A0 (en) | 1978-06-27 |
| IE46958B1 (en) | 1983-11-16 |
| FR2396464B1 (en) | 1983-02-04 |
| LU79887A1 (en) | 1978-12-07 |
| DE2729633C3 (en) | 1983-11-03 |
| BE868632A (en) | 1978-10-16 |
| FR2396464A1 (en) | 1979-01-26 |
| IE781305L (en) | 1978-12-30 |
| NL7806866A (en) | 1979-01-03 |
| DE2729633B2 (en) | 1980-06-12 |
| IT1108744B (en) | 1985-12-09 |
| DE2729633A1 (en) | 1979-01-04 |
| DK294278A (en) | 1978-12-31 |
| CH634697A5 (en) | 1983-02-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |