GB1586350A

GB1586350A - Method of manufacturing a semiconductor device

Info

Publication number: GB1586350A
Application number: GB2253378A
Authority: GB
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1977-10-21
Filing date: 1978-05-25
Publication date: 1981-03-18

Description

(54) A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (71) We, NCR CORPORATION of Dayton in the State of Ohio, and Baltimore in the State of Maryland, United States of America, a corporation organized under the laws of the State of Maryland, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a method of manufacturing a semi-conductor device.

Semiconductor devices commonly employed include insulated gate devices such as insulated gate field effect transistors. A known insulated gate field effect transistor includes a semiconductor substrate of a first conductivity type having provided in a surface thereof source and drain regions of a second conductivity type.

A conductive gate electrode separated from such surface by insulating material spans the region separating the source and drain regions, thereby defining a channel region.

An overlap may exist between the gate electrode and the source and drain regions.

Such overlap has the disadvantage of tending to increase the capacitance of the gate electrode and hence reduce the switching speed of the transistor.

It is an object of the present invention to provide a method of manufacturing a semiconductor device whereby the aforementioned disadvantage may be alleviated.

Therefore, according to the present invention, there is provided a method of manufacturing a semiconductor device, including the steps of providing a semiconductor substrate, forming an electrode layer adjacent a surface of said substrate, forming on said electrode layer a masking layer having a first boundary, utilizing said masking layer to form from said electrode layer an electrode having a second boundary spaced apart from said first boundary in a direction along said surface and lying under said masking layer, and utilizing said first boundary to control doping of said substrate to form a doped impurity region having a third boundary aligned with said second boundary.

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figs. 1 to 1 lB illustrate cross-sections taken across a semiconductor substrate at successive stages during the manufacture of a semiconductor device according to a first embodiment of the invention; Fig. 12 illustrates a cross-section taken across a semiconductor substrate at one stage during the manufacture of a semiconductor device according to a second embodiment of the invention Figs. 13 to 16 illustrate cross-sections taken across a semiconductor substrate at successive stages during the manufacture of a semiconductor device according to a third embodiment of the invention; Figs. 17 and 18 illustrate cross-sections taken across field effect transistors manufactured by a method according to the invention.

Referring first to Fig. 17, there is shown a cross-sectional view taken parallel to the channel of a self-aligned silicon gate field effect transistor 10 manufactured by a method according to the present invention.

Although the description is directed to the fabrication of the transistor 10, it will be appreciated that the transistor 10 is merely exemplary of devices which may be manufactured by methods according to the invention. Also, the process parameters are exemplary of alternatives which will be readily applied by those skilled in the art to implement the disclosed process.

The device 10 comprises a substrate 11 of one conductivity type, illustratively, P-type, within which spaced-apart surface-adjacent regions of the opposite conductivity type form source 12 and drain 13. A thick layer 16 of dielectric, typically silicon oxide, is formed on the substrate 11 for isolating the device 10. A gate structure comprising silicon oxide gate insulation layer 18 and silicon gate electrode 21 overlies the channel region between the source 12 and drain 13. The opposite edges of the gate structure are coincident with the source and drain inner edges 28 and 29 (the opposed inner edges of the junctions of the source and drain with the substrate), such that the gate structure does not overlap the source and drain. For purposes of illustration, electrical contacts 22 and 23, respectively, are shown connected to the source 12 and the drain 13 for applying bias voltages which, in cooperation with the gate voltage applied via electrical contact 24, control the conduction path and current across the channel region. Those skilled in the art will understand that electrical contact is usually made at a single point along each of a pair of diffusion stripes which provide the source and drain for a plurality of devices. Other insulating materials, passivating materials, and electrical connections and interconnections (not shown) may be applied as needed to complete the protection of and the integration of the transistor 10 with other components.

The thicknesses and other dimensions shown for the device 10 are selected for clarity of illustration and are not to scale.

Typical thicknesses, dictated by the current state of the art, are: source 12 and drain 13 junction depth, about 2.2.5 microns for channel and one micron for n-channel; field oxide 16, about 1.5-2.0 microns; gate oxide 18, about 0. I micron (1,000 Angstroms); silicon gate electrode 21, about 0.5 micron; source and drain contacts 22 and 23, about 4 microns; and gate contact 24, about 4 microns. Also, the gate structure length (measured along the longitudinal dimension of the channel between the source and drain in the plane of the drawing) and width (measured laterally of the channel length perpendicular to the plane of the drawing) are typically approximately 3 microns by 10 microns but could be made smaller or larger. At least some of these dimensions, such as junction depth, can be expected to decrease with improvements in process technology. In any event, it is obvious that meaningful scale representation of such widely varying dimensions is impossible within limited drawing space.

The present fabrication process provides a self-aligned structure in which the source and drain are formed in precisely aligned, non-overlapping relationship with respect to the gate structure.

Referring now to Figs. 1 to 12 an exemplary process briefly comprises step 1: forming a layer of silicon nitride 6 on a semiconductor wafer 11 (Fig. 1) step 2: selectively removing the silicon nitride layer to leave a layer 7 of active device areadefining silicon nitride which is approximately coextensive longitudinally and laterally of the substrate with the subsequent location and shape of the combined source, gate and drain (Fig. 2); step 3: forming a thick field oxide layer 16 on the substrate 11 about the sides of the nitride layer 7 (Fig. 3); step 4: removing the silicon nitride layer 7 to leave the active device area 43 defined on the substrate by the oxide layer 16 (Fig. 4); step 5: forming an oxide layer 34 in the channel area (Fig.

5); step 6: forming a silicon layer 36 on the oxide layer 34 (Fig. 6); step 7: forming a photoresist mask 37 over and extending longitudinally outside the gate region (Fig.

7); step 8: overetching the silicon layer 36 under the mask 37 to form silicon gate electrode 21 having opposite edges 41 and 42 lying inside the opposite edges 38 and 39 of the mask (Fig. 8); and, step 9: selectively forming the oxide layer 34 to the desired shape of the gate oxide 18 (Figs. 9A and 9B).

In one embodiment, the process next uses separate deposition and drive-in steps to form the source and drain. First, superficial layers 48 and 49 of impurities are deposited in the substrate using the mask 37 (step 10B: Fig. 10B deposition may be ion implantation) or the gate oxide 18A (step 10A: Fig. 10A deposition may be by diffusion of impurities or ion implantation) as a deposition mask to form the impurity layers with edges 51 and 52 spaced a predetermined distance outside the gate electrode 21. Then, the impurities are driven into the substrate by high temperature diffusion for a time sufficient to attain the desired junction depth, x1, and align the impurity layer edges 51 and 52 with the opposite edges 41 and 42 of the silicon gate (step 11: Figs. 1IA and lIB), thus completing the source and drain.

The two step, diffusion deposition- diffusion drive-in approach is particularly useful where the device is subjected to subsequent high temperature processing steps. This is because the two step approach permits depositing the impurity layers 48 and 49 to an initial, predetermined junction depth and to initial, predetermined lateral edges 51 and 52 such that the particular subsequent high temperature process step(s) (whether used for other fabrication steps or used solely for drive-in purposes) will drive the impurities into the substrate and laterally along the substrate to complete the source and drain at the desired junction depth and with inner edges 28 and 29 thereof coincident with the gate.

In a second embodiment, as an alternative to the two-step, deposition and drive-in sequence, and referring to Fig. 12, (step 10A'), formation of the source and drain can be done using a high temperature diffusion cycle to accomplish deposition and drive-in in a single process step. That is, using high temperature diffusion the impurities are deposited and driven into the substrate for a time sufficient to form the source and drain to the desired junction depth x, and with the inner edges 28 and 29 thereof coincident with the gate opposite edges 41 and 42.

Focusing upon the results of the crucial steps of the process, a photoresist mask 37 is formed on the previously formed silicon (Fig. 7). The peripheral boundary or boundary of the mask 37 includes opposite longitudinal edges 38 and 39 which extend the distance equal to the junction depth x, (the depth in the substrate of the sourcesubstrate junction and the drain-substrate junction) past the opposite longitudinal edges 41 and 42 of the peripheral boundary or boundary of the subsequently formed gate electrode 21. Referring to Fig. 8, the electrode 21 is then formed by undercutting the silicon layer 36 beneath the mask 37 (step 8). Next, the mask 37 is used to form oxide layer 34 to (1) a gate oxide 18A having a peripheral boundary or boundary of which opposite longitudinal edges 46 and 47 are aligned with the mask edges (step 9A) or (2) a gate oxide 18B having a peripheral boundary or boundary of which opposite longitudinal edges 44 and 45 are recessed beneath the mask (step 9B). As mentioned, the alternative oxide dimensions permit the use of (1) either diffusion or ion implantation (step 10A) or (2) ion implantation (step 10B) to form superficial impurity regions 48 and 49 having inner edges 51 and 52 which are controlled by the mask edges 38 and 39 or the oxide edges 46 and 47. In either case, the inner edges 51 and 52 of the boundaries of the impurity regions are initially spaced longitudinally approximately the distance x, from the silicon gate edges. Upon heating the substrate 11 (step 11A or 11B)to diffuse the impurities into the substrate and form the source and drain ofjunction depth xr lateral diffusion also occurs and the impurities are also driven laterally the distance xi from impurity layer inner edges 51 and 52 and into coincidence with the edges 41 and 42-of the gate. That is, source 12 and drain 13 are completed so that inner edges 28 and 29 of their boundaries are aligned with the gate edges 41 and 42.

The preceding discussion regarding steps 10 and 11 applies also to the alternative, one step, diffusion cycle shown in Fig. 12, step 10A', except that the diffusion cycle by which ions are deposited is continued, as required, to expand the initial impurity layers 48 and 49 to the desired dimensions of the source and drain. Again, the inner edges of the source and drain boundaries are aligned with the gate edges 41 and 42.

Referring in greater detail to Figs. I to 12, preparatory to the crucial oxide removal, impurity deposition, or impurity deposition and drive steps, in step I (Fig. 1) the silicon nitride layer 6 is formed on the substrate 11 to a thickness, e.g., of 1,500 Angstroms.

Exemplary techniques for forming the layer 6 include reacting ammonia, NH3, and silane (silicane) SiH4, in a reactor at approximately 8000 C, or reacting ammonia and silicon tetrachloride, SiCI4, in a furnace at approximately 9000 C. Those skilled in the art will appreciate that the parameters such as temperature and thickness may be changed, and other processes employed, for this and the other steps.

It may be desirable to grow a layer 8 of oxide (shown in phantom in Fig. 1) on the substrate 11 to increase adhesion of the silicon nitride layer 6 to substrate materials such as silicon. The oxide layer 8 also acts as a barrier to prevent the formation of hardto-etch compounds by the silicon nitride 6 and the silicon substrate 11. A thickness of about 1,000 Angstroms is suitable for the layer 8. One suitable technique is to steam grow the silicon oxide layer 8 at 9750C.

Other techniques such as pyrolitic decomposition and plasma deposition will be readily applied by those skilled in the art.

In step 2, the nitride layer 6 is formed to the active device area-defining layer 7 (Fig.

2). One technique is to etch the layer 6 through a mask (not shown). The mask can be a standard photoresist material which is applied in solution to the nitride, spun to promote a uniform coating, and then dried.

The resulting layer is exposed to ultraviolet light through a mask (not shown), developed to remove the areas which were exposed to light, and the developed image hardened by baking. The resulting exposed nitride areas are removed by etching in hot phosphoric acid.

In step 3 (Fig. 3), the field oxide 16 is grown about the edges of the channel nitride layer 7 and to a thickness of about 1.5 microns (15,000 Angstroms). As is done in growing oxide layer 8, the field oxide can be steam grown at 9750C.

In step 4, the channel-defining nitride layer 7 is removed by etching in hot phosphoric acid (Fig. 4). If the adherencepromoting oxide layer 8 is present, it is also removed, e.g., by etching using an etchant such as a 7:1 mixture by volume of ammonium fluoride and hydrofluoric acid.

This mixture etches silicon oxide at about 1500 Angstroms per minute at 330C and, at this temperature, will etch through the 1,000 Angstrom thickness of silicon oxide layer 8 to the substrate 11 in less than one minute.

Removal of the silicon nitride layer 7 or the nitride layer and the oxide layer 8 leaves channel region 43 defined within field oxide 16 on the surface of substrate 11.

In step 5 (Fig. 5), layer 34 of oxide is grown or deposited on the substrate 11 in the channel region 43. Growing the oxide in a dry O3 environment provides a good quality, relatively dense gate oxide; however, the aforementioned steam growth, pyrolitic decomposition, or plasma deposition techniques can be used. For the exemplary dry O3 growth, at 1,0000C the oxide layer is formed to the sufficient thickness of about 0.1 micron (1,000 Angstroms) in about 150 minutes.

The silicon layer 36 (Fig. 6) is formed on the silicon oxide surface in step 6 by, e.g., decomposition of silane. One suitable method employs the AMT Model 1200 reactor made by Applied Materials, 3050 Bowers Avenue, Santa Clara, California, and transports the silane in nitrogen carrier gas and decomposes the silane at 600 700do for deposition on the underlying silicon oxide.

At least several other techniques such as deposition in a furnace tube, evaporation, pyrolitic decomposition of e.g. SiC14 and H2 and cathodic sputtering can be used to form the silicon. It should be noted that the exemplary conditions are not suitable for the formation of single crystal silicon and the silicon will be formed in polycrystalline form, but that either single crystal or polycrystalline silicon can be utilized in the electrode 21.

The gate photoresist mask 37 is formed on the silicon layer 36 in step 7 (Fig. 7). The peripheral boundary of the mask is formed so that opposite edges 38 and 39 thereof are each spaced (in their longitudinal positions along the length of the channel) the distance of the source and drain junction depth, x,, from the subsequently formed (step 8) opposite edges 41 and 42 of the silicon gate electrode 21. Again, the mask may be formed as described in step 2 using suitable conventional photolithographic techniques.

In Fig. 8, step 8, the silicon layer 36 is etched about the mask 37 to the oxide layer 34 to form gate electrode 21. Preferably, the etchant, such as a mixture of hydrofluoric, nitric and acetic acids or a plasma etcher using CF gas selectively etches the silicon (etches the silicon much faster than the adjacent material). The etching treatment is applied for a sufficiently long time to form the silicon gate electrode 21 to the desired peripheral boundary, including longitudinally opposite edges 41 and 42 which define gate length along the length of the channel.

In step 9, the silicon oxide layer 34 is formed to the desired peripheral boundary of gate oxide 18. Referring first to step 9B (Fig. 9B), the oxide layer 34 may be selectively removed in the presence of the mask 37 so that longitudinal edges 44 and 45 of the resulting gate oxide 18B are either aligned with edges 38 and 39 of the mask 37 or are recessed (as shown) beneath the mask. For example, a selective etchant such as the 7:1 buffered mixture of hydrofluoric acid in ammonium fluoride can be used to overetch the oxide beneath the mask to form the gate oxide 18B recessed beneath the mask.

Referring to Fig. 9A, an alternative approach is to form gate oxide 18A with longitudinal edges 46 and 47 coincident with the photoresist mask edges 38 and 39, e.g., spaced x, from gate edges 41 and 42. The gate oxide 18A can then be used as a deposition mask for impurity layers 48 and 49. The gate oxide 18A can be formed by selective etching of a mask-defined, ion implanted region of oxide 34 or by ion milling or field-aided plasma techniques.

The selective etching is accomplished by using ion implantation to dope the oxide layer about the mask 37 outside the gate edges 46 and 47 with p-type dopant, such as boron, to a concentration of about 1019Cm-3. Then, an etchant, such as dilute hydrofluoric acid, is applied which selectively etches the doped oxide more quickly than the undoped oxide. For example, dilute hydrofluoric etchant removes oxide having a 10'9 Cm-3 concentration of boron about 5 times faster than it removes undoped oxide. For the 1,000 Angstrom thick oxide layer 34, the hydrofluoric acid would overetch the oxide about 200 Angstroms beneath the mask.

Ion milling and field-aided plasma etching techniques are unidirectional. When applied in the presence of mask 37, these techniques form the oxide to the same shape, size, and location as the mask. Thus, a predetermined size, shape, and location can be transferred directly from the mask to the gate oxide 18A. Ion milling can be done using an ion-milling system to impinge argon ions normal to the oxide surface to eject atoms from the surface and thereby remove the surface. One suitable system is a Veeco Micro Etch used with a VS 7760 pumping station, both available from Veeco Instruments, Inc., Terminal Drive, Plainview, New York. Field-aided plasma etching can be employed by applying an electric field normal to the surface to be etched to selectively direct the plasma ions of a CF4 gas plasma in a commercial plasma etcher. One suitable etcher is model no.

PFS/PDE/PDS-501 available from LFE Corporation, 1601 Trapelo Road, Waltham, Massachusetts.

In Figs. 10A and 10B, the mask 37 and/or the gate oxide 18 are used as deposition masks to define the impurity layers 48 and 49. As mentioned previously, the impurity layers 48 and 49 can be implanted or diffused. Implantation is more nearly unidirectional than is diffusion and implanted areas are thus more precisely defined by the mask outline. That is by positioning the bombardment system to direct the ions perpendicularly to the mask 37, the mask defines the inner edges 51 and 52 of the impurity layers approximately coincident with mask edges 38 and 39. This is true although the mask 37 is spaced from the substrate surface. The mask 37 thus may be used with implantation in both step 10A and step 10B.

The oxide 18A of step 9A is suitable for use as a deposition mask during diffusion as well as during implantation in step 10A. This is because the extensions 53 and 54 of gate oxide 1 8A provide a mask on the substrate which precisely defines the edges 51 and 52 of the deposited layers, regardless of which deposition process is used.

Those skilled in the art will realizdit may be desirable to implant impurities through an oxide layer to minimize substrate surface crystal lattice damage. This can be done by forming a layer of oxide outside gate oxide region 18A or 18B prior to implantation.

Alternatively, some or all of the thickness of the portions of oxide layer 34 outside oxide 18A or 18B may be left in place by an abbreviated step 9 or by eliminating step 9.

Referring to Fig. 12, step 10A', either mask 37 or gate oxide 18A may be used with the one step diffusion cycle. As is true for ion implantation per Fig. 10B, step 10B, or ion implantation or diffusion per Fig. 10A, step 10A, the deposition mask defines the inner edges 51 and 52 of the deposited impurity layers. For a short diffusion deposition time, edges 51 and 52 will be approximately coincident with the deposition mask edges. Most of the drive-in and lateral drive-in will be performed during the subsequent drive-in cycle. This is the situation represented by Figs. 10A and 1 IA, steps 10A and 1 IA. For longer diffusion deposition cycles, edges 51 and 52 still will be controlled by the mask edges, but will be increasingly close to outer edges 41 and 42 of the gate. At the opposite extreme from step 10A, the diffusion deposition cycle is continued for a sufficient time to drive-in the impurity layers to junction depth x and to laterally drive the edges 51 and 52 the distance xi into coincidence with the gate edges. That is, the diffusion deposition cycle is used to form the source and drain so that inner edges 28 and 29 are coincident with gate edges 41 and 42. This the situation shown in Fig. 12, step 10A'. Numerous twostep diffusion deposition and diffusion drive-in cycles are possible between the extremes of step 10A and step 10A'. Also, the length of the deposition and/or the drive-in will be varied to suit the desired junction depth and the individual fabrication process, including any subsequent high temperature process steps.

As an example of the application of steps 10 and 11, for diffusion, phosphorus-doped impurity layers can be formed in the substrate pursuant to step 10A, Fig. 10A or step 10A', Fig. 12 by subjecting a POCI3 compound source to about 900"C. If it is desired to drive-in the resulting layer, the substrate is heated, e.g. to about 1000"C pursuant to step 1 lA to drive the impurity layers isotropically into the substrate to complete the N-type source and N-type drain.

Because drive-in is approximately isotropic, in steps 10A', lIA, and 11B, the ions diffuse laterally (orthogonally relative to the perpendicular drive-in direction) along the substrate a like distance, i.e., about xl. This characteristic is utilized, by depositing the impurity layers through substrate surface regions having inner edges which are spaced the distance x from their respective nearest gate electrode edges 41 and 42 (step 10). Then, when the deposited layers are diffused into the substrate to the junction depth x in step 11, diffusion also drives inner edges of the layers laterally (including longitudinally along the channel) the distance x to form source 12 and drain 13 having their inner edges 28 and 29 aligned with the respective adjacent edges 41 and 42 of the gate electrode 21.

About 5001,500 Angstroms thickness of oxide 9, Fig. 7, may be formed on the polysilicon layer 36 after step 6 to enhance adhesion between the photoresist mask 37 and the polysilicon. This may be achieved by converting the upper surface of the silicon layer 36 to a layer 9 of silicon oxide, or by depositing silicon oxide on the polysilicon upper surface. The oxide outside the mask can then be removed after step 7 using the 7:1 buffered mixture of hydrofluoric acid in ammonium fluoride.

Finally, the remaining oxide under the mask would be removed at the same time as, or in the next process step following, removal of the mask.

The device 10 is typically completed to the form shown in Fig. 17.. by forming additional insulation, as needed, over the source 12 and drain 13 and etching openings through the insulation and forming the illustrative source, drain, and gate contacts 22, 23, and 24. Although the gate silicon electrode 21 is made conductive by the doping of step 10, an additional conducting layer of material (not shown) may be applied to the electrode to enhance electrical contact. (This doping may also convert the surfaces of oxide extensions 53 and 54 into unwanted conductors which connect the gate to the source and drain, To eliminate this condition, the doped surfaces of the extensions can be removed after step 10 or step 11. The contacts 22, 23, and 24 are typically of a conductive metal such as aluminium. A passivating layer (not shown) of material such as silicon oxide and connections and interconnections (not shown) may also be applied to the device.

Also, the gate and/or the field regions of the substrate may be doped during the fabrication process to control the threshold voltage and eliminate parasitic conduction paths. Such doping is conveniently done early in the process, prior to the introduction of obstructing structures such as the gate or the field oxide.

A third embodiment of the invention utilizes a scattering effect during ion implantation to effect deposition and drivein of impurity ions simultaneously and, if desired, without removing portions of the gate oxide layer 34. The preliminary steps I to 6, Figs. 1 to 6, may be used. In step 7, the mask 37 is formed as shown in Fig. 13 in a similar manner to step 7, Fig. 7, with the longitudinal dimension selected to provide a desired overlay Aw over each of the longitudinal edges 41, 42 of the silicon gate electrode 21. Subsequent steps include overetching the silicon layer 36 under the mask 37 to form silicon gate electrode 21 overlying the channel region and having opposite edges 41 and 42 lying inside the opposite edges 38 and 39 of the mask (step 8, Fig. 14); as an option, selectively forming the oxide layer 34 to the desired shape of the gate oxide 18; (step 9A, Fig. 15A); and, implanting impurities in the substrate to form source 12 and drain 13 (step 9 or 10, Figs. 15 or 16). The position of the mask edges 38 and 39 and the implantation energy are selected to concurrently drive the impurities into the substrate to the desired source and drain junction depth x so that by lateral scattering, the inner edges 28 and 29 of the source and drain are simultaneously formed in alignment with the opposite sides 41 and 42, respectively, of the gate electrode.

Referring further to Figs. 13 to 16 and focusing upon the results of the crucial steps of the process, the photoresist mask 37 is formed on the previously formed silicon (step 7, Fig. 13). The peripheral boundary or boundary of the mask 37 includes opposite longitudinal edges 38 and 39 which extend the distance Aw=x (the depth in the substrate of the source-substrate junction and the drain-substrate junction)+Tox (the thickness of gate oxide layer 34) past the future positions of the opposite longitudinal edges 41 and 42 of the peripheral boundary or boundary of the subsequently formed gate electrode 21. Referring to Fig. 14, the electrode 21 is then formed by over-etching or otherwise undercutting the silicon layer 36 so that each of the opposite edges or sides 41 and 42 is recessed the distance Aw beneath the mask edges 38 and 39, respectively (step 8).

In step 9 (step 10, Fig. 16) in the manner of step 9 (Fig. 15). The substrate is bombarded by ions within surface areas which are again determined by the boundaries of the mask 37. Here, the substrate surface areas are indicated at 61 and 62 and correspond to the oxide surface areas 56 and 57, step 9. As discussed regarding step 9, scattering effects lateral ion movement to complement the drive-in movement perpendicular to the plane of the substrate and form the source and drain at the desired junction depth xi with the inner edges 28 and 29 coincident with gate edges 41 and 42. Note that here T0x=0, and Aw=xj. Accordingly, the dimensions of the mask 37 are made such that the overlap relative to gate electrode 21 is Aw=xj and the implantation energy is decreased to accomplish the desired drive in and scatter for the lesser value Aw=x. It will be appreciated that the mask dimensions and ion acceleration energy can be varied to accommodate a wide range of oxide thicknesses, and that all or only a part of the thickness of the oxide layer 34 may be removed from areas 61 and 62.

Referring again to Fig. 13 (step 7), prior to formation of the photoresist mask in step 7, the upper surface of the silicon layer 36 can be converted to a layer 9 of silicon oxide (shown in phantom in Fig. 13, step 7) or the silicon oxide can be deposited on the silicon upper surface. The silicon oxide layer 9 increases adhesion of the photoresist to the silicon and thus enhances the masking characteristics of the photoresist during etching. About 50(we500 Angstroms thickness of oxide is suitable for this purpose.

The gate photoresist mask 37 is formed on the silicon layer (or on the oxide layer 9) 36 in step 7 (Fig. 13). The peripheral boundary of the mask is formed so that opposite edges 38 and 39 thereof are each spaced (in their longitudinal positions along the length of the channel) the distance Aw from the .subsequently formed (step 8) edges 41 and 42 of the silicon gate electrode 21. The mask may be formed as described in step 2 using suitable conventional photolithographic techniques.

If the adherence-promoting oxide layer 9 is used, it should be removed outside the gate region prior to formation of the gate electrode 21, using the buffered mixture of hydrofluoric acid in ammonium fluoride.

In step 8 (Fig. 14), the silicon layer 36 is etched about the mask 37 to form gate electrode 21. Etching is by a selective etchant, such as a mixture of hydrofluoric, nitric and acetic acids, which etches the silicon much faster than the adjacent material, here silicon oxide layer 18.

Alternatively, the electrode 21 can be formed by plasma etching using CF4 gas.

The etchant is applied for a sufficiently long time to form the silicon gate electrode 21 to the desired peripheral boundary, including longitudinally opposite edges 41 and 42 which define gate length along the length of the channel.

Next, depending upon whether implantation is to be through the existing oxide layer 34, or is to be done directly into the substrate surface or into a reduced thickness oxide layer 34, one proceeds directly to the implantation step 9 (Fig. 15), or forms the gate oxide in accordance with step 9A (Fig. 15A) before implanting pursuant to step 10 (Fig. 16). In the gate oxide-forming step 9A (Fig. 15A), the oxide layer 34 is formed to a gate oxide 18 having a peripheral boundary or boundary of which opposite longitudinal edges 46 and 47 are aligned with mask edges 38 and 39 (i.e., spaced Aw from gate edges 41 and 42; this is the embodiment shown in Fig. 15A, step 9A) or recessed beneath the mask (not shown).

Etching, using a selective etchant such as the buffered mixture of hydrofluoric acid in ammonium fluoride can be used to form the gate oxide 18 recessed beneath the mask.

The gate oxide 18 can be formed coincident with the mask edges by selective etching of a mask-defined, ion-implanted oxide 34 or by ion milling or field-aided plasma techniques as described for the first embodiment.

Those skilled in the art will realize it may be desirable to implant impurities through an oxide layer such as the layer 34 (step 9, Fig. 15) to minimize substrate surface crystal lattice damage. For this purpose, some of the thickness of the portions of oxide layer 34 outside gate oxide 18 may be left in place by an abbreviated step 9A (Fig.

15A). Alternatively, step 9A (Fig. 15A) can be used to remove the entire thickness of oxide outside the gate region prior to implantation directly into the substrate, or oxide can be formed to the desired thickness over the substrate after complete removal pursuant to step 9A and the substrate then implanted through the oxide.

To implant the source and drain, the mask 37 (the mask 37 and oxide 18) is (are) used as a deposition mask to define the implanted areas 56 and 57 in the upper surface of the oxide layer 34 (step 9, Fig. 15) or in areas 61 and 62 in the upper surface of substrate 11 (step 10, Fig. 16). Implantation is nearly unidirectional. By positioning the bombardment system to direct the ions perpendicularly to the mask 37, the inner edges of the initial surface-implanted areas are precisely aligned with mask edges 41 and 42 as discussed above and scattering is used to obtain the desired lateral drive-in during drive-in normal to the surface.

Typical ion implantation procedure is to ionize a gas containing the implant species in a high vacuum (10-6-10-7 torr is typical), then the resulting dopant ions are accelerated across an electric field of sufficient magnitude to implant the ions to the desired depth in a receiving medium such as substrate II. The gas may be ionized in a first chamber, the wafer or substrate 11 held in a second chamber, and the dopant ions accelerated between the first chamber and the second chamber. A suitable implantation apparatus is the Model 200- 20A2F by Varion/Extrion of Blackburn Industrial Park, Gloucester, Mass.

As an example of ion implantation according to step 9 or step 10, arsine, AsH3, gas is ionized to As+ at 10-3-10-7 torr and the As+ ions are subjected to an acceleration energy of 200 keV with a dose of about 10'3cm-2 to provide n-type source 12 and drain 13 of junction depth x,=0.5 micron and 102'cm-3 concentration.

Obviously p-type and other n-type ions can be used to form the source and drain.

The relatively heavy ions, such as the exemplary arsenic ions, and antimony ions, are relatively immobile at even the elevated temperatures used in semiconductor device fabrication. This characteristic permits greater control of the source and drain dimensions and location, because the heavy ions can be implanted to the desired final junction depth and alignment, which will be unaffected by subsequent processing.

When relatively light weight ions are implanted, it is desirable to tailor the initial junction depth achieved by implantation (and thereby the scatter-induced lateral drive-in) so that diffusion caused by subsequent high temperature processing will drive the ions to the desired junction depth xl and alignment. Of course the mask overhang is still determined by the junction depth x and is Aw=x1+T0.

The device 10 is completed to the form shown in Fig. 17 by removing the mask 37 and remaining portion of the oxide layer 9, forming additional insulation, as needed, over the source 12 and drain 13, etching contact openings through the insulation, and forming source, drain, and gate contacts 22, 23, and 24. The contacts 22, 23, and 24 are typically of a conducting metal such as aluminium. A passivating layer (not shown) of material such as silicon oxide and connections and interconnections (not shown) may also be applied to the device.

Those skilled in the art will appreciate that when the gate electrode 21 is of silicon, the silicon is made conductive by doping during the formation of the semiconductor device. This doping can be done in the reactor used to form the silicon layer 36 and as part of step 6. Alternatively, it may be possible to remove mask 37 (and any oxide layer 9) prior to implantation and use the gate oxide as the implantation mask. This requires that the thickness of the gate oxide 18 (see Fig. 16, step 10) be sufficiently greater than Tox (the thickness of the oxide, if any, over the source and drain)+xj to preclude doping the substrate through the gate oxide and thereby extending the source and drain beneath the gate electrode 21.

Assuming that this condition is satisfied, and that the mask 37 is removed and the gate oxide is used as the implantation mask, the silicon gate electrode 21 will be made conductive by doping during implantation of the source and drain. Of course, an additional conducting layer (not shown) can be applied to the electrode to enhance electrical contact.

The invention is not limited to formation of the exemplary silicon-oxidesemiconductor structure, but applies equally to gate structures or other projections of oxide, silicon, nitride, etc.

which are adjacent one or more diffused regions. For example, the polysilicon could be replaced by any refractory metal to form an MOS (metal-oxide-semiconductor) structure. Also, the SiO2 could be replaced by a composite of Si3N4 and SiO2 or of Al203 and SiO2. Furthermore, and referring to Fig.

18, a memory SNOSFET (silicon-nitrideoxide-semiconductor field effect transistor) or MNOSFET (metal-nitride-oxidesemiconductor field effect transistor) 40 having nitride layer 19 inserted between the gate oxide 18 and the gate electrode 21 may be formed using the process of the present invention. The SNOS and MNOS structures can be fabricated by forming the oxide layer in step 5; depositing a 500 Angstroms layer of nitride on the oxide after step 5; depositing the gate conductor layer 36 per step 6; performing steps 7 and 8; then, if desired, removing the nitride outside the gate region after step 8 using a selective etchant such as phosphoric acid.

If the SNOSFET or MNOSFET is to be a non-memory device, the gate oxide is formed sufficiently thick to prevent charge tunneling. For example, this could be done by forming oxide layer 34 to about 500 Angstroms in step 5. If the SNOSFET or MNOSFET is to be a memory device, the gate oxide is formed to about 160 Angstroms thickness.

The performance of the device 10 relative to that of prior art devices can be estimated as follows. First, the gate capacitance, Cg, is given by: C9=Àd, (1) where s=permittivity of the gate dielectric, d=thickness of the gate dielectric, and A,=gate area.

The gate area, As, is given by: Ag=W(Leff+2+p), (2) where w=gate width, L",=minimum effective gate length, i.e.

channel length, and p=length of overlap between the gate and the source and/or drain.

Combining equations (I) and (2), C5=Ew(L5+2pYd. (3) The ratio of the capacitance, Cgn(p=pn), for the present device 10 to that of prior art devices, C90(p=po), is obtained from equation (3) and, after cancelling like terms, is: Can (Leff+2pn) = (4) C90 (Le+2po). (4) Assuming that the prior art overlap p0 is equal to x,, which approximates both the junction depth and the lateral diffusion distance, and that the overlap, Pn, of device 10 is~O,

Then, for the typical values xixl micron and Let 4 microns, Cgn#.67Cgo. The device 10 is thus seen-to decrease gate capacitance by about one-third.

Consider next the MOS inverter delay, td, which is given by td R00C5( 1 + M). (6) where R0=.turn on resistance of the load device, and M=Miller coefficient, indicating the feedback capacity of the device.

The ratio of the time delay for device 10, tdn, to that for prior art devices, tdo, is tdn C9n(1+Mn) tdo CgoF l + Mo) and tdn~o.s7 tdo, where Mn~O, x~l micron Le"~4 microns,

C9n/C90~0.67, from (5).

In short, in typical applications the device 10 embodying the present invention can be expected to decrease gate capacitance by about one-third (C9n~0.67 C90) and to decrease the operating time delay by nearly one-half (tdfl0.57 tdo).

Thus, there has been described a process for forming a self-aligned, non-overlapping silicon gate device and an exemplary embodiment for forming a silicon gate FET.

Other alternative embodiments within the scope of the claims will be readily devised by those skilled in the art. For example, the invention is applicable in general to the fabrication of projections of oxide, silicon, etc. which are adjacent one or more diffused regions. Also, fabrication parameters such as etchants and etch times and temperatures will be readily changed by those skilled in the art.

WHAT WE CLAIM IS: 1. A method of manufacturing a semiconductor device, including the steps of providing a semiconductor substrate, forming an electrode layer adjacent a surface of said substrate, forming on said electrode layer a masking layer having a first boundary, utilizing said masking layer to form from said electrode layer an electrode having a second boundary spaced apart from said first boundary in a direction along said surface and lying under said masking layer, and utilizing said first boundary to control doping of said substrate to form a doped impurity region having a third boundary aligned with said second boundary.

2. A method according to Claim I, including the step of providing a layer of insulating material on said surface prior to said step of forming said electrode layer, said electrode layer being formed on said layer of insulating material.

3. A method according to Claim I or Claim 2, wherein said step of utilizing said first boundary to control doping of said substrate includes the steps of providing a superficial layer of impurities at said surface having a fourth boundary substantially aligned with said first boundary, and heating said substrate for a sufficient time to cause the deposited impurities to move into said substrate to form said doped impurity region.

4. A method according to Claim 3, wherein after said step of forming said electrode, a part of said layer of insulating material is removed to leave an insulator region thereof lying under said masking layer.

5. A method according to - Claim 4, wherein said insulator region has a fifth boundary aligned with said first boundary.

6. A method according to Claim 4 or

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. The gate area, As, is given by: Ag=W(Leff+2+p), (2) where w=gate width, L",=minimum effective gate length, i.e. channel length, and p=length of overlap between the gate and the source and/or drain. Combining equations (I) and (2), C5=Ew(L5+2pYd. (3) The ratio of the capacitance, Cgn(p=pn), for the present device 10 to that of prior art devices, C90(p=po), is obtained from equation (3) and, after cancelling like terms, is: Can (Leff+2pn) = (4) C90 (Le+2po). (4) Assuming that the prior art overlap p0 is equal to x,, which approximates both the junction depth and the lateral diffusion distance, and that the overlap, Pn, of device 10 is~O, Then, for the typical values xixl micron and Let 4 microns, Cgn#.67Cgo. The device 10 is thus seen-to decrease gate capacitance by about one-third. Consider next the MOS inverter delay, td, which is given by td R00C5( 1 + M). (6) where R0=.turn on resistance of the load device, and M=Miller coefficient, indicating the feedback capacity of the device. The ratio of the time delay for device 10, tdn, to that for prior art devices, tdo, is tdn C9n(1+Mn) tdo CgoF l + Mo) and tdn~o.s7 tdo, where Mn~O, x~l micron Le"~4 microns, C9n/C90~0.67, from (5). In short, in typical applications the device 10 embodying the present invention can be expected to decrease gate capacitance by about one-third (C9n~0.67 C90) and to decrease the operating time delay by nearly one-half (tdfl0.57 tdo). Thus, there has been described a process for forming a self-aligned, non-overlapping silicon gate device and an exemplary embodiment for forming a silicon gate FET. Other alternative embodiments within the scope of the claims will be readily devised by those skilled in the art. For example, the invention is applicable in general to the fabrication of projections of oxide, silicon, etc. which are adjacent one or more diffused regions. Also, fabrication parameters such as etchants and etch times and temperatures will be readily changed by those skilled in the art. WHAT WE CLAIM IS:

1. A method of manufacturing a semiconductor device, including the steps of providing a semiconductor substrate, forming an electrode layer adjacent a surface of said substrate, forming on said electrode layer a masking layer having a first boundary, utilizing said masking layer to form from said electrode layer an electrode having a second boundary spaced apart from said first boundary in a direction along said surface and lying under said masking layer, and utilizing said first boundary to control doping of said substrate to form a doped impurity region having a third boundary aligned with said second boundary.

6. A method according to Claim 4 or

Claim 5, wherein said part of said layer of insulating material is removed by an etchant.

7. A method according to Claim 5, wherein said part of said layer of insulating material is removed by ion milling utilizing said masking layer as an ion milling mask.

8. A method according to Claim 5, wherein said part of said layer of insulating material is removed by field-aided plasma etching utilizing said masking layer as a mask.

9. A method according to any one of Claims 4 to 8, wherein said step of providing a superficial layer is effected by diffusion utilizing said insulator region as a diffusion mask.

10. A method according to any one of Claims 4 to 8, wherein said step of providing a superficial layer is effected by ion implantation utilizing said masking layer as an ion implantation mask.

11. A method according to any one of Claims 4 to 8, wherein said step of utilizing said first boundary to control doping of said substrate includes the step of utilizing said insulator region as a diffusion mask to diffuse impurities into said substrate thereby forming said doped impurity region.

12. A method according to Claim 1 or Claim 2, wherein said step of utilizing said first boundary to control doping of said substrate includes the step of implanting ions into said substrate utilizing said masking layer as an ion implantation mask, the energy of the ions being implanted being sufficiently great that said doped impurity region is formed as a result of ion scattering.

13. A method according to Claim 2 and Claim 12, wherein after said step of forming said electrode, a part of said layer of insulating material is removed to leave an insulator region thereof which is aligned with or recessed beneath said masking layer.

14. A method according to Claim 12 or Claim 13, wherein said ions are ions of arsenic or antimony.

15. A method according to any one of the preceding claims, wherein the distance between said first and second boundaries is substantially equal to Xj+TOI where xj is the depth of said doped impurity region and Tox > O is the depth of insulating material, if any, which overlies said surface in the region of said doped impurity region during said doping of said substrate.

16. A method according to any one of Claims 2 to 15, wherein said insulator layer is formed of an oxide material.

17. A method according to Claim 16, wherein said oxide material is silicon oxide.

18. A method according to any one of the preceding claims, wherein said electrode layer is formed of silicon.

19. A method according to Claim 18, wherein said silicon is in polycrystalline form.

20. A method according to any one of Claims I to 17, wherein said electrode layer is formed of a refractory metal.

21. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to Figs. I to lIB or Figs. I to 9A and 12; or Figs. I to 6 and 13 to 16 of the accompanying drawings.

22. A semiconductor device when manufactured by a method according to any one of the preceding claims.