GB1584915A - Silicon devices - Google Patents
Silicon devices Download PDFInfo
- Publication number
- GB1584915A GB1584915A GB1843778A GB1843778A GB1584915A GB 1584915 A GB1584915 A GB 1584915A GB 1843778 A GB1843778 A GB 1843778A GB 1843778 A GB1843778 A GB 1843778A GB 1584915 A GB1584915 A GB 1584915A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon
- glass
- holes
- slice
- portions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Sensors (AREA)
Description
(54) IMPROVEMENTS IN OR RELATING TO SILICON DEVICES
(71) We, STANDARD TELEPHONES AND
CABLES LIMITED, a British Company of 190 Strand, London WC2, England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the' following statement: This invention relates to the manufacture of silicon devices.
A variety of electronic devices using thin silicon have been devised in recent years, one example being the so-called silicon relays described in our application No. 08302/78 (Serial No. 1584914), in which the variations in the electrical characteristics due to changes in its configuration are exploifed. Other applications of silicon include strain gauges.
In such devices it is desirable to be able to electrically isolate portions of silicon one from the other, e.g. when several silicon devices are produced from the same piece of silicon or on the same substrate. To do this the silicon can be provided with glass inserts or edge or corner portions, and an object of this invention is the production of silicon devices with such glass inlays.
According to the present invention there is provided a method of manufacturing a silicon device having one or more inserts or edge or corner portions of glass for insulative purposes, which inserts or edge or corner portions are discrete and separated from each other, which method includes subjecting a silicon slice to a selective etching process to produce one or more holes, or edge or corner cut-outs, filling said holes or cut-outs with glass frit without coating the surface of the slice with frit so that the filled holes-or cutouts are - separated from each other if more than one, and-fusing the device so as to leave the silicon slice with one or more discrete portions of glass, the glass portions if more than one being separated from each other by the silicon.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which Figs. 1 to 10 show various stages in the manufacture df silicon devices when using the present invention, while Fig. 11 is a perspective view of part of a completed silicon device made in accordance with the present invention.
The process to be described herein commences with slices of silicon which have < 100 > orientation and are polished on both sida. The first step involves the diffusion into the silicon of boron plus any other dopants required from both sides so that we get a 'sandwich' with doped layers on either side of an undoped layer. Next any oxide glass which has been produced during this diffusion process is removed, arid the top side of the slice is coated with aluminiurn' and photo etched using a first mask.
We now plasma etch the slice through the mask and the diffused layer to produce a structure as shown in Fig. 1, in which the boron-diffused' layers are not shown. However, the etching is to a depth such- that it extends through the upper diffused layer.
The next step is a selective etching process via the mask to produce relatively deep holes each of which extends almost to the bottom side of the slice. The presence of the borondiffused layer there stops the etch so that the diffusion only produces blind holes in the silicon slice. The holes thus produced are filled with glass frit and fused so'that we get the condition indicated in Fig. 2.
Next the top side of the slice is coated with aluminium and once again photo-etched using a second mask, whereafter the slice is plasma etched through the mask and the diffused layer to give the condition shown in
Fig. 3.
The bottom side of the slice is now coated with aluminium and photo-etched using a third mask, whereafter the bottom side is photo-etched through the mask and the diffused layer to give the condition show in
Fig. 4. It will be recalled that the bottom side as well as the top side was provided with a boron diffused layer at an early stage in the process.
The slice is now treated to remove all the aluminium since this is no longer needed now that the plasma etching steps have been performed. We now deposit contacts on to the slice, using chromium or gold, whereafter another photo-etch process is effected using a fourth mask. This gives the condition shown in Fig. 5, the contacts being indicated at 1, 2, 3.
Assuming that the device being made is to be one of a number of devices in an array on a substrate, we now follow the process steps to which Figs. 6, 7 and 8 relate. Initially a thick spacing layer which can be copper is deposited on the top side of the slice, whereafter it is subjected to another photo-etch using a fifth mask. This gives the result shown in Fig. 6, where the copper spacing layer is indicated at 4, 5.
After the deposition of the spacing layer 4, 5, fixed contacts and interconnections are deposited on the device, with another photoetch. This is followed by the deposition of a substrate, which is then fired or cured to give
Fig. 7. Here an interconnection is shown at 6, a fixed contact at 7, and the insulating substrate at 8.
The next step is to saw up the slices being treated, each of which before this sawing bears a large number of devices, into arrays of devices. We now have a selective etch, after which- spacing- layers such-as 4, 5, are etched away and the devices are mounted in suitable packages to give the arrangement shown in Fig. 8, where 9 is a wire bond. The selective etch, as can be seen from Fig. 8, bears a number of devices electrically separated from each other. Note here that as the side on which the fabrication steps were performed has been referred to as the top side, the fired devices produced thereby are upside down.
We now consider the production of a single relay for incorporation into a dual-inline-package (DIP) device, with reference to
Figs. 9 and 10. The arrangement of Fig. 5 receives a deposit of solder via a fifth mask, which deposit can be of the thick film type.
The slice is now sawn up and the chips thus produced are soldered into a lead frame connectable to the various contacts of the
DIP unit. This gives the arrangement of Fig.
9, where the solder portions are shown at 10, 12 onto which portions 15, 16 of the lead frame are soldered. A portion of the lead frame 17 is shown which is not soldered to, but happens to be above, a contact 18 on the slice.
Finally a selective etch is effected to produce the device shown at Fig. 10 whereafter the encapsulation is complete.
Fig. 11 shows in perspective and much enlarged a device made by the process described herein. In this figure, we have two areas 20, 21, of silicon separated from each other by a glass insert 22 whose function is to provide the insulation between the areas 20, 21. There are also glass inserts 23, 24, which act as etch stops at the corners.
We now summarise the process as applied to glass insert production.
Anisotropic etching techniques allow the fabrication of a variety of shapes in silicon but with certain limitations. By inlaying glass into the silicon slice some of these limitations can be removed.
The technique is to etch holes in the silicon slice using selective etch. A boron diffused layer on the opposite side prevents the holes going right through. On < 100 > orientation silicon it is easy to control the size of rectangular holes when their sides are < 111 > planes. The holes are filled with a glass frit by a modified screen printing process and, after any organic binder or medium has been driven off, the glass is fused. The slice, which now has glass inlaid areas, can be processed further; for example a further selective etching stage can form shapes that are defined by glass (which is unattacked) as well as the boron doped surface layers and < 111 > slow etching planes. The glass inserts can act as etch stops at external corners where otherwise there would be fast etching planes exposed. The glass can also be used for its insulating properties by etching away the surrounding silicon so that only glass is left between areas being insulated from one another.
It will be appreciated that a similar process is usable for the production of edges or corner inserts.
Claims (5)
1. A method of manufacturing a silicon device having one or more inserts or edge or corner portions of glass for insulative purposes, which inserts or edge or corner portions are discrete and separated from each other, which method includes subjecting a silicon slice to a selective etching process to produce one or more holes, or edge or corner cut-outs, filling said holes or cut-outs with glass frit without coating the surface of the slice with frit so that the filled holes or cutouts are separated from each other if more than one, and fusing the device so as to leave the silicon slice with one or more discrete portions of glass, the glass portions if more than one being separated from each other by the silicon.
2. A method as claimed in claim 1, wherein the opposite face of the silicon from which the holes are etched has a borondiffused layer which acts to limit the progression of the etch so as to produce blind holes, and wherein after the holes have been filled with glass a further etch is performed to remove said boron-diffused layer.
3. A method ás .claimed in claim 2, wherein initially blank faces of the silicon have boron diffused layers, the layer on said other face being selectively etched away at the points at which holes have to be made for glass.
4. A method of manufacturing a silicon device substantially as described with reference to the attached drawings.
5. A silicon device made by the method of claim 1, 2, 3 or 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1843778A GB1584915A (en) | 1978-05-09 | 1978-05-09 | Silicon devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1843778A GB1584915A (en) | 1978-05-09 | 1978-05-09 | Silicon devices |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1584915A true GB1584915A (en) | 1981-02-18 |
Family
ID=10112433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1843778A Expired GB1584915A (en) | 1978-05-09 | 1978-05-09 | Silicon devices |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1584915A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2136204A (en) * | 1983-01-26 | 1984-09-12 | Hitachi Ltd | A method of fabricating especially etching a diaphragm in a semiconductor device |
-
1978
- 1978-05-09 GB GB1843778A patent/GB1584915A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2136204A (en) * | 1983-01-26 | 1984-09-12 | Hitachi Ltd | A method of fabricating especially etching a diaphragm in a semiconductor device |
US4588472A (en) * | 1983-01-26 | 1986-05-13 | Hitachi, Ltd. | Method of fabricating a semiconductor device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |