GB1581550A

GB1581550A - Timing circuits

Info

Publication number: GB1581550A
Application number: GB3176676A
Authority: GB
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1976-07-30
Filing date: 1976-07-30
Publication date: 1980-12-17
Also published as: DE2734375A1

Description

(54) IMPROVEMENTS IN OR RELATING TO TIMING CIRCUITS (71) We THE PLESSEY COMPANY LIMITED, a British Company of Vicarage Lane, Ilford, Essex, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement : - This invention relates to timing circuits and is especially applicable to timing circuits for use in a.c. power control applcations using so-called proportional control systems.

At the present time in a.c. power control applications including heaters, transformers, relays, on-off lamp control, on-off motor control, it is becoming increasingly popular to use so called zero voltage switching techniques in the control of power applied to a circuit, pulses being generated at the zero voltage points of the supply voltage which are used to trigger say a triac into conduction, the triac then remaining in a conductive state until the supply voltage again falls to zero volts or thereabouts. In this way the load utilizes full half-cycles of the supply voltage as opposed to partial halfcycles with conventional phase control power circuits and transient current pulses and hence radio frequency interference, are virtually eliminated.

In addition, as well as using simple ON OFF switching which suffers from the disadvantage that 'overshoot' is inevitably obtained, called Iproportional control systems are becoming increasingly used in which a sawtooth waveform is generated, this typically taking the form of a ramp or triangular waveform, which is used in conjunction with a sensor e.g. negative temperature coefficient thermistor in temperature control applications for controlling the number of firing pulses that are applied to the triac. Thus on a temperature control application, at a desired temperature a certain number of pulses would occur, and the number of pulses would be increased or reduced proportionately dependent upon how much the absolute temperature differed from the desired temperature. If the absolute temperature was less than the desired temperature by a small amount then the number of firing pulses would be increased by a small amount whereas if the absolute temperature was less than the desired temperature by a large amount then the number of firing pulses would be increased by a large amount.

In some countries legislation is being introduced which endeavours to reduce the effects of so-called flicker noise by restricting the number of times the supply voltage may be switched in a given time period.

The period between successive switchings is normally made dependent upon the power to be switched and typically the period may be 32 seconds for a 2200 watt load, 14 seconds for a 1600 watt load and 6 seconds for 1200 watt load. In order to comply with this legislation use of the proportional control system has been proposed, it being arranged that the period of the sawtooth waveform corresponds to the minimum period between switchings. Such a system has been called a time proportional control system or a controlled switching rate system. In order to obtain a sawtooth waveform suitable for use with the high wattage loads it is therefore necessary to generate it with a period in the order of 30 - 35 seconds.

In generating the sawtooth waveform, whether it be of ramp or triangular form, use is normally made of a timing circuit which includes a capacitor which is charged either from a current source or via a resistor in order to generate the amplitudel time characteristic. For a lot of applications relatively short time constant circuits only are required, but in the afore mentioned time proportional control system time constants in the order of 30 - 35 seconds may typically be required and to obtain such time constant it is normally necessary to use large expensive high value e.g. 68atF electrolytic or possibly tantalum capacitors in order to achieve the low leakage and small tolerances required. Even so the capacitance tolerance is not always as good as may be required.

It is an object of the present invention to provide a timing circuit arrangement that is especially although not exclusively suitable for use in a.c. power control applications using proportional control systems based on zero switching techniques.

According to the present invention there is provided a timing circuit as aforesaid comprising capacitor means. charging means for causing the capacitor means to be charged, and charge chopping means for periodically interupting the supply of charge to the capacitor means to cause the effective time constant of the ciruit to be increased in dependence upon the duty cycle of the charge chopping means, the charge chopping means comprising diode means connected in series wifh the capacitor means and periodically operable switching means connected in parallel with the series connected diode means and capacitor means. The switching means may have pulse generating means associated therewith for controlling the duty cycle of the switching means.

By arranging that the duty cycle is say 9: 1 or 99 : 1 a chopped charging function is obtained the effective time constant is increased by 10 or 100 times as the case may be.

In order to generate a ramp waveform first comparator means responsive to the voltage of the capacitor means, may be provided affording an output when the voltage of the capacitor means exceeds a first reference voltage said output being used to effect discharge of the capacitor and preferably second comparator means responsive to the voltage of the capacitor means will be provided for affording an output when the voltage of the capacitor means falls below a second reference voltage, this output being used to terminate the discharge of the capacitor means and to initiate recharging thereby.

An exemplary embodiment of the invention will now be described, reference being made to the accompanying single figure drawing which shows a timing circuit according to the present inventon.

In the drawing a capacitor 1 is caused to be charged from a current source 2 via a normally forward conducting diode 11. A preferably electronic switch ' 3 operated by a pulse generator 4 is connected in parallel wit'h the series connected diode 11 and capacitor 1. The pulse generator 4 is arranged to have a duty cycle typically of 99 1 and it is arranged that the switch 12 is open for one time period and closed for 99 time periods. When the switch 12 is open the capacitor 1 is allowed to be charged from the current source 2 and when the switch 12 is closed the charging current bypasses the capacitor 1 but which is prevented from discharging due to the diode 11 being reverse biassed.

In this way the charging circuit of the capacitor 1 is interupted resultng in a staircase voltage waveform appearing across the capacitor 1. This have the effect of increasing the effective time constant of the circuit by 100 times or alternatively enables the same time constant to be obtained with a capacitor that is 100 times smaller.

In order to obtain a ramp waveform from the capacitor 1, the staircase voltage across it is applied to two voltage comparators 5 and 6, the comparator 5 being arranged to afford an output when the capacitor voltage exceeds a high reference level 7 applied to it, the output from the comparator 5 being applied via a logic circuit 8T to a capacitor discharge circuit 9 which causes the capacitor 1 to be discharged. The voltage across the capacitor 1 is also applied to the other comparator 6 which is arranged to afford an output when the capacitor voltage falls below a low reference level 10 applied to it. Thus as the capacitor 1 disdharges, when its voltage falls below the low reference level 10, the comparator 6 affords an output which is fed via the logic circuit 8 to the capacitor discharge circuit 9 to terminate the discharging of the capacitor 1 to allow it to be recharged.

The resulting voltage appearing across the capacitor 1 takes the form of a staircase waveform which is ideal for use in a proportional control system of an a.c. power control application. In time proportional control system it has been found that a time constant of 30 seconds may be obtained with a standard non-electrolytic laF capacitor compared with a usual electrolytic capacitor of 68,uP. In some applications, in order to reduce the loading on the capacitor it may be convenient to connect the input of the comparator 5 to the junction of the current source 2 and the diode 11 but in this case the comparator 5 must be able to operate satisfactorily with a chopped input.

Also instead of the current source 2 being used to charge the capacitor 1, a conventional resistive charge circuit may be used.

Although the timing circuit described finds particular applicaton in a.c. power control applications using proportional control systems, it is envisaged that it will find application in other areas where a chopped sawtooth waveform may be used.

WHAT WE CLAIM IS: 1. A timing circuit arrangement comprising capacitor means, charging means for causing the capacitor means to be charged, and charge chopping means for periodically interruptng the supply of charge to the capacitor means to cause the effective time constant of the circuit to be increased in dependence upon the duty cycle of the charge chopping means, the charge chopping means comprising diode means connected in series with the capacitor means and periodically operable switching means connected in parallel with the series connected diode means and capacitor means.

2. An arrangement as claimed in claim 1 in whidh the switching means has pulse generating means associated therewith for controlling the duty cycle of the switching means.

3. An arrangement as claimed in any claim 1 or 2 in which, in order to generate a ramp waveform there is provided a first comparator means responsive to the voltage of the voltage of the capacitor means and affording an output when the voltage of the capacitor means exceeds a first reference voltage said output being used to effect discharge of the capacitor.

4. An arrangement as claimed in claim 3, in which there is provided a second comparator means responsive to the voltage of the capacitor means and affording an output when the voltage of the capacitor means falls below a second reference voltage, this output being used to terminate the discharge of the capacitor means and to initiate recharging thereby.

5. An arrangement as claimed in claim 3 or 4, in which a discharge circiut is provided for effectng discharge of the capacitor means.

6. An arrangement as claimed in any preceding claim in which the charging means is a current source.

7. An arrangement is claimed in any one of claims 1 to 6 in which the charging means is a resistive charge circuit.

8. A timing circuit arrangement substantially as herein described with reference to and as illustrated in the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. find application in other areas where a chopped sawtooth waveform may be used. WHAT WE CLAIM IS:

1. A timing circuit arrangement comprising capacitor means, charging means for causing the capacitor means to be charged, and charge chopping means for periodically interruptng the supply of charge to the capacitor means to cause the effective time constant of the circuit to be increased in dependence upon the duty cycle of the charge chopping means, the charge chopping means comprising diode means connected in series with the capacitor means and periodically operable switching means connected in parallel with the series connected diode means and capacitor means.