GB1580808A - Sequence controller with a state memory for input and output elements - Google Patents

Sequence controller with a state memory for input and output elements Download PDF

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Publication number
GB1580808A
GB1580808A GB4815677A GB4815677A GB1580808A GB 1580808 A GB1580808 A GB 1580808A GB 4815677 A GB4815677 A GB 4815677A GB 4815677 A GB4815677 A GB 4815677A GB 1580808 A GB1580808 A GB 1580808A
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output
input
card
information
cards
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Toyoda Koki KK
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Toyoda Koki KK
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1125—I-O addressing
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1188—Detection of inserted boards, inserting extra memory, availability of boards

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Control By Computers (AREA)

Description

(54) SEQUENCE CONTROLLER WITH A STATE MEMORY FOR INPUT AND OUTPUT ELEMENTS (71) We, TOYODA KOKI KABUSHIKI KAISHA, a Japanese body corporate, of I-I, Asahi-machi, Kariyashi, Aichiken, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates generally to a sequence controller of the stored program type and, more particularly, to such a controller provided with a state memory for memorizing the operational states of input and output elements.
In such sequence controllers, basically, input cards (i.e. input power converter cards or modules) are successively selected prior to the execution of a sequence program and the closed and open states of input elements are read as ON and OFF signals. The read ON and OFF signals are memorized at memory areas of a rewritable state memory respectively assigned to the input cards. After execution of the sequence program, output elements are energized or deenergized in accordance with ON and OFF information being memorized at memory areas of the state memory respectively assigned to output cards (i.e. output power converter cards or modules) connected to the output elements.
Accordingly, in the sequence controllers, unless the input cards are distinguished from the output cards in a certain way so as not to select the output cards when the state memory reads the open and closed states of the input elements, null information comprising all " I" or "0" is memorized at memory areas of the state memory respectively associated with the output cards since the same are not provided with circuits which feed back the ON and OFF information for energization and deenergization of the output elements.
If the null information is read out as the ON or OFF information, all of the output elements are energized or deenergized regardless of the results of the examination, thus resulting in lack of control.
For this reason, in a prior-art device, assignment has been made with connectors connectable to input cards and connectors connectable to output cards. On reading the open and closed states of input elements, the connectors connectable to the input cards are selected, and rewritings of the states of the input elements are carried out.
However, such a device raises drawbacks in that, since the connectors connectable to the input cards and the connectors connectable to the output cards are fixed, the replacement of the input and output cards as well as the alteration of the input/output card ratio are impossible to perform.
It is therefore an object of the present invention to provide an improved sequence controller in which the input/output power converter card ratio is alterable as required, without system re-design and reconstruction.
Briefly, according to the present invention. there is provided a sequence controller which comprises to plurality of input power converter cards each connectable to at least one input element to convert closed and open states of that input element or those input elements into, respectively, ON and OFF signals; a plurality of output power converter cards each connectable to at least one output element to energize or deenergize that output element or those output elements in response to ON or OFF information supplied thereto; a plurality of connectors respectively connectable to said input and output power converter cards; a rewritable state memory having memory areas respectively assigned to said connectors to memorize the ON and OFF signals of the input elements and the ON and OFF information for the output elements, respectively, in those memory areas corresponding to said input and output power converter cards; a program memory for memorizing a sequence program; a card selector for successively designating said connectors and thereby selecting the input and output cards in a predetermined order; discrimination means for distinguishing said input power converter cards from said output power converter cards so as to output discrimination information; and an operation control device including first means for controlling said card selector and said state memory so as to successively memorize in said state memory the ON and OFF signals of only those input elements discriminated by the discrimination information supplied from said discrimination means, second means for controlling said program memory and said state memory so as to read out said sequence program from said program memory, to examine the states of the input elements in accordance with said sequence program and by reference to the contents of said state memory, and to rewrite the ON and OFF information for the output elements, being memorized in said state memory, in accordance with the results of the examination, and third means for controlling said card selector and said state memory so as to successively output the rewritten ON and OFF information from said state memory to said output power converter cards to thereby energize and deenergize respectively the output elements.
Since the sequence controller comprises discrimination means for distinguishing the input power converter cards from the output power converter cards so as to output discrimination information to the first means and, based upon the discrimination information, the first means controls the state memory to memorize the ON and OFF signals of only the input elements, this avoids the ON and OFF information for the output elements, being memorized in the state memory, being rewritten in accordance with null information delivered from an output card associated therewith, so that each of the input and output cards can be connectable to any desired one of the connectors.
Various other objects, features and attendant advantages of the present invention will be readily appreciated as the same becomes better understood from the following detailed description of a preferred embodiment when considered in connection with the accompanying drawings, wherein like reference numerals designate like or corresponding parts throughout the several views in which: Figure 1 is a block diagram illustrating an embodiment of a sequence controller according to the present invention Figure 2 is an exemplified circuit diagram of an input card shown in Figure 1; and Figure 3 is an exemplified circuit diagram of an output card shown in Figure 1.
Referring to Figure 1, 10a--10n denote a plurality of connectors, which are connected to input cards 11 (i.e. input power converter cards or modules) and output cards 12 (i.e. output power converter cards or modules) disposed in random order. Each of the input cards 11 is connected to input elements such as, for example push button switches PS10 and PS20, a limit switch LS3 and the like. Each of the output cards 12 is connected to output elements such as, for example, a relay CRI, solenoids SOLI1 and SOL12 and the like. The connectors l0a-l0n are connected to an input/output bus line IOB and signal lines 13 and 14 in a parallel relation with one another, and the input/output bus line JOB is in turn connected to a data bus DB.A card selector 15 delivers selection signals CS to the connectors 10a--10n, so that one input card 11 or one output card 12, which is connected to the connector receiving the selection signal CS, is selected. Thus, between the selected input card 11 or the selected output card 12 and the data bus DB, ON and OFF signals of the input elements or ON and OFF information for the output elements are transmitted as a block of signals of one card, that is, in the case where the number of input or output elements per each card is eight "8", as a block of eight bit signals.
Each of the input cards 12 is provided with a signal generating circuit, referred to later, which sends out a write-in signal WEN to the signal line ~ 14 upon receiving the selection signal CS. The signal generating circuit serves as discrimination means so as to distinguish the input cards 11 from the output cards 12.
A rewritable state memory 19 has memory areas of the number corresponding to the connectors 10a--10n. For example, in the case where one memory area is composed of eight bits for one word, the state memory 19 has words of the same number as that of the connectors 10a--10n.
The ON and OFF signals sent out from the input elements are memorized, as one block of eight bits, at one of the memory areas of the state memory 19 which one is assigned to the connector connected to one of the input cards 11. On the other hand, the ON and OFF commands for energization and deenergization of the output elements are memorized at one of the memory areas of the state memory 19 which one is assigned to the connector connected to one of the output cards 12.
Further, the ON and OFF signals of the input elements being output to the data bus DB are written, as new ON and OFF signals, at one memory areas associated with the selected input card 11 when a write-in-command WRITE is delivered from an operation control device 16, referred to later, to a read-out and write-in control circuit 20. The ON and OFF information or commands which heave been memorized at one of the memory areas associated with the selected output card 12, are read and sent out therefrom to the data bus DB when a read-out command READ is delivered to the control circuit 20.
The operation control device 16 is composed by way of example, of a small capacity computer such as a microprocessor and in accordance with a main program stored in a program or main memory 17, repeatedly performs three execution steps, which comprises the read execution of the ON and OFF signals of input elements, the execution of a sequence program and the read-out execution of the ON and OFF information for energization and deenergization of the output elements.
In the step of reading the ON and OFF signals of the input elements, address data for respectively designating the connectors 10a--10n, are sent out to the card selector 15 via an address bus AB and consequently, the input and output cards 11, 12 connected to the connectors 10a--10n are successively selected without discrimination. Whenever any one of the inputs cards 11 is selected, the write-in signal WEN is delivered to the operation control device 16 via the signal line 14, and the eight-bit ON and OFF signals, output to the data bus DB via the input/output data bus IOB, are written in at the memory area of the state memory 19 assigned to the connector connected to the selected input card 11.
In the subsequent step of executing the sequence program, the read-out command READ is delivered to the readout control circuit 18 so as to successively read out various commands of the sequence program stored in the main memory 17. If there is read out an examine command for examining the ON or OFF state of an input or output element, data which is of the ON and OFF signals of the input elements or the ON and OFF information for the output elements being memorized by the state memory 19, and which corresponds to the input or output element designated by the examine command, is read out and examined.To the contrary if the read-out command is an output command for energizing or deenergizing an output element based upon one or more examination results, the ON or OFF information at one of the memory bits of a memory area, which is assign.ed to the output element designated by the read-out command, is rewritten based upon the examine results.
In the step of reading out the ON and OFF information, address data for respectively designating the connectors 10a--10n is delivered to the card selector 15 so as to successively select the input and output cards without discrimination. The ON and OFF signals or information, which have been memorized at one of the memory areas associated with a selected input or output card, are read out from the state memory 19 and are output to the data bus DB. Since the input cards 11 are unable to read the ON and OFF signals, only the ON and OFF information, which have been read out from one of the memory areas of the state memory 19 assigned to the selected output card, is read by the selected output card 12. As a result, eight output elements, connected to the selected output card 12, are selectively and simultaneously energized or deenergized.
Figure 2 illustrates an example of the input cards 11, eight input terminals I-17 of which are respectively connected to one ends of the input elements comprising the push button switches PS10 and PS20, limit switches LS3 and LS27 and the like. These input elements, when closed, respectively apply AC voltage to level converters LCO--LC7. Each of the level converters LCeLC7 converts the applied AC voltage into a signal called "TTL level".
Signals output from the level converters tC--LC7 are respectively connected to one input terminals of NAND gates NG(NO7. The ON and OFF signals output from the NAND gates NGO--NG7 are delivered to the input/output bus IOB through the connector, for example, 10a connected to the input card 11.Each of the NAND gates NG-NG7 is composed of an integrated circuit (IC) having an open collector output lest the ON and OFF signals, output from the NAND gates NG(#NG7, should interfere with the ON and OFF signals sent out from the state memory 19, the operation control device 16 and the like, and output stages of the operation control device 16, the main memorv 17 and the state memory 19 are composed also of integrated circuits of the same type.
The selection signal CS, sent out from the card selector 15, is delivered to the input terminal INVI, acting as buffer amplifier, via the connector 10a. The inverted signal, output from the inverter INVI, is again inverted by an inverter INV2 and is input to all of the other input terminals of the NAND gates NG0NG7. Accordingly, when the selection signal CS is delivered to the input 7 card 11, then the NAND gates NG0NG7 are all opened, whereby the ON and OFF signals of the input elements are output to the input/output bus IOB.
Furthermore, the input card 11 is provided with the signal generating circuit 21 comprising an inverter INV3, which feeds back the write-in signal WEN on the arrival of the selection signal CS. Thus, the operation control device 16 finds that connected to the selected connector 10a is an input card 11 and causes the state memory 19 to memorize the eight-bit ON and OFF signals, having appeared on the input/output bus IOB, at one of the memory areas thereof assigned to the selected connector.
Figure 3 illustrates one example of the output cards 12. The ON and OFF information, output from the input/output bus IOB, are connected to input terminals of a latch circuit 31 via a connector, for example, 10b connected to the output card 12. This latch circuit 31 reads and memorizes the ON and OFF information, delivered to its input terminals, when receiving a signal at its trigger terminal and continues the output of the memorized ON and OFF information until new ON and OFF information are thereafter delivered thereto.The ON and OFF information from the latch circuit 31 is further delivered to power switches PC07PC7. These power switches PCO--PC7 energize or deenergize the assbciated output elements comprising the relays CR1 and CR20, solenoids SOLIl and SOL12 and the like, connected to output terminals O007, in accordance with the ON and OFF information, respectively.
Further, the selection signal CS and the write-in command WRITE, output from the card selector 15 and the operation control device 16, are forwarded via the connector 10b to both input terminals of an AND gate AGI, respectively. The AND gate AGI in turn forwards its output signal to the trigger terminal of the latch circuit 31. Consequently, when the output card 12, connected to the connector 10b, is selected by the card selector 15 and when the write in command WRITE is delivered from the operation control circuit 16, the ON and OFF information, having been output to the input/output bus IOB, is then read by the latch circuit 31, whereby the output elements are energized or deenergized.
Unlike the input card 11, the output card 12 is not provided with the signal generating circuit 21 and does not feed back the writein signal WEN even upon receiving the card selection signal CS. In this connection, when the connector 10b connected to the output card 12 is selected in the step of reading the ON and OFF signals of the input and output elements, rewriting is not carried out with the contents of the memory area of the state memory 19 which is assigned to the selected connector 10b. It can therefore be avoided that the ON and OFF information, being memorized at that memory area, would be re-written in accordance with null information which comprises all " I " in this - particular embodiment.
Although the signal generating circuit 21, for generating the write-in signal WEN, is provided only on each of the input cards 11 in the foregoing embodiment, it is to be noted that the discrimination of the output card 12 may otherwise be acheived by providing only on the output card 12 a circuit for generating a write-in inhibition signal. It is further to be noted that the input and output cards 11, 12 may be provided, respectively, with the circuit for generating the write-in signal and the circuit for generating the write-in inhibition signal, and that the writing-in operation may be controlled in accordance with an interlocked output between both the signals.
As mentioned previously, the input or output card is provided with the signal generating circuit for indicating which one of an input card and an output card is selected, the input and output cards are designated in a predetermined order and without discrimination, and the state memory is not enabled to execute rewriting when any output card is selected.
Accordingly, the ON and OFF information at a memory area, assigned to the selected output card, can be prevented from being rewritten in accordance with null information. Further, the replacement of the input and output cards, by connecting the same to desired connectors, and the alteration of input/output card ratio can be freely performed.
WHAT WE CLAIM IS: 1. A sequence controller comprising: a plurality of input power converter cards each connectable to at least one input element to convert closed and open states of that input element or those input elements into, respectively, ON and OFF signals; a plurality of output power converter cards each connectable to at least one output element to energize or deenergize that output element or those output elements in response to ON or OFF information supplied thereto; a plurality of connectors respectively connectable to said input and output power converter cards; A rewritable state memory having memory areas respectively assigned to said connectors to memorize the ON and OFF signals of the
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

  1. **WARNING** start of CLMS field may overlap end of DESC **.
    7 card 11, then the NAND gates NG0NG7 are all opened, whereby the ON and OFF signals of the input elements are output to the input/output bus IOB.
    Furthermore, the input card 11 is provided with the signal generating circuit
    21 comprising an inverter INV3, which feeds back the write-in signal WEN on the arrival of the selection signal CS. Thus, the operation control device 16 finds that connected to the selected connector 10a is an input card 11 and causes the state memory 19 to memorize the eight-bit ON and OFF signals, having appeared on the input/output bus IOB, at one of the memory areas thereof assigned to the selected connector.
    Figure 3 illustrates one example of the output cards 12. The ON and OFF information, output from the input/output bus IOB, are connected to input terminals of a latch circuit 31 via a connector, for example, 10b connected to the output card 12. This latch circuit 31 reads and memorizes the ON and OFF information, delivered to its input terminals, when receiving a signal at its trigger terminal and continues the output of the memorized ON and OFF information until new ON and OFF information are thereafter delivered thereto.The ON and OFF information from the latch circuit 31 is further delivered to power switches PC07PC7. These power switches PCO--PC7 energize or deenergize the assbciated output elements comprising the relays CR1 and CR20, solenoids SOLIl and SOL12 and the like, connected to output terminals O007, in accordance with the ON and OFF information, respectively.
    Further, the selection signal CS and the write-in command WRITE, output from the card selector 15 and the operation control device 16, are forwarded via the connector 10b to both input terminals of an AND gate AGI, respectively. The AND gate AGI in turn forwards its output signal to the trigger terminal of the latch circuit 31. Consequently, when the output card 12, connected to the connector 10b, is selected by the card selector 15 and when the write in command WRITE is delivered from the operation control circuit 16, the ON and OFF information, having been output to the input/output bus IOB, is then read by the latch circuit 31, whereby the output elements are energized or deenergized.
    Unlike the input card 11, the output card
    12 is not provided with the signal generating circuit 21 and does not feed back the writein signal WEN even upon receiving the card selection signal CS. In this connection, when the connector 10b connected to the output card 12 is selected in the step of reading the ON and OFF signals of the input and output elements, rewriting is not carried out with the contents of the memory area of the state memory 19 which is assigned to the selected connector 10b. It can therefore be avoided that the ON and OFF information, being memorized at that memory area, would be re-written in accordance with null information which comprises all " I " in this - particular embodiment.
    Although the signal generating circuit 21, for generating the write-in signal WEN, is provided only on each of the input cards 11 in the foregoing embodiment, it is to be noted that the discrimination of the output card 12 may otherwise be acheived by providing only on the output card 12 a circuit for generating a write-in inhibition signal. It is further to be noted that the input and output cards 11, 12 may be provided, respectively, with the circuit for generating the write-in signal and the circuit for generating the write-in inhibition signal, and that the writing-in operation may be controlled in accordance with an interlocked output between both the signals.
    As mentioned previously, the input or output card is provided with the signal generating circuit for indicating which one of an input card and an output card is selected, the input and output cards are designated in a predetermined order and without discrimination, and the state memory is not enabled to execute rewriting when any output card is selected.
    Accordingly, the ON and OFF information at a memory area, assigned to the selected output card, can be prevented from being rewritten in accordance with null information. Further, the replacement of the input and output cards, by connecting the same to desired connectors, and the alteration of input/output card ratio can be freely performed.
    WHAT WE CLAIM IS: 1. A sequence controller comprising: a plurality of input power converter cards each connectable to at least one input element to convert closed and open states of that input element or those input elements into, respectively, ON and OFF signals; a plurality of output power converter cards each connectable to at least one output element to energize or deenergize that output element or those output elements in response to ON or OFF information supplied thereto; a plurality of connectors respectively connectable to said input and output power converter cards; A rewritable state memory having memory areas respectively assigned to said connectors to memorize the ON and OFF signals of the
    input elements and the ON and OFF information for the output elements, respectively, in those memory areas corresponding to said input and output power converter cards; a program memory for memorizing a sequence program; a card selector for successively designating said connectors in a predetermined order; discrimination means for distinguishing said input power converter cards from said output cards so as to output discrimination information; and an operation control device including: first means for controlling said card selector and said state memory so as to successively memorize in said state memory the ON and OFF signals of only those input elements discriminated by the discrimination information supplied from said discrimination means; second means for controlling said program memory and said state memory so as to read out said sequence program from said program memory, to examine the states of the input elements in accordance with said sequence program and by reference to the contents of said state memory, and to rewrite said ON and OFF information for the output elements, being memorized in the state memory, in accordance with the results of the examinations; and third means for controlling said card selector and said state memory so as to successively output the rewritten ON and OFF information from said state memory to said output power converter cards and to thereby energize and deenergize respectively the output elements
  2. 2. A sequence controller as claimed in Claim 1, wherein said discrimination means comprises a signal generator responsive to a selection signal supplied from said card selector to generate the discrimination information to said first means whenever any one of said connectors connected to said input or power converter cards is selected by said card selector.
  3. 3. A sequence controller as claimed in Claim 2, wherein said signal generator is provided on each of said input power converter cards to feed back a write-in signal as the discrimination information to said first means in response to such selection signal.
  4. 4. A sequence controller as claimed in Claim 1, 2 or 3, wherein said first to third means are repeatedly operable in that order.
  5. 5. A sequence controller as claimed in any one of the preceding claims, wherein each of said connectors is connectable to any one of said input and output power converter cards.
  6. 6. A sequence controller as claimed in any one of the preceding claims, wherein each of said memory areas of said state memory has a plurality of memory bits capable of respectively memorizing the ON and OFF signals and the ON and OFF information, and wherein each of said input power converter cards and each of said output power converter cards are respectively connectable to input elements and output elements of the same number as said memory bits.
  7. 7. A sequence controller as claimed in any one of the preceding claims, wherein said operation control device comprises a microprocessor.
  8. 8. A sequence controller as claimed in Claim 2 or 3, or any one of Claims 4 to 7 when dependent on Claim 2 or 3, wherein said signal generator comprises an invertor for receiving said selection signal through andther invertor. So as to output the selection signal as the discrimination information.
  9. 9. A sequence controller, substantially as herein described with reference to the accompanying drawings.
GB4815677A 1976-12-08 1977-11-18 Sequence controller with a state memory for input and output elements Expired GB1580808A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14755976A JPS5948402B2 (en) 1976-12-08 1976-12-08 sequence controller

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GB1580808A true GB1580808A (en) 1980-12-03

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FR (1) FR2393358A1 (en)
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2842372A1 (en) * 1978-09-28 1980-04-10 Siemens Ag PROGRAMMABLE CONTROL
US4387442A (en) * 1980-10-01 1983-06-07 International Business Machines Corporation Controlled machine inhibition when control module is absent
DE3678369D1 (en) * 1985-09-27 1991-05-02 Allen Bradley Co STORAGE PROGRAMMABLE CONTROL WITH A SELF-TESTING INPUT / OUTPUT STRUCTURE.

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Publication number Priority date Publication date Assignee Title
JPS4993002U (en) * 1972-11-30 1974-08-12
US3974487A (en) * 1973-07-05 1976-08-10 Kokusai Denshin Denwa Kabushiki Kaisha Magnetic bubble transmission system
US3942158A (en) * 1974-05-24 1976-03-02 Allen-Bradley Company Programmable logic controller
JPS5062106U (en) * 1974-08-22 1975-06-06

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FR2393358A1 (en) 1978-12-29
JPS5948402B2 (en) 1984-11-26
JPS5371773A (en) 1978-06-26
FR2393358B1 (en) 1981-06-26

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