GB1580490A - Semiconductor switching device - Google Patents

Description

(54) SEMICONDUCTOR SWITCHING DEVICE (71) We, MITSUBISHI DENKI KABUSHIKI KAISHA, a Japanese Company, of 2-3, Marunouchi 2-chome, Chiyodaku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to improvements in a thyristor-type semiconductor switching device with gate reverse bias and more particularly to improvement in the turn-off characteristic of PNPN four layer semiconductor switching devices.

Among conventional PNPN four layer semiconductor switching devices there are well known gate turn-off thyristors and gate assisted turn-off thyristors utilising both the reverse biasing of the gate electrode and that of the anode electrode. In such switching devices it has been difficult to decrease the lateral or sheet resistance of the base region to which the control or gate electrode is attached, and therefore to improve the turn-off capability of the devices.

According to one aspect of the present invention there is provided a thyristor-type semiconductor switching device with gate reverse bias comprising a semiconductor substrate including a pair of opposed main faces, a first semiconductor layer of one conductivity type exposed to a first one of said main faces of said semiconductor substrate, a second semiconductor layer of the opposite conductivity type forming a first PN junction with said first semiconductor layer, a third semiconductor layer of the one conductivity type forming a second PN junction with said second semiconductor layer, and a fourth semiconductor layer of the opposite conductivity type exposed to a second one of said main faces of said semiconductor substrate and forming a third PN junction with said third semiconductor layer, a first main electrode disposed in ohmic contact with said first semiconductor layer, and a second main electrode disposed in ohmic contact with said fourth semiconductor layer, said second semiconductor layer including a third surface exposed to said first main face of said semiconductor substrate, and a control electrode disposed in ohmic contact with said second semiconductor layer, wherein said second semiconductor layer is thicker than said third semiconductor layer, and wherein there is provided gate reverse bias means connected between said control electrode and said first main electrode to apply a reverse voltage across said first PNjunction by way of said control electrode, said second semiconductor layer, said first semiconductor layer and said first main electrode.

Preferably, the second semiconductor layer may be formed of a low resistivity semiconductor layer and a high resistivity semiconductor layer, the low resistivity semiconductor layer including a surface exposed to the one main face of the semiconductor substrate and connected to the control electrode and the low resistivity semiconductor layer is interposed between the first semiconductor layer and the high resistivity semiconductor layer to form a low resistance layer.

In order to increase the reverse breakdown voltage of the first PN junction, a semiconductor layer higher in resistivity than the exposed portion of the first semiconductor layer may be disposed adjacent the first PN junction at the interface between the first semiconductor layer and the second semiconductor layer.

The present invention will become more readily apparent from the following description taken in conjunction with the accompanying drawings in which: Figure 1 is a schematic cross sectional view of a prior art PNPN four layer semiconductor switching device; Figure 2A is a schematic cross sectional view of a PNPN four layer semiconductor switching device of the present invention; Figure 2B is a view similar to Figure 2A but illustrating a modification of the arrangement shown in Figure 2A; Figure 3A is a schematic cross sectional view of a further embodiment of the invention; Figure 3B is a view similar to Figure 3A but illustrating a modification of the arrangement shown in Figure 3A; Figure 4A is a schematic cross sectional view of another embodiment of the invention; Figure 4B is a schematic plan view of the arrangement shown in Figure 4A with some parts omitted; Figure 5A is a schematic cross sectional view in still another embodiment of the invention; Figure 5B is a view similar to Figure 5A but illustrating a modification of the arrangement shown in Figure 5A; and Figure 6 is a graph illustrating the current-to-voltage curve depicted in the ON and OFF states of the semiconductor switching device of the present invention and also upon switching its ON to its OFF state thereof.

Throughout the Figures except for Figure 6 like reference numerals designate the identical or corresponding components.

Referring now to Figure 1 of the drawings, there is illustrated a notional structure of one type of well known PNPN four layer semiconductor switching devices such as gate turn-off thyristors and gate assisted turn-off thyristors utilizing both the reverse biasing of the gate electrode and that of the anode electrode. The arrangement illustrated comprises a semiconductor substrate 10 including a first transistor composed of a first P type semiconductor layer 12, a second N type semiconductor layer 14 and a third P type semiconductor layer 16 and a second transistor composed of the second N type semiconductor layer 14, the third P type semiconductor layer 16, and a fourth N type semiconductor layer 18 consisting of an annular N type semiconductor layer portion and a central N type semiconductor layer portion disposed in the third semiconductor layer 16.

In the first transistor the P type semiconductor layer 12 serving as an emitter region is exposed to one of the opposite main faces in this case, the upper main face of the substrate 10 and forms a first PN junction J1 with the second N type semiconductor layer 14. Then the second N type semiconductor layer 14 forms as second PN junction J2 with the third P type semiconductor layer 16 thinner than the layer 14.

The second transistor includes the second PN junction J2 and three discrete third PN junctions J3 formed between the third P type semiconductor layer 16 and the central and annular N type semiconductor layer portions forming the fourth layer 18 exposed to the other or lower main face of the substrate 10. Also the third layer 16 is partly exposed to the lower main face of the substrate 10. In the second transistor the P type semiconductor layer 16 serves as a base region while the N type layer 18 serves as emitter region.

In all the Figures except for Figure 6, the conductivity of the emitter or base region is designated by the reference character identifying the conductivity of the semiconductor material forming that region and suffixed with the reference character "e" or "b". For example, Pb designates the conductivity of the third semiconductor layer 16 serving as the base region.

A first main electrode, in this case, an anode electrode 20 is disposed in ohmic contact with the exposed surface of the first semiconductor layer 12 and connected to a first main terminal X while a second main electrode or a cathode electrode 22 is formed of a central and an annular electrode portions disposed in ohmic contact with the central and annular semiconductor layer portions forming the fourth layer 18 and connected together to a second main terminal Y. Then a gate electrode 24 includes an annular gate electrode portion disposed in ohmic contact with the peripheral portion of the exposed surface of the third semiconductor layer 16 and another annular gate portion disposed in ohmic contact with that portion of the exposed surface of the third layer 16 located between the fourth annular and central layer portions 18. The gate electrode portions 24 are concentric with each other and connected together to a gate terminal G.

A gate source of direct current 26 is connected across the second main terminal Y and the gate terminal G through a switch 28 to bias the gate electrode 24 so as to be negative with respect to the cathode electrode 22. Another DC gate source 26' is similarly connected across those terminals to bias the gate electrode 24 so as to be positive with respect to the cathode electrode 22.

The first transistor has a rate of carrier injection or a current amplification factor less than that of the second transistor.

Conventional PNPN four layer devices such as shown in Figure 1 have had the following disadvantages: Upon turn-off, a reverse voltage from the source 26 is applied to the gate electrode 24 to draw carriers out from the third semiconductor layer 16 interposed between the second and fourth semiconductor layers 14 and 18 respectively through the gate electrode 24.

This third layer is called hereinafter a "control gate layer". As the turn-off process proceeds, current paths due to the carriers injected from the first semiconductor layer 12 are concentrated in a position furthest remove away from the gate electrode 24, that is to say, the central portion of the fourth semiconductor layer 18 as shown at the arrow I in Figure 1.

On the other hand, the third layer 16 or the control gate layer through which the current paths extend has a sheet resistance rg (see Figure 1) to which the gate electrode is attached and is small in thickness because the current amplification degree is imparted mainly by the second transistor 1" 16--18 as above described. Therefore the sheet resistancebecame high and a voltage drop across the high resistance r has made it difficult to reversely bias that third junction J3 located on the central portion of the fourth semiconductor layer 18 most remote from the gate electrode 24.

If the third semiconductor layer 16 is formed of a low resistivity semiconductive material to decrease the resistance rug then the reverse voltage with stood by the third junction J3 is decreased until that portion of the third junction J3 near to the gate electrode 24 will be first broken down in the reverse direction.

In the arrangement of Figure 1 the only measure for decreasing the resistance rg has been to provide a small lateral dimension of the central portion of the fourth semiconductor layer 18, which, in turn, decreases the area occupied by the fourth semiconductor layer 18. This area forms the effective area for the current flowing through the fourth semiconductor layer 18. Also it has been required to provide a complicated fine pattern in which the third and fourth semiconductor layers are exposed to the other main face of the substrate 10. This has been attended with high rate of the occurrence of defects in the substrate and therefore such a pattern has been difficult to produce in view of the manufacturing steps involved. With the pattern easily formed, it has been difficult to decrease the resistance rg to a sufficiently low magnitude. Eventually there has been no measure but to decrease significantly the mean density of the current flowing through the associated semiconductor substrate.

Referring now to Figure 2A, there is illustrated a PNPN four layer semiconductor switching device constructed in accordance with the principles of the present invention. The arrangement illustrated comprises a semiconductor substrate 10 including a pair of first and second main faces, a first P type semiconductor layer 12 consisting of an annular and a central portion exposed to the peripheral edge and central portions of the first main face, in this case, the upper main face of the substrate 10 and a second N+ type semiconductor layer 14a exposed to the remaining portion of the first main substrate face and overlain by the first P type layer 12 to form three discrete first PN junction J, therebetween. The N+ type semiconductor layer 14a is continuous to an i type semiconductor layer 14b to form an N type semiconductor layer 14 corresponding to the N type semiconductor layer 14 as shown in Figure 1. The i type semiconductor layer 14b is disposed on a third P type semiconductor layer 16 to form a second PN junction J2 between the N and P type semiconductor layers 14 and 16 respectively.

The other main face of the substrate 10 is formed of a fourth N type semiconductor layer 18 disposed on the third P type semiconductor layer 16 to form a third PN junction J3 therebetween.

As in the arrangement of Figure 1, the first, second and third semiconductor layers form a first transistor while the second, third and fourth semiconductor layers form a second transistor.

An annular and a central electrode 20 are disposed in ohmic contact with the annular and central portions of the first N type semiconductor layer 12 and connected together to a first main terminal X. Those electrodes form a first main electrode 20, in this case, an anode electrode. A second main electrode 22 or a cathode electrode is disposed in ohmic contact with the fourth semiconductor layer 18 and connected to a second main terminal Y. An annular control electrode 24 called the gate electrode in the arrangement of Figure 1 is disposed in ohmic contact with the exposed portion of the N+ type semiconductor layer 14a to be located between the central and annular anode electrode 20. Unlike the arrangement of Figure 1, the third semiconductor layer 16 is not exposed to the other main face of the substrate 10.

A control source of direct current 26 is shown in Figure 2A as including a negative side connected to the first main terminal X and a positive side connected to a control terminal C to which the control electrode 24 is connected.

The arrangement of Figure 2A is turned on by having a voltage applied across the anode and control electrodes 20 and 24 respectively with a polarity reversed from that of control voltage shown by CA in.

Figure 2A.

From the foregoing it is seen that in the present embodiment the second semiconductor layer 14, which is thicker than the remaining layers, is exposed to the first main face of the substrate 10 and the control electrode 24 is disposed in ohmic contact with the exposed surface of the second semiconductor layer 14. In the forward blocking state, a reverse voltage is applied across the second junction J2 to spread the depletion layer adjacent to that junction toward the second semiconductor layer 14. Thus the second semiconductor layer 14 has an increased thickness sufficient to spread the depletion layer as required.

In the arrangement of Figure 2A, the control is accomplished by the first transistor 12-14-16 having a low current amplification factor resulting in an increase in control current -I, from the control source 26 for reversely biasing the second junction J2. However, since the second semiconductor layer 14 has a thickness very large as compared with the remaining semiconductor layers, a current having flowed through the anode electrode 20 and the first semiconductor layer 12 is actually commutated directly to the second semiconductor layer 14 is low in sheet electrode 24. This means that the second semicondutor layer 14 is low in sheet resistance rc (see Figure 2A).

In order to decrease further this sheet resistance, that side of the second semiconductor layer 14 near to the second junction J2 has been formed of a lightly doped semiconductor layer 14b having a high resistivity and therefore a low impurity concentration. The layer 14b may be of an i or a y type semiconductive material.

In addition, that portion of the second semiconductor layer 14 near to the first junction J, has been formed of a semi conductive material highly doped with an impurity, an N type impurity in the example illustrated, to have a low resistivity. Therefore this low resistivity layer is of N+ type and its thickness x, (see Figure 2A) can be greater than the thickness x, of the third semiconductor layer 16 forming the base region of the second transistor.

This is because the second semiconductor layer 14 forms the base region of that transistor having a low current amplification factor. Therefore the layer 14 can easily have an increased thickness. For example, the third semiconductor layer has a thickness x3 ranging from several microns to scores of microns while the thickness x2 of the second semiconductor layer 14 may range from scores to hundreds of microns.

Also the low resistivity layer 14a may have its thickness x5 equal to from one sixth to two thirds the thickness x2.

In this way the sheet resistance rc of the second semiconductor layer 14 and more particularly of the low resistivity layer 14a can be extremely low. As a result, the control voltage VCA required for the principal current I to be commutated, as a current -I, through the control electrode 24, is decreased in the absolute magnitude.

In this case, the absolute magnitude of the control current --I, is not greater higher than that of the principal current I and may be greater than the latter at the beginning of the turn-off process. Alternatively, with the conditions for the control voltage remaining unchanged, the central portion of the first semiconductor layer 12 exposed to the first main face of the substrate 10 may rather have its diameter RA (see Figure 2A) increased. This results in a decrease in fineness of the particular pattern to facilitate manufacture.

Figure 2B shows a modification of the arrangement illustrated in Figure 2A. The arrangement illustrated differs from that shown in Figure 2A only in that in Figure 2B the components have the conductivity reversed from that illustrated in Figure 2A with the sources poled accordingly. For example, Figure 2A shows the second semiconductor layer with an N+ type conductivity operatively connected to the control electrode while Figure 2B shows that having a P+ type conductivity. In Figure 2B, the layer 14b may be of an i or 7t type semiconductive material.

This arrangement illustrated in Figure 3A differs from that shown in Figure 2A only in that in Figure 3A, a thin semiconductor layer is disposed adjacent the interface between the first and second semiconductor layers 12 and 14a or the junction J, within the second semiconductor layer 14a exposed to the first main face of the substrate 10. This thin semiconductor layer 30 is higher in resistivity than the exposed portion of the first semiconductor layer 12 and may be of either an N- or a P- type. An N- or a Ptype layer is higher in resistivity, or less in impurity concentration than an N or a P type layer. If the semiconductor layer 30 is of the N- type then the discrete first junctions Jl are formed in solid line Jl. On the other hand, the use of the P- type layer 30 results in the formation of the first junctions in dotted line adjacent to the solid line Jt.

In Figure 3B, the components have the conductivity reversed from that illustrated in Figure 3A with the sources (not shown) poled accordingly. In other respects, the arrangement is identical to that shown in Figure 3A.

In Figure 3B, therefore, the thin semiconductor layer 30 with a P- type conductivity forms the discrete first junctions in solid line J, with the first semiconductor layer 12 while the layer 30 having an N- type conductivity and semiconductor layer 12 form the first junctions in dotted line adjacent to the solid line J.

In the arrangements as shown in Figures 3A and 3B, the reverse breakdown voltage for the first PN junction J, is increased thereby to permit a higher control voltage VCA to be applied thereacross. This cooperated with a decrease in sheet resistance rc as above described to permit a higher current to be turned off.

In another embodiment of the present invention shown in Figures 4A and 4B, the semiconductor substrate 10 includes a bevelled peripheral wall and the first semiconductor layer 12 in the form of a plurality of radial strips disposed at substantially equal angular intervals. As best shown in Figure 4B wherein the anode and gate electrodes 20 and 24 respectively omitted only for purposes of illustration, the radial strips forming the first semiconductor layer 12 radially extend between a pair of concentric circles as shown at dotted line in Figure 4B also concentric with the circular substrate 10 and each strip includes circumferentially extended short branches.

Further the substrate 10 is fixedly secured to a circular base plate 32 of any suitable electrically conductive material such as copper, molybdenum, tungsten or the like as by brazing the cathode electrode 22 to the base plate 32.

Therefore, in the present embodiment, the pattern in which the first and second semiconductor layers 12 and 14 respectively are disposed on one of the main faces of the substrate 10 can be made similar to the pattern in which the base and emitter regions are disposed in conventional transistors and also to the patterns of the gate and cathode regions used in conventional gate turn-off and gate assisted turn-off thyristors. With the fineness of the pattern remaining unchanged, the current which can be turned off becomes high. Alternatively, with a current to be turned off remaining unchanged, the fineness of the particular pattern is decreased to facilitate the manufacture.

Figure 5A shows still another embodiment of the present invention applied to a reverse conducting device and Figure 5B shows a modification thereof similar to that illustrated in Figure 5A except for the conductivity of the components. That is, the arrangement of Figure 5A includes an N+ type control gate layer 14 and that of Figure 5B includes a P+ type control gate layer 14.

As shown in Figure 5A, the first P type semiconductor layer 12 is in the form of two concentric annuli disposed on the one main face of the substrate 10 and a pair of first main electrodes 20, in this case, anode electrodes are disposed in ohmic contact with the two annuli of the first P+ type semiconductor layer 12. It is to be noted that the outer annulus of the electrode 20 is also disposed in ohmic contact with the exposed surface portion of the second N type semiconductor layer 14.

Further the other main face of the substrate 10 includes the central portion to which the fourth N type semiconductor layer 18 is entirely exposed and the peripheral portion to which the peripheral portion of the third P type semiconductor layer 16 is exposed. Then a single second main electrode 22, in this case, a cathode electrode is disposed in ohmic contact with the other main substrate face throughout the entire area and then suitably fixed to a base plate 32 of an electrically conductive material such as above described.

In Figure 5A, the fourth semiconductor layer 18 is shown having a radius less S than the outside radius of the outer annulus of the first semiconductor layer 12. Also it is seen that those portions of both electrodes 20 and 22 contacted by the second and third semiconductor layers 14 and 16 respectively form a semiconductor diode with those portions of the layers 12 and 14 located therebetween. The diode includes the peripheral portion of the second junction J2 Therefore the arrangement of Figure 5A comprises a PNPN switching device surrounded by a semiconductor diode.

Since the anode-cathode path of the switching device cannot, because of the surrounding diode, have a reverse voltage applied thereto, the high resistivity semiconductor layer 14a may have a reduced thickness. Thus the low resistivity layer 14b can easily increase in thickness.

This results in the facilitation of a further decrease in sheet resistance rc of the layer 14a.

In PNPN switching devices having the reverse blocking voltage less than the forward blocking voltage, the peripheral surface of the semiconductor substrate may be subjected to the positive bevelling thereby to increase the rate at which the area of the semiconductor wafer can be utilized. In the positive bevelling a tilted angle to either one or the other of main faces of the substrate approaches 50 degrees and normally is of the order of 60 degrees as shown in Figures 4 and 5.

In the arrangements as shown in Figures 2 to 5, the control electrode 24 is disposed on the one main face of the semiconductor substrate 10 to which the first semiconductor layer 12 is exposed so that the second main electrode 22 on the side of the fourth semiconductor layer 18 becomes flat. Then the base plate 32 as above described can be fixedly secured to that flat surface of the second main electrode. In this case, the positive bevelling permits the cross sectional profile of the substrate to have an acute angle located on the base plate. In other words, the substrate includes the other main face broader in area than the one main face. This cooperates with a positively bevelled angle approaching 90 degrees to make it difficult to break or damage the semiconductor substrate.

By contrast, conventional devices such as shown in Figure 1, have included the one main face to which a base plate is attached and also the first semiconductor layer is exposed. Under these circumstances, the positive bevelling causes a decrease in area of the one main substrate face. Therefore the semiconductor substrate or wafer has a cross sectional profile including an acute angle located on that side thereof remote from the base plate. This results in the easy break or damage of the semiconductor wafer. This is avoided through the negative bevelling but the resulting cross sectional profile will include an angle of several degrees. Thus the semiconductor wafer has a decreased rate of utilization of its area.

From the foregoing it will be appreciated that the present invention is effective in view of the utilization of semiconductor wafers.

The embodiment of Figure 2 has the structural feature that the base layer to which the control gate 24 is attached that is to say, the base layer 14 of the first transistor 12--144-16 is thick as compared with the prior art practice. Therefore the first transistor has a low current amplification factor and a control current -I, for turning the device off approximates the principal current I to be turned off.

That is, a turn off current gain has a value approximating one.

The structural feature as above described is of great advantage to cause gate turn-off thyristors to withstand higher voltages.

This is because the characteristics of gate turn-off thyristors are most affected by the characteristics of the transistor including a control electrode.

More specifically, the collector-toemitter sustaining voltage V,,,,, in the process of turning transistors oft depends upon the current amplification factor hFF in the common emitter configuration within the operating region with low currents. It is well known that the relationship

where VCBO designates the collector-to-base breakdown voltage upon opening the emitter and n has a value ranging from two (2) to six (6).

In conventional power transistors, the current amplification factor hFF in the common emitter configuration has been of a value ranging from twenty (20) to thirty (30) within the operating range with low currents, in which the field effect developed in the base region thereof does not decrease the current amplification factor. Thus the substaining voltage VCEO(SUS) has been equal to from about one half to one quarter the breakdown voltage VCBO. In other words, the sustaining voltage VCEO(SUS) actually withstood by such power transistors has been equal to from about one half to about one quarter the voltage VCBO withstood by the semiconductor diode alone formed of the collector and base regions of such transistors. Accordingly the voltage to be controlled has been inevitably relatively low.

The relationship as above described is equally applicable to both conventional gate turn-off transistors such as shown in Figure 1 and transistors including, as the base region, the semiconductor layer 16 to which a gate electrode is attached as shown in Figure 1. Thus the dynamic withstanding voltage has been equal to about one half the breakdown voltage of the junction J2 alone for the following reasons: In conventional gate turn-off thyristors it has been of the most importance in view of the design to increase the current control gain provided by the gate electrode, and therefore transistors including, as the base region, the semiconductor layer 16 has been high in current a along the ordinate against the voltage across the first and second main electrode.

Also the arrow indicates the turn-off process through which the device is switched from its ON to its OFF state.

The hFE can readily be made equal to or less than two (2) because the base layer 14 of the first transistor 12-14-16 is made relatively thick. In addition, the rate of carrier injection from the first semiconductor layer 12 is reduced by decreasing the sheet resistance rc of that semiconductor layer 14a forming one part of the base layer 14. Therefore to decrease the hFE is further facilitated. Such a decrease in hFE causes a reduction in turnoff current gain. However, the semiconductor layer 14a directly contacted by the first semiconductor layer 12 has its sheet resistance made low to permit a decrease in reverse voltage VCA applied across the first and second semiconductor layers 12 and 14 respectively upon the turning off. Further the decrease in hFE causes an increase in turn-off speed. Therefore the electrical energy required for controlling the turnoff is not high as compared with the prior art practice.

As above described, a decrease in turnoff current gain causes an increase in turnoff control current Ic but a voltage V,,s capable of being turned off is decreased while a turn-off time is decreased. This means that the present invention rather increases the turn-off power gain in terms of the mean power.

As above described, the gate turn-off thyristors of the present invention can withstand higher voltages by decreasing the current amplification factor hFE of the transistor including, as the base layer, the second semiconductor layer 14 for the common emitter configuration. It will readily be understood that, in this respect, the present invention increases the ability to control switching devices for controlling high powers.

From the foregoing it is seen that the present invention can readily improve the turn-off characteristics by attaching the control electrode 24 to the second semiconductor layer 14 thicker than the third semiconductor layer 16. The turn-off characteristics can be further improved by directly contacting the first semiconductor layer 12 with the low resistivity layer 14a forming one part of the second semiconductor layer 14. Further, the arrangement as shown in Figure 5A or 5B has the more improved turn-off characteristics because a semiconductor diode including one portion of the second junction J2 is operated to suppress a reverse blocking voltage or to reversely conduct the arrangement thereby to increase the permissible thickness of the second semiconductor layer and hence the low resistivity layer.

In addition, the arrangement as shown in Figure 3A or 3B can increase the ability to turn it off. This is because a thin semiconductor layer 30 higher in resistivity than the first semiconductor layer 12 is disposed adjacent to the first PN junction J; therby to increase a reverse blocking voltage for the first PNjunction J, to permit a turn-off control voltage VCA.

Also by causing the current amplification factor hFE of the common emitter transistor including, as the base region, the second semiconductor layer 14 to be equal to or less than two (2), a higher voltage can be controlled as above described.

WHAT WE CLAIM IS: 1. A thyristor-type semiconductor switching device with gate reverse bias comprising a semiconductor substrate including a pair of opposed main faces, a first semiconductor layer of one conductivity type exposed to a first one of said main faces of said semiconductor substrate, a second semiconductor layer of the opposite conductivity type forming a first PN junction with said first semiconductor layer, a third semiconductor layer of the one conductivity type forming a second PN junction with said second semiconductor layer, and a fourth semiconductor layer of the opposite conductivity type exposed to a second one of said main faces of said semiconductor substrate and forming a third PN junction with said third semiconductor layer, a first main electrode disposed in ohmic contact with said first semiconductor layer, and a second main electrode disposed in ohmic contact with said fourth semiconductor layer, said second semiconductor layer including a third surface exposed to said first main face of said semiconductor substrate, and a control electrode disposed in ohmic contact with said second semiconductor layer, wherein said second semiconductor layer is thicker than said third semiconductor layer, and wherein there is provided gate reverse bias means connected between said control electrode and said first main electrode to apply a reverse voltage across said first PN junction by way of said control electrode, said second semiconductor layer, said first semiconductor layer and said first main electrode.

2. A semiconductor switching device as claimed in Claim 1 wherein said second semiconductor layer is formed of a low resistivity semiconductor layer and a high resistivity semiconductor layer, said low

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. along the ordinate against the voltage across the first and second main electrode. Also the arrow indicates the turn-off process through which the device is switched from its ON to its OFF state. The hFE can readily be made equal to or less than two (2) because the base layer 14 of the first transistor 12-14-16 is made relatively thick. In addition, the rate of carrier injection from the first semiconductor layer 12 is reduced by decreasing the sheet resistance rc of that semiconductor layer 14a forming one part of the base layer 14. Therefore to decrease the hFE is further facilitated. Such a decrease in hFE causes a reduction in turnoff current gain. However, the semiconductor layer 14a directly contacted by the first semiconductor layer 12 has its sheet resistance made low to permit a decrease in reverse voltage VCA applied across the first and second semiconductor layers 12 and 14 respectively upon the turning off. Further the decrease in hFE causes an increase in turn-off speed. Therefore the electrical energy required for controlling the turnoff is not high as compared with the prior art practice. As above described, a decrease in turnoff current gain causes an increase in turnoff control current Ic but a voltage V,,s capable of being turned off is decreased while a turn-off time is decreased. This means that the present invention rather increases the turn-off power gain in terms of the mean power. As above described, the gate turn-off thyristors of the present invention can withstand higher voltages by decreasing the current amplification factor hFE of the transistor including, as the base layer, the second semiconductor layer 14 for the common emitter configuration. It will readily be understood that, in this respect, the present invention increases the ability to control switching devices for controlling high powers. From the foregoing it is seen that the present invention can readily improve the turn-off characteristics by attaching the control electrode 24 to the second semiconductor layer 14 thicker than the third semiconductor layer 16. The turn-off characteristics can be further improved by directly contacting the first semiconductor layer 12 with the low resistivity layer 14a forming one part of the second semiconductor layer 14. Further, the arrangement as shown in Figure 5A or 5B has the more improved turn-off characteristics because a semiconductor diode including one portion of the second junction J2 is operated to suppress a reverse blocking voltage or to reversely conduct the arrangement thereby to increase the permissible thickness of the second semiconductor layer and hence the low resistivity layer. In addition, the arrangement as shown in Figure 3A or 3B can increase the ability to turn it off. This is because a thin semiconductor layer 30 higher in resistivity than the first semiconductor layer 12 is disposed adjacent to the first PN junction J; therby to increase a reverse blocking voltage for the first PNjunction J, to permit a turn-off control voltage VCA. Also by causing the current amplification factor hFE of the common emitter transistor including, as the base region, the second semiconductor layer 14 to be equal to or less than two (2), a higher voltage can be controlled as above described. WHAT WE CLAIM IS:

1. A thyristor-type semiconductor switching device with gate reverse bias comprising a semiconductor substrate including a pair of opposed main faces, a first semiconductor layer of one conductivity type exposed to a first one of said main faces of said semiconductor substrate, a second semiconductor layer of the opposite conductivity type forming a first PN junction with said first semiconductor layer, a third semiconductor layer of the one conductivity type forming a second PN junction with said second semiconductor layer, and a fourth semiconductor layer of the opposite conductivity type exposed to a second one of said main faces of said semiconductor substrate and forming a third PN junction with said third semiconductor layer, a first main electrode disposed in ohmic contact with said first semiconductor layer, and a second main electrode disposed in ohmic contact with said fourth semiconductor layer, said second semiconductor layer including a third surface exposed to said first main face of said semiconductor substrate, and a control electrode disposed in ohmic contact with said second semiconductor layer, wherein said second semiconductor layer is thicker than said third semiconductor layer, and wherein there is provided gate reverse bias means connected between said control electrode and said first main electrode to apply a reverse voltage across said first PN junction by way of said control electrode, said second semiconductor layer, said first semiconductor layer and said first main electrode.

2. A semiconductor switching device as claimed in Claim 1 wherein said second semiconductor layer is formed of a low resistivity semiconductor layer and a high resistivity semiconductor layer, said low

resistivity semiconductor layer including a third surface exposed to said first main face of said semiconductor substrate and connected to said control electrode, and said low resistivity semiconductor layer is interposed between said first semiconductor layer and said high resistivity layer to form a low resistance layer region.

3. A semiconductor switching device as claimed in Claim 2 wherein said first main electrode is also disposed in ohmic contact with one portion of said second semiconductor layer exposed to said first main face and said third semiconductor layer includes one portion having a fourth surface exposed to the second face and connected to the second main electrode.

4. A semiconductor switching device as claimed in Claim 2 wherein a semiconductor layer higher in resistivity than said exposed portion of said first semiconductor layer is disposed adjacent said first PN junction at the interface between said first semiconductor layer and said second semiconductor layer.

5. A thyristor-type semiconductor switching device with gate reverse bias as claimed in Claim 1, constructed, arranged and adapted to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.