GB1579488A - System for extracting timing information from a modulated carrier - Google Patents

System for extracting timing information from a modulated carrier Download PDF

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Publication number
GB1579488A
GB1579488A GB19325/77A GB1932577A GB1579488A GB 1579488 A GB1579488 A GB 1579488A GB 19325/77 A GB19325/77 A GB 19325/77A GB 1932577 A GB1932577 A GB 1932577A GB 1579488 A GB1579488 A GB 1579488A
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signal
oscillator
carrier
derived
signals
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Schlumberger Technology Corp
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Schlumberger Technology Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • EFIXED CONSTRUCTIONS
    • E21EARTH OR ROCK DRILLING; MINING
    • E21BEARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00Survey of boreholes or wells
    • E21B47/12Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling
    • E21B47/14Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling using acoustic waves
    • E21B47/18Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling using acoustic waves through the well fluid, e.g. mud pressure pulse telemetry
    • E21B47/20Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling using acoustic waves through the well fluid, e.g. mud pressure pulse telemetry by modulation of mud waves, e.g. by continuous modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Mining & Mineral Resources (AREA)
  • Geology (AREA)
  • Geophysics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Fluid Mechanics (AREA)
  • Remote Sensing (AREA)
  • Acoustics & Sound (AREA)
  • General Life Sciences & Earth Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Environmental & Geological Engineering (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Indicating And Signalling Devices For Elevators (AREA)
  • Communication Control (AREA)

Description

(54) SYSTEM FOR EXTRACTING TIMING INFORMATION FROM A M(JDU LATED CARRIER (71) We, SCIILUMBERGER T,ECHNOLOGY CORPORATION, a corporation organised and existing under the laws of the State of Texas, 5000 Gulf Freeway, P.O. Box 1472, Houston, Texas 77001 U.S.A., do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is. to be performed, to be particularly described in and by the following statement: BACKGROUND OF THE INVENTION This invention relates to digital signalling systems and, more particularly, to the extraction of timing information from digital signalling systems.
When digital data is transmitted by electrical, acoustic, mechanical or other means, it is necessary at the receiving end to extract timing information from the received signal in order to identify the start time epoch of each transmitted digital symbol. Typically, at the transmitter end a carrier signal was modulated with digital symbols, the symbol rate being related to the carrier frequency, generally either as a multiple thereof or as a ratio of integers.
In systems where the received signal has become noisy, the problem of accurately obtaining timing information is particularly acute. For example, one type of system wherein a noisy transmission path is experienced is a so-called "logging-whiledrilling" system wherein well logging data is transmitted to the surface of a borehole via a drill pipe during the drilling operation. In such instance, it is difficult to transmit acquired data to the surface electrically unless the drill pipe is provided with a special insulated conductor including means for forming appropriate connections for the conductor at the drill pipe joints. Accordingly, there have been proposed various systems for transmitting the logging data acoustically, either through the drill pipe or in drilling liquid.Typically, the data is converted to digital form and then used to modulate a carrier signal, such as by "phasewshift keying" ("PSK"), "frequency shift keying" ("FSK"), or "amplitude-shift keying" ("ASK"). At the surface, the acoustic signal is detected and demodulated in order to provide the desired readout information (see e.g. U.S. Patent No.
3,886,495). In this type of system, or any other wherein the transmission medium is less than ideal, the signal experiences substantial noise and this renders it difficult to extract symbol timing information. Some techniques for extracting symbol timing were described in an article entitled "Re cent Advances in Symbol Synchronization" by W. N. Waggener, which appeared in Volume 12, No. 1 of Instrument Society of America Transactions, at page 7.
When digital data is transmitted by modulating a carrier and the carrier fre quency is coherently related to the symbol rate, timing information from the carrier wave can be used to aid in extracting symbol timing information. By way of a numerical example, if the symbol rate were, say, 600 symbols per second, and the modulated carrier frequency was, say, 2400 hertz, there are four carrier cycles per symbol period. Simple division of the carrier frequency by a factor of 4 would yield a clock frequency equal to the symbol rate.
Although the divided frequency would be substantially correct, the division process produces an ambiguous phase which must be resolved.
Symbol timing information could also be extracted from the digital data independently of the carrier frequency, as is disclosed in the above-referenced publication.
Symbol timing information can only be obtained, however, when a symbol changes from one value to another value. Thus, extended periods without such a transition render it difficult to maintain symbol synchronization. Also, where unusually high noise levels are experienced during transmission, the problem of maintaining synchronization is intensified.
It is an object of the present invention to provide a system which minimizes errors during detection of timing information.
SUMMARY OF THE INVENTION In accordance with this and other objects, one aspect of the present invention is directed to a method for extracting timing information from a carrier signal modulated with digital symbols, the symbol rate being related to the carrier frequency, wherein a phase-locked loop generates an error signal and includes an oscillator responsive to said error signal, and comprising the steps of: generating a first signal in response to said carrier signal at substantially the symbol rate; generating a second signal responsive to symbol transitions; and combining said first signal, said second signal and a signal derived from said oscillator to generate said error signal.
Another aspect of the present invention is directed to an apparatus for extracting timing information from a carrier signal modulated with digital symbols, the symbol rate being related to the carrier frequency, comprising: a phase-locked loop including an oscillator and error signal generating means for controlling said oscillator; means responsive to said carrier for generating a first signal at substantially the symbol rate; means responsive to symbol transitions for generating a second signal; and said error signal generating means being responsive to said first signal, said second signal and a signal derived from said oscillator for generating an error signal to control said oscillator.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a system in accordance with an embodiment of the invention.
FIG. 2 is a schematic block diagram of a system in accordance with another embodiment of the invention.
FIG. 3 is a diagram, partially in block form, showing the present invention incorporated in a system for well logging.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, there is shown a schematic block diagram of a system in accordance with the invention for extracting timing information from a received input carrier signal modulated with digital symbols. The basic timing is provided by a phase-locked loop 20 which includes, inter alia, a voltage controlled oscillator 21, a loop filter 22, and an error signal generating means 23. In the present embodiment, the error signal generating means is a summing amplifier comprising an operational amplifier 24 arranged in conventional manner to serve as a summing amplifier; i.e.
with appropriate feedback resistance and a summing junction at its inverting input.
The inputs to the summing junction of summing amplifier 23, via weighting resistors R1 and R2, are the outputs of phase comparators 31 and 32 respectively.
Phase comparator 31 receives as one of its inputs a signal having a characteristic frequency fl which is derived from the oscillator 21 by a digital clock divider 40. The other input to comparator 31 is derived from the carrier of the received signal. A carrier clock is obtained from the carrier and is input to a counter 50 whose characteristic count cycle is set at the ratio between the carrier frequency and the symbol rate, this ratio assumed to be an integer N for ease of illustration. The output of the counter 50, which is accordingly at substantially the symbol rate, is coupled to the phase comparator 31 via AND gate 55.
One input to the phase comparator 32 is a signal at a reference frequency f2, which is also derived from oscillator 21 by clock divider 40 and will generally be the same as fl. The other input to phase comparator 32 is the output of a transition detector 60 whose output is a measure of the detected symbol transitions of the symbol-modulated carrier input signal. In particular, the input to the transition detector 60 is derived from the received input data by conventional filtering and limiting circuitry, so as to obtain a "clean" version of the received symbol data. The output of loop filter 22 which is indicative of the error level, is coupled to a threshold detector 70 whose output is a logical "0" if a prescribed threshold level is exceeded.Conversely, the threshold detector output is a logical "1" if the threshold level is not exceeded. The output of threshold detector 70 is the second input to the AND gate 55.
Operation of the system of FIG. 1 is as follows: The output of the transition detector is phase compared to the frequency f2 which is derived from the phase-locked loop oscillator 21. The resultant signal (referred to herein generally as the "second error component signal") is weighted by R2 and applied as an error signal which drives the phase-locked loop to the frequency and phase of the symbol transitions. The output of the transition detector 60 also resets the counter 50. As the system is initially activated, counter 50 can randomly contain any count. The initial reset signal from transition detector 60 thus synchronizes it with the symbol signals so that the carrier can suitably replace the symbol transitions should the latter stop for a time.Once the loop 20 is in phase-lock, the error signal in the loop, as measured at the output of the loop filter 22, will be small enough that the output of the threshold detector 70 will become a logical "1" which, in turn, enables the AND gate 55. Now, clock pulses from the counter 50 are fed to phase comparator 31 to be phase compared with the signal at frequency ft. The phase error indicated at the output of comparator 31 (referred to herein generally as the "first error component signal") is weighted by R1 and summed by summing amplifier 23 with the measured phase error based on symbol transitions. A feature of the invention is that if there are no symbol transitions for a period of time, the carrier clock counter 50 maintains loop synchronization.When symbol transitions occur, the phase error contribution based on symbol transitions is more heavily weighted than the phase error contribution based on the carrier clock by virtue of the different value resistors R1 and R2, so the loop tends to readjust the loop oscillator phase to match the actual symbol transition timing. The resistor R1 is variable to facilitate adjustment of the weighting ratio, when desired. If the loop loses lock, the increase in loop error signal will cause the error contribution due to the carrier clock 50 to be inhibited by virtue of AND gate 55 being disabled. This inhibiting action continues until the occurrence of symbol transitions which relock the phase-locked loop. The necessary system timing is obtained, for example, from clock divider 40.
The voltage controlled oscillator 21 is preferably set to run at a frequency which is a multiple of the symbol rate so that the digital clock divider 40 can provide multiple phases of the reference frequency. This permits the optimum clock phase to be selected for the two phase comparators and permits compensation for any known fixed phase shift between the carrier transitions and the symbol transitions (by using appropriate fl and f). Preferably, the carrier frequency should be a relatively large multiple of the symbol rate so as to minimize the phase offset due to the resolution of the counter 50. In cases when the carrier frequency is only a small multiple of the symbol rate, a coherent frequency multiplier may be employed to increase the carrier reference clock frequency.
A less complex version of the system of FIG. 1 is shown in FIG. 2. In this embodiment, the symbol transition detector 60 resets the counter 50 each time a symbol transition occurs. A single phase comparator 31 is employed and derives an error signal by comparison of the output of the clock divider 40 with the output of counter 50. When symbol transitions are absent, the counter "free runs" and maintains loop lock.
It is readily apparent from FIG. 4 that counter 50 provides an output pulse in response to the occurrence of a reset pulse and/or when it reaches its preset count.
Should a synchronous counter implementation be selected for counter 50, these two events should occur within the same carrier clock period so that both result in one counter output pulse. A disadvantage inherent in using a synchronous counter is due to the fact that the counter output is in phase with the carrier clock and not necessarily with the data signal. Thus, although this implementation is less complex than the system of FIG. 1, the resolution of counter 50 is a limiting factor on per formance.
The resolution error can be improved by using an asynchronous counter. It generates an output pulse in immediate response to a reset pulse when a symbol transition is detected. Consequently, the precise phase of the data signal is provided to phase comparator 31 to maintain the phase lock loop accurately locked onto the symbol transitions. However, it should be noted that if the carrier frequency is much higher than the data frequency, the phase difference between the carrier and the symbol transitions is so small that it may be acceptable even with the use of a synchronous counter.
The abovediscussed timing signal extraction system has been found useful in the field of well logging, and, more particularly, for the technique of "logging-whiledrilling" previously mentioned. An apparatus capable of performing this technique is depicted in FIG. 3 in connection with a typical rotary drilling apparatus 100.
Derrick 102 supports drill string 104 extending into the borehole 107 and suspended from hook 105 by swivel 106. Drill string 104 includes bit 108, one or more drill collars 110, and a length of drill pipe 112. Pipe 112 is coupled to a kelley 114 which extends through rotary drive mechanism 116 driven by one or more motors 118.
Positioned near the entrance of borehole 107 is a conventional drilling fluid, or mud, circulating system 115. The circulating system includes a pump 120 which circulates mud from pit 122 into mud line 124 and then downwardly through kelley 114, drill string 104 and out the orifices in bit 108. The mud then returns upwardly in the annulus 126 and exits casing 128 through opening 130 into mud return line 132 back to mud pit 122.
A logging-while-drilling system 134 is suitably positioned downhole in proximity to hit 108. Perhaps the most promising approach to date for transmitting signals uphole is a system which includes a signal generator 136 controllably driven for selectively interrupting the flow of the mud to thereby impart an acoustic signal to it.
The acoustic signal travels upward through the circulating mud in drill string 104 and is detected at the surface by transducer 138 attached to mud line 124. Cartridge 140 is provided for sensing the various downhole conditions and for driving signal generator 136 in accordance with the values of the sensed conditions. Power supply 142 serves to energize cartridge 140 and includes a turbine positioned within the flow of the circulating mud. The details of such a system are disclosed in U.S. Patent No. 3,309,656, for example.
The timing signal extraction circuit described above is positioned at the surface to receive at its input the filtered signal from transducer 138. A pump-noise filter 144 removes the mud disturbances caused by pump operation which would otherwise seriously distort the signal from generator 136, as disclosed in U.S. Patent No.
3,742,443. Processing circuit 146 receives the filtered signal and may include further means to improve the signal quality such as a bandpass filter and an automatic gain control. However, the primary function of processing circuit 146 is to recover a carrier clock as well as to demodulate the output of filter 144. These tasks are performed in a well known manner by available circuitry. The above-described timing reconstruction circuit 148 (see FIGS. 1 and 2) receives two inputs 149 and 150 from processing circuit 146 corresponding, respectively, to the carrier clock and the demodulated data signal. A suitable clock signal in phase with the data is produced by circuit 148 in accordance with the detailed discussion provided above and then input to data reconstruction circuit 150.
The reconstructed clock is utilized by circuit 152 to recover the information in the data signal on line 150 which is indicative of the measured downhole condition. If PSK modulation is used, circuit 152 may operate to produce a bit decision signal from the input 150 which is then passed through a differential decoder which indicates the occurrence of a transition. A decommutator may also be included which functions under the timing control of circuit 148 to determine the beginning of a data word. Circuitry of this sort is well known and no further details are therefore deemed necessary. (For a presentation of the processing and data reconstruction circuits see Viterbi, A. J., Principles of Coherent Communication, McGraw-Hill, 1966, pages 286-292).The data words and/or measurements derived from the decommutator output may be selectively displayed and/or recorded on a suitable device 154.
WHAT WE CLAIM IS:- 1. A method for extracting timing information from a carrier signal modulated with digital symbols, the symbol rate being related to the carrier frequency, wherein a phase-locked loop generates an error signal and includes an oscillator responsive to said error signal, and characterized by the steps of: generating a first signal in response to said carrier signal at substantially the symbol rate; generating a second signal responsive to symbol transitions; and combining said first signal, said second signal and a signal derived from said oscillator to generate said error signal.
2. The method of claim 1, characterized in that the digital symbol rate is an integral submultiple of the carrier frequency.
3. The method of claim 1 or 2, characterized in that the signal derived from said oscillator is an integral submultiple of the oscillator frequency.
4. The method of claim 1, 2 or 3, characterized in that said combining step comprises comparing the phase of the signal derived from the oscillator with the phase of said second signal in the presence of symbol transitions and the phase of said first signal at least in the absence of symbol transitions.
5. The method of any one of claims 1 to 3, characterized i,n that said combining step comprises combining the first and second signals and comparing the phase of the resulting signal with the phase of the signal derived from said oscillator.
6. The method of any one of claims 1 to 3, characterized in that the combining step comprises comparing the phases of the first and second signals, respectlvely, with signals derived from said oscillator to produce third and fourth signals; summing the third and fourth signals.
7. The method of claim 6, further characterized by weighting the third and fourth signals to emphasize the effect of said fourth signal relative to that of the second signal.
8. The method of claim 4, 5, 6 or 7, further characterized by disabling said first signal in response to a predetermined condition.
9. The method of claim 8, characterized in that said disabling step comprises detecting the output level of said error signal and disabling said first signal when said output level exceeds a preselected level.
10. The method of claim 5, wherein the first signal is derived from the carrier signal with a counter and characterized in that
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (37)

**WARNING** start of CLMS field may overlap end of DESC **. approach to date for transmitting signals uphole is a system which includes a signal generator 136 controllably driven for selectively interrupting the flow of the mud to thereby impart an acoustic signal to it. The acoustic signal travels upward through the circulating mud in drill string 104 and is detected at the surface by transducer 138 attached to mud line 124. Cartridge 140 is provided for sensing the various downhole conditions and for driving signal generator 136 in accordance with the values of the sensed conditions. Power supply 142 serves to energize cartridge 140 and includes a turbine positioned within the flow of the circulating mud. The details of such a system are disclosed in U.S. Patent No. 3,309,656, for example. The timing signal extraction circuit described above is positioned at the surface to receive at its input the filtered signal from transducer 138. A pump-noise filter 144 removes the mud disturbances caused by pump operation which would otherwise seriously distort the signal from generator 136, as disclosed in U.S. Patent No. 3,742,443. Processing circuit 146 receives the filtered signal and may include further means to improve the signal quality such as a bandpass filter and an automatic gain control. However, the primary function of processing circuit 146 is to recover a carrier clock as well as to demodulate the output of filter 144. These tasks are performed in a well known manner by available circuitry. The above-described timing reconstruction circuit 148 (see FIGS. 1 and 2) receives two inputs 149 and 150 from processing circuit 146 corresponding, respectively, to the carrier clock and the demodulated data signal. A suitable clock signal in phase with the data is produced by circuit 148 in accordance with the detailed discussion provided above and then input to data reconstruction circuit 150. The reconstructed clock is utilized by circuit 152 to recover the information in the data signal on line 150 which is indicative of the measured downhole condition. If PSK modulation is used, circuit 152 may operate to produce a bit decision signal from the input 150 which is then passed through a differential decoder which indicates the occurrence of a transition. A decommutator may also be included which functions under the timing control of circuit 148 to determine the beginning of a data word. Circuitry of this sort is well known and no further details are therefore deemed necessary. (For a presentation of the processing and data reconstruction circuits see Viterbi, A. J., Principles of Coherent Communication, McGraw-Hill, 1966, pages 286-292).The data words and/or measurements derived from the decommutator output may be selectively displayed and/or recorded on a suitable device 154. WHAT WE CLAIM IS:-
1. A method for extracting timing information from a carrier signal modulated with digital symbols, the symbol rate being related to the carrier frequency, wherein a phase-locked loop generates an error signal and includes an oscillator responsive to said error signal, and characterized by the steps of: generating a first signal in response to said carrier signal at substantially the symbol rate; generating a second signal responsive to symbol transitions; and combining said first signal, said second signal and a signal derived from said oscillator to generate said error signal.
2. The method of claim 1, characterized in that the digital symbol rate is an integral submultiple of the carrier frequency.
3. The method of claim 1 or 2, characterized in that the signal derived from said oscillator is an integral submultiple of the oscillator frequency.
4. The method of claim 1, 2 or 3, characterized in that said combining step comprises comparing the phase of the signal derived from the oscillator with the phase of said second signal in the presence of symbol transitions and the phase of said first signal at least in the absence of symbol transitions.
5. The method of any one of claims 1 to 3, characterized i,n that said combining step comprises combining the first and second signals and comparing the phase of the resulting signal with the phase of the signal derived from said oscillator.
6. The method of any one of claims 1 to 3, characterized in that the combining step comprises comparing the phases of the first and second signals, respectlvely, with signals derived from said oscillator to produce third and fourth signals; summing the third and fourth signals.
7. The method of claim 6, further characterized by weighting the third and fourth signals to emphasize the effect of said fourth signal relative to that of the second signal.
8. The method of claim 4, 5, 6 or 7, further characterized by disabling said first signal in response to a predetermined condition.
9. The method of claim 8, characterized in that said disabling step comprises detecting the output level of said error signal and disabling said first signal when said output level exceeds a preselected level.
10. The method of claim 5, wherein the first signal is derived from the carrier signal with a counter and characterized in that
said first and second signals combining step comprises controlling the reset of said counter with said second signal.
11. The method of any one of the previous claims further characterized by the steps of drilling a borehole traversing earth formations, sensing a given parameter during the drilling operation, generating said symbols in response to the sensed parameter, modulating said carrier signal with said symbols, transmitting said modulated signal to the surface, said detecting said transmitted modulated signal at the surface.
12. The method of claim 11, wherein drilling fluid is circulated from the surface downhole and then back to the surface during drilling and characterized in that said modulated signal is acoustically transmitted to the surface through said drilling fluid.
13. The method of claim 11 or 12, further characterized by obtaining a carrier signal and a symbol transition signal from said detected modulated signal and reconstructing said symbols at the surface under the timing control of the signal derived from said oscillator to provide measurements of said parameter.
14. The method of claim 13, further characterized by recording and/or displaying an output derived from the reconstructed symbols.
15. The method of any one of the previous claims, further characterized by synchronizing said first and second signals.
16. An apparatus for extracting timing information from a carrier signal modulated with digital symbols, the symbol rate being related to the carrier frequency, comprising: a phase-locked loop including an oscillator and error signal generating means for controlling said oscillator; and characterized by means responsive to said carrier for generating a first signal at substantially the symbol rate; means responsive to symbol transitions for generating a second signal; and said error signal generating means being responsive to said first signal, said second signal and a signal derived from said oscillator for generating an error signal to control said oscillator.
17. The apparatus of claim 16, characterized in that said first signal generating means comprises a counter.
18. The apparatus of claim 16 or 17 characterized in that said digital symbol rate is in integral submultiple of the carrier frequency.
19. The apparatus of claim 16, 17 or 18 characterized in that said signal derived from said oscillator is an integral submultiple of the frequency of said oscillator.
20. The apparatus of any one of claims 16 to 19, wherein the signal generating means has two inputs and characterized in that said first and second signal generating means are coupled to one input of the error signal generating means and the signal derived from said oscillator is applied to the other input.
21. The apparatus of any one of claims 16 to 19, further characterized by a first comparator means responsive to said first signal and said signal derived from the oscillator to generate a third signal; a second comparator means responsive to said second signal and a signal derived from the oscillator to generate a fourth signal; and a means for summing said third and fourth signals and for providing the summed signal to said error signal generating means.
22. The apparatus of claim 21, further characterized by means for weighting the values of said third and fourth signals at the input to said summing means such that said fourth signal is applied with greater weight than the third signal.
23. The apparatus of claim 17 and 21, characterized in that said second signal is applied to the reset of said counter.
24. The apparatus of claims 17 and 20, characterized in that the output of said counter is connected to said error signal generating means and the reset of said counter is responsive to said second signal.
25. The apparatus of any one of the previous claims, further characterized by means for disabling said first signal in response to a predetermined condition.
26. The apparatus of claim 25, characterized in that said disabling means comprises means for detecting the output level of said error signal generating means and for disabling said first signal when the output level exceeds a preselected level.
27. The apparatus of claim 16, further characterized by means for synchronizing said first signal generating means with said second signal.
28. The apparatus of any one of the previous claims, further characterized by means for drilling a borehole traversing earth formations; means for sensing a given parameter during the drilling operation; means for generating said symbols in response to the sensed parameter; means for modulating said carrier signal with said symbols, means for transmitting said modulated signal to the surface; and means for detecting said transmitted modulated signal at the surface.
29. The apparatus of claim 28, wherein drilling fluid is circulated from the surface downhole and back to the surface during drilling, characterized in that said transmitting means comprises means for acou stically transmitting signals through said drilling fluid.
30. The apparatus of claim 28, characterized by a filter means responsive to the detected modulated signal for reducing noise signals which are generated in the drilling fluid by the pump used for circulating said drilling fluid.
31. The apparatus of claim 29 or 30, further characterized by means for obtaining a carrier signal and a symbol transition signal from said detected modulated signal and for reconstructing said symbols under the timing control of a signal derived from said oscillator.
32. The apparatus of claim 31, further characterized by means for recording and/ or displaying an output derived from the reconstructed symbols.
33. A method of extracting timing information from a carrier signal modulated with digital symbols, the method being substantially as herein described.
34. A well-logging method substantially as herein described.
35. An apparatus for extracting timing information from a carrier signal modulated with digital symbols, the apparatus being substantially as herein described with reference to Figure 1 of the accompanying drawings.
36. An apparatus for extracting timing information from a carrier signal modulated with digital symbols, the apparatus being substantially as herein described with reference to Figure 2 of the accompanying drawings.
37. A well-logging system substantially as herein described with reference to Figure 3 of the accompanying drawings.
GB19325/77A 1976-05-10 1977-05-09 System for extracting timing information from a modulated carrier Expired GB1579488A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220200750A1 (en) * 2020-12-17 2022-06-23 Intel Corporation Closed-loop baud rate carrier and carrier frequency tuning for wireless chip-to-chip interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220200750A1 (en) * 2020-12-17 2022-06-23 Intel Corporation Closed-loop baud rate carrier and carrier frequency tuning for wireless chip-to-chip interface

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NO771514L (en) 1977-11-08
OA05657A (en) 1981-04-30
IT1101653B (en) 1985-10-07
GR63199B (en) 1979-10-04
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CA1119686A (en) 1982-03-09
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FR2351549B1 (en) 1980-02-15
NL7705119A (en) 1977-11-14

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