GB1578553A - Digital transmission - Google Patents

Abstract

In a digital transmission of plesioquinous pulse sequences with positive-negative stuffing, additional information must be transmitted which contains stuffing information, and also an information bit in the case of negative stuffing. Falsification of the additional information due to double and multiple errors is possible when the additional information includes adjacent bits. This error source is eliminated by the fact that every additional information is transmitted serially, forming a stuffing frame, together with a stuffing frame identifier. The additional information occurs in the first time slot of the sixteenth channel in the second, eighteenth, thirty fourth, fiftieth, etc. basic frame. <IMAGE>

Description

(54) IMPROVEMENTS IN OR RELATING TO DIGITAL TRANSMISSION (71) We, SIEMENS AKTIENGESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:: This invention relates to a method of digital communications transmission in which a plurality of plesiochronous pulse sequences internested in a frame for transmission via a t.d.m. transmission system, wherein at the transmitting end of the system pulses are omitted (negative stuffing) from each pulse sequence which has too high a pulse repetition frequency the omitted pulses being substituted for stuffing information bits of the t.d.m. frame, and stuffing pulses are added (positive stuffing) to each pulse sequence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated, the frame containing information channels for items of information, a synchronising channel for a frame code, and stuffing channels for additional items of information each of which consists of stuffing information bits and, in the case of negative stuffing, an information bit.

Such a method of transmission is disclosed, for example, in the "Nachrichtentechnischen Fachberichten", edition 42, 1972, published by the VDE -Verlage GmbH Berlin Charlottenburg, pages 245 to 256. In the system described therein, eight bits of the frame are in each case required for the transmission of the additional information.

The "Siemens-Zeitschrift", 48 (1974) supplement to Nachrichten Ubertragungstechnik, pages 269 to 275, describes a so-called PCM 30 system in which thirty speech signals are transmitted in 30 channels by means of pulse code modulation (PCM), a further channel serves to transmit a frame code and message words, and another channel, namely the channel 16, serves to transmit characteristics for the speech signals. As described in detail in the "Siemens-Zeitschrift", 49 (4975), 7, pages 466 to 472, a super-frame comprising sixteen basic frames is formed for the transmission of the characteristics. As two characteristic words can be transmitted in each basic frame, thirty-two characteristic words can be transmitted in the super-frame. As only thirty are required, one serves for the characteristic frame code, and another as a further message word of which only two of the four bits are used.

This invention seeks to provide a method as recited above in which adulteration of the items of additional information as a result of double and multiple faults which occur when directly adjacent bits become disturbed, is prevented, and which permits plesiochronous pulse sequences to be inserted into the pulse frame of the know PCM 30 system.

According to a first aspect of this invention there is provided a method of digital transmission in which a plurality of plesiochronous pulse sequences are multiplexed in a frame for transmission via a t.d.m. transmission system, wherein at the transmitting end of the system pulses are omitted (negative stuffing) for each pulse sequence which has too high a pulse repetition frequency the omitted pulses being substituted for stuffing information bits of the t.d.m. frame, and pulses are added (positive stuffing) to each pulse sequence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated, the frame containing information channels for items of inform an tion, a synchronising channel for a frame code, and stuffing channels for items of additional information each of which consists of stuffing information relating to a respective associated information channel and, in the case of negative stuffing, an information bit, wherein each item of additional information comprises a plurality of parts and these parts are transmitted serially within respective ones of said frames of a stuffing frame which comprises a plurality of said frames and is determined in accordance with a stuffing frame code which is also transmitted. Preferably a plurality of the items of additional information are assigned a common stuffing frame code.

Expedicntly each item of additional information comprises a four digit code word of which the first three digits aie assigned to the stuffing information and the last digit is, in the case of negative stuffing, assigned to the relevant information bit. In this case preferably the digits of four consecutive items of additional information form a sixteen bit sequence of, in the case of no stuffing. alternately four ones and four zeros; in the case of positive stuffing four ones followed by four zeros twice in succession followed by four ones; and in the case of negative stuffing four ones followed by four zeros followed by four ones followed by three further ones and the relevant information bit.

If one or more items of additional information are transmitted in a PCM 30 system, this is preferably effected in the characteristic channels, in which case the stuffing frame forms a super-frame rclative to the characteristic frame, and a super-super-frame relative to the basic frames. The stuffing frame code can be transmitted in two bits, which are not otherwise used. of the message word in the charactierstic frame. In this case it is advantagcous to use a stuffing frame code which consists of a sequence of zero-zero.

zero-onc, one-zero, and one-one digits.

According to a second aspect of this invention there is provided a t.d.m. transmission system having means for multiplexing a plurality of plesiochronous pulse sequences in a frame for transmission via the t.d.m. transmission system, wherein at the transmitting end of the system, pulses are omitted (negative stuffing) from each pulse sequence which has too high a pulse repetition frcquency, the omitted pulses being substituted for stuffing information bits of the t.d.m.

frame, and pulses are added (positive stuffing) to each pulse sequence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated. the frame containing information channels for items of information, a synchronising channel for a frame code, and stuffing channels for items of additional information each of which consists of stuffing information relating to a respective associated information channel and, in the case of negative stuffing, an information bit, each item of additional information comprising a plurality of parts, means being provided for transmitting the parts of each item of additional information serially in respective ones of said frames of a stuffing frame comprising a plurality of said frames, and means being provided for transmitting a stuffing frame code for determining the stuffing frame.

A t.d.m. transmission system arranged for the digital transmission of a plurality of multiplexed plesiochronous pulse sequences in accordance with the method recited above and comprising a receiving end synchronising device comprising a shift register through which the multiplexed signal is passed, first, second and third frequency dividers which serve to produce pulse trains in synchronism with the multiplex signal, a frame synchronising circuit having inputs connected to outputs of the shift register and serving to control the first frequency divider, a super-frame synchronising circuit having inputs connected to outputs of the shift register and serving to control the second frequency divider. and a stuffing frame synchronising circuit having inputs connected to outputs of the shift register and the super-frame synchronising circuit and serving to control the third frequency divider. Advantageously the stuffing frame synchronising circuit comprises a recognition circuit, which serves to recognise the stuffing frame and to control the third frequency divider, and a monitoring circuit which serves to monitor the stuffing frame in the synchronous state.

The invention will be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Figs. 1 and 2 schematically illustrate a digital data multiplex device and a data insertion device respectively; Fig. 3 schematically illustrates a superframe comprising 16 basic pulse frames; Figs. 4, 5, and 6 are explanatory tables respectively of code words in the sixteenth time channel of the basic frame, additional information in super-super-frames, and the stuffing frame code in the super-superframes; Fig. 7 schematically illustrates a receiving-end synchronising device of a digital data multiplex device; Fig. 8 schematically illustrates a stuffing frame synchronising circuit; and Fig. 9 schematically illustrates a two-stage frequency divider.

Fig. 1 schematically illustrates a digital data multiplex device in which thirty digital signals each having a nominal bit rate of 64 kbit/s are grouped to form a signal having a nominal bit rate of 2048 kbit/s.

Fig. 2 schematically illustrates a data insertion device which is supplied with a 2048 kbit/s signal, the capacity of which is not fully exploited, and a few 64 kbit/s signals which are inserted into the 2048 kbit/s signal when capacity is available, thereby producing an output signal with a nominal bit rate of 2048 kbit/s.

Fig. 3 illustrates 16 basic pulse frames I to XVI forming a super-frame in a PCM 30 system. Coded signals, for example telephone signals, are transmitted in the 8-bit time slots 1 to 15 and 17 and 31 of each basic frame. A frame code word is transmitted in the time slot 0 of each of the odd-numbered basic frames I, III, V,...XV aud a message word is transmitted in the time slot 0 of each of the even-numbered basic frames II, IV,VI,...XVI of the super-frame. In the frame code word and message word represented in Fig. 3, D is a message bit for an urgent alarm N is a message bit for a nonurgent alarm, X is a reserved bit for international use, and Y is a reserved bit for national use. The time slot 16 of each basic frame serves to transmit characteristics.The first four bits of the time slot 16 of the basic frame I serve to transmit the characteristic frame code, and the bits 6 and 7 serve to transmit a message word. The bits 5 and 8 referenced X1 and X2 are not used in the known system but in accordance with this invention are utilised as described below. The time slots 16 of the basic frames II to XVI each transmit two characteristic words comprising four bits, each characteristic word being assigned to a respective one of the 30 speech channels.

It is assumed for example that in the datainsertion device illustrated in Fig. 2 the channel 1 constituted by the time slot 1 in each basic frame is not in use, which has the result that the first four bits in the time slot 16 of the basic frame II are also free. These four bits would be sufficient to transmit the additional information required for transmission of a pulse sequence via the channel 1, but there is a problem that they could be adulterated as a plurality of bits which are situated next to one another and are simultaneously affected by disturbances.

For this reason, only one of the free bits is used for the additional information. As the additional information consists of four bits, for the transmission of these four bits a super-super-frame is formed from four super-frames, i.e. from basic frames I to LXIV. In this super-super-frame the additional information is transmitted as the first bit of the time slot 16 of the basic frames II, XVIII, XXXIV, and L. At least one of the free service bits 5 and 8 (X1 and X2) in the time slot 16 of the basic frame I is used for the frame code of this stuffing frame.

Fig. 4 shows a table which indicates the allocation of the bit positions of the time slot ZA16 of basic frames GR1 to XVI in each super-frame, the letters a to d indicating the four bits of each characteristic word and the associated numerals 1 to 30 indicating the channel to which the bit relates.

Fig. 5 shows a further table which illustrates the allocation of the bit a 1 in the time slot ZA16 of the basic frames II, XVIII, XXXIV, and L in the super-super-frames for the cases of no stuffing 0, positive stuffing +, and negative stuffing -. The protected, two-value stuffing information is contained in the first three bits of each item of additional information. In the case of negative stuffing the fourth bit contains an information bit J. It will be seen that the digits of four consecutive items of additional information form a sixteen bit sequence which, for no stuffing comprises four ones and four zeros alternately for negative stuffing, four ones followed by four zeros twice in succession followed by four ones and for positive stuffing, four ones followed by four zeros followed by four ones followed by three ones and the information bit J.

Fig. 6 shows a table illustrating how the free service bits X1 and X2 in the time slot 16 of the basic frames II, XVIII, XXXIV, and L in the super-super-frames are influenced. In this way the receiver is able to recognise the beginning of the additional information. An item of additional information occupies a transmission time of 8 ms. In comparison, when the bit rates have unfavourable tolerances within their tolerance ranges, a stuffing process is required only approximately every 100 ms.

Fig. 7 illustrates a receiving-end synchronising device of a digital data multiplex device which operates in accordance with the method described above. The synchronising device consists of an 8-bit shift register SR, a frame synchronising circuit RS, a superframe (characteristic frame) synchronising circuit MRS, a super-super-frame (stuffing frame) synchronising circuit SS, a nine-stage frequency divider TL1, a three-stage frequency divider TL2, and a two-stage frequency divider TL3. The stuffing frame synchronising circuit SS and the divider TL3 constitute novel parts of the synchronising device.

The divider TL1 produces from a 2048 kHz pulse train supplied to an input TE pulse trains having frequencies of 1024 kHz to 4 kHz, 4 kHz being the repetition frequency of the frame code word which occurs in alternate basic frames. The divider TL1 is set to zero by a resetting pulse at an input C3. From the 4 kHz pulse train the divider TL2 produces pulse trains having frequencies of 2 kHz, 1 kHz. and 500 Hz, 500 Hz being the repetition frequency of the frame code word of the super-frame. The divider TL2 is set to zero by a resetting pulse at an input C4. From the 500 Hz pulse train the divider TL3 produces pulse trains having frequencies of 250 Hz and 125 Hz, 125 Hz being the repetition frequency of the stuffing frame.The two stages of the third divider TL3 can be set individually to "one" by setting pulses at inputs Sl and S2 or to "zero" by resetting pulses at inputs Cl and C2.

A 2048 kbit/s signal supplied to an input SE passcs through the 8-bit shift register SR, at outputs 1 to 8 of which eight consecutive bits are in each case available in parallel. The frame synchronising circuit RS detects the frame code word in the 2048 kbit/s signal and upon such detection emits a pulse to the input C3 of the divider TL1 which is thereby reset to "zero". In this way, the pulse trains produced by the dividers TL1 to TL3 are synchronised with the basic frames of the 2048 kbit/s signal. All the bit and word pulse trains of the basic frames can be produced from these synchronised pulse trains in known manncr by means of logic circuits.

When the divider TLI has been synchronised, the super-frame synchronising circuit MRS analyses the bits 1 to 4 of the code word in each time slot 16, and as soon as the frame code word of the super-frame (characteristic frame) occurs in these bits the synchronising circuit MRS emits a pulse to the input C4 of the divider TL2 which is thereby reset to "zero". This pulse is also supplied to the stuffing frame synchronising circuit SS.

which analyscs the bits 5 and 8 (Xl and X2) of the code word in the time slot 16.

As shown in Fig. 8 the circuit SS consists of a monitoring circuit comprising two Exclusive-OR gates Gl and G2 and two NAND gates G3 and G4, which monitors the stuffing frame in the synchronised state, and a recognition circuit which recognises the stuffing frame during the synchronising process and sets the divider TL3 accordingly.

The recognition circuit consists of two D flip-flops OFF 1 and FF2. four NAND gates G6 to G9, and an invcrtcr 1.

As shown in Fig. 9 the divider TL3 consists of two JK flip-flop FF3 and FF4 which are constructed in the low-power Schottky technique. The J and K inputs of the flip-flop FF3 are unconnected and thus have the valuc logic "onc".

With the rising flank of the 8 kHz pulse train, the D- flop flip-flops FFI and FF2 receive the bits 5 and 8 of the code word in each time slot 16. When the super-frame synchronising circuit MRS recognises the frame code word of the super-frame, via the inverter I the pulse at the input (?4 temporarily enables the NAND gates G6 to G9. Thus the flip-flop FF3 of the divider TL3 is set to the logic value of the bit 5 and the flip-flop FF4 is set the logic valuc of the bit 8. (In order to set or reset flip-flops constructed in the low-power Schottky TTL technique it is necessary to connect a "zero-pulse" to the input of the Pr of Cl input respectively). If the pulse at the input C4 is available in inverted form, the inverter I can of course be dispensed with.By means of this arrangement, the stuffing frame synchronism is established simultaneously with the super-frame synchronism.

During the synchronising process, the super-frame synchronising circuit MRS emits a logic "zero" to the input El so that the NAND gates G3 and G4 are blocked and logic values "zero" are present at the outputs B5' and B8'. At the end of the synchronising process the synchronising circuit MRS emits a logic "one" to the input El so that the NAND gates G3 and G4 are enabled. The monitoring circuit comprising the gates G1 and G4 compares the bits 5 and 8 in the time slot 16 with the contents of the flip-flops FF3 and FF4 of the divider TL3 and in the event of identity emits a logic "zero" at outputs B5' and B8'.

The super-frame synchronising circuit MRS analyses the signals at the terminals B5' and B8' in the same way as the signals at the terminals B1 to B4. With the rising flank of the 8 kHz pulse train, i.e. at the beginning of the time slot 16. the signals at the terminals B I to B4, B5' and B8' would have to possess the value "zero". If a deviation occurs twice in succession, the super-frame synchronising circuit MRS introduces another synchronising process.

The 2048 kbit/s signal is emitted from the synchronising device at a output SA as shown in Fig. 7.

WHAT WE CLAIM IS: 1. A method of digital transmission in which a plurality of plesiochronous pulse sequences are multiplexed in a frame for transmission via a t.d.m. transmission system, wherein at the transmitting end of the system pulses are omitted (negative stuffing) from each pulse sequence which has too high a pulse repetition frequency the omitted pulses being substituted for stuffing information bits of the t.d.m. frame, and pulses are added (positive stuffing) to each pulse sequ ence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated, the frame containing information channels for items of information, a synchronising channel for a frame code, and stuffing channels for items of additional information each of which consists of stuffing information rclating to a respective associated information channel and, in the case of negative stuffing. an information bit, wherein each item of additional information comprises a plurality of parts and these parts are transmitted serially within respective ones of said frames of a stuffing frame which

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (12)

**WARNING** start of CLMS field may overlap end of DESC **. the 500 Hz pulse train the divider TL3 produces pulse trains having frequencies of 250 Hz and 125 Hz, 125 Hz being the repetition frequency of the stuffing frame. The two stages of the third divider TL3 can be set individually to "one" by setting pulses at inputs Sl and S2 or to "zero" by resetting pulses at inputs Cl and C2. A 2048 kbit/s signal supplied to an input SE passcs through the 8-bit shift register SR, at outputs 1 to 8 of which eight consecutive bits are in each case available in parallel. The frame synchronising circuit RS detects the frame code word in the 2048 kbit/s signal and upon such detection emits a pulse to the input C3 of the divider TL1 which is thereby reset to "zero". In this way, the pulse trains produced by the dividers TL1 to TL3 are synchronised with the basic frames of the 2048 kbit/s signal. All the bit and word pulse trains of the basic frames can be produced from these synchronised pulse trains in known manncr by means of logic circuits. When the divider TLI has been synchronised, the super-frame synchronising circuit MRS analyses the bits 1 to 4 of the code word in each time slot 16, and as soon as the frame code word of the super-frame (characteristic frame) occurs in these bits the synchronising circuit MRS emits a pulse to the input C4 of the divider TL2 which is thereby reset to "zero". This pulse is also supplied to the stuffing frame synchronising circuit SS. which analyscs the bits 5 and 8 (Xl and X2) of the code word in the time slot 16. As shown in Fig. 8 the circuit SS consists of a monitoring circuit comprising two Exclusive-OR gates Gl and G2 and two NAND gates G3 and G4, which monitors the stuffing frame in the synchronised state, and a recognition circuit which recognises the stuffing frame during the synchronising process and sets the divider TL3 accordingly. The recognition circuit consists of two D flip-flops OFF 1 and FF2. four NAND gates G6 to G9, and an invcrtcr 1. As shown in Fig. 9 the divider TL3 consists of two JK flip-flop FF3 and FF4 which are constructed in the low-power Schottky technique. The J and K inputs of the flip-flop FF3 are unconnected and thus have the valuc logic "onc". With the rising flank of the 8 kHz pulse train, the D- flop flip-flops FFI and FF2 receive the bits 5 and 8 of the code word in each time slot 16. When the super-frame synchronising circuit MRS recognises the frame code word of the super-frame, via the inverter I the pulse at the input (?4 temporarily enables the NAND gates G6 to G9. Thus the flip-flop FF3 of the divider TL3 is set to the logic value of the bit 5 and the flip-flop FF4 is set the logic valuc of the bit 8. (In order to set or reset flip-flops constructed in the low-power Schottky TTL technique it is necessary to connect a "zero-pulse" to the input of the Pr of Cl input respectively). If the pulse at the input C4 is available in inverted form, the inverter I can of course be dispensed with.By means of this arrangement, the stuffing frame synchronism is established simultaneously with the super-frame synchronism. During the synchronising process, the super-frame synchronising circuit MRS emits a logic "zero" to the input El so that the NAND gates G3 and G4 are blocked and logic values "zero" are present at the outputs B5' and B8'. At the end of the synchronising process the synchronising circuit MRS emits a logic "one" to the input El so that the NAND gates G3 and G4 are enabled. The monitoring circuit comprising the gates G1 and G4 compares the bits 5 and 8 in the time slot 16 with the contents of the flip-flops FF3 and FF4 of the divider TL3 and in the event of identity emits a logic "zero" at outputs B5' and B8'. The super-frame synchronising circuit MRS analyses the signals at the terminals B5' and B8' in the same way as the signals at the terminals B1 to B4. With the rising flank of the 8 kHz pulse train, i.e. at the beginning of the time slot 16. the signals at the terminals B I to B4, B5' and B8' would have to possess the value "zero". If a deviation occurs twice in succession, the super-frame synchronising circuit MRS introduces another synchronising process. The 2048 kbit/s signal is emitted from the synchronising device at a output SA as shown in Fig. 7. WHAT WE CLAIM IS:

1. A method of digital transmission in which a plurality of plesiochronous pulse sequences are multiplexed in a frame for transmission via a t.d.m. transmission system, wherein at the transmitting end of the system pulses are omitted (negative stuffing) from each pulse sequence which has too high a pulse repetition frequency the omitted pulses being substituted for stuffing information bits of the t.d.m. frame, and pulses are added (positive stuffing) to each pulse sequ ence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated, the frame containing information channels for items of information, a synchronising channel for a frame code, and stuffing channels for items of additional information each of which consists of stuffing information rclating to a respective associated information channel and, in the case of negative stuffing. an information bit, wherein each item of additional information comprises a plurality of parts and these parts are transmitted serially within respective ones of said frames of a stuffing frame which

comprises a plurality of said frames and is determined in accordance with a stuffing frame code which is also transmitted.

2. A method as claimed in claim 1 wherein a plurality of the items of additional information are assigned a common stuffing frame code.

3. A method as claimed in claim 1 or claim 2 wherein each item of additional information comprises a four digit code word of which the first three digits are assigned to the stuffing information and the last digit is, in the case of negative stuffing, assigned to the relevant information bit.

4. A method as claimed in claim 3 wherein the digits of four consecutive items of additional information form a sequence of, in the case of no stuffing, alternately four ones and four zeros; in the case of positive stuffing four ones followed by four zeros twice in succession followed by four ones; and in the case of negative stuffing four ones followed by four zeros followed by four ones followed by three further ones and the relevant information ibt.

5. A method as claimed in any one of claims 1 to 4 wherein the pulse sequence are assigned characteristic channels in which the items of additional information are transmitted.

6. A method as claimed in claims 2 and 5 wherein the stuffing frame code is transmitted utilising otherwise unused service bits present in the characteristic channels.

7. A method as claimed in claim 6 the stuffing frame code comprises a sequence zero-zero, zero-one, one-zero and one-one transmitted utilising two otherwise unused service bits.

8. A method of digital transmission substantially as herein described with reference to Fig. 3 to 6 of the accompanying drawings.

9. A t.d.m. transmission system having means for multiplexing a plurality of plesiochronous pulse sequences in a frame for transmission via the t.d.m. transmission system, wherein at the transmitting end of the system, pulses are omitted (negative stuffing) from each pulse sequence which has too high a pulse repetition frequency, the omitted pulses being substituted for stuffing information bits of the t.d.m. frame, and pulses are added (positive stuffing) to each pulse sequence which has too low a pulse repetition frequency and at the receiving end of the system the pulse sequences are separated from one another and the stuffing pulses are eliminated, the frame containing information channels for items of information, a synchronising channel for a frame code, and stuffing channels for items of additional information each of which consists of stuffing information relating to a respective associated information channel and, in the case of negative stuffing, an information bit, each item of additional information comprising a plurality of parts, means being provided for transmitting the parts of each item of additional information serially in respective ones of said frames of a stuffing frame comprising a plurality of said frames, an d means being provided for transmitting a stuffing frame code for determining the stuffing frame.

10. A t.d.m. transmission system according to claim 9, wherein a receiving end synchronising device comprises a shift register through which the multiplexed signal is passed, first, second, and third frequency dividers which serve to produce pulse trains in synchronism with the multiplexed signal, a frame synchronising circuit having inputs connected to outputs of the shift register and serving to control the first frequency divider, a super-frame synchronising circuit having inputs connected to outputs of the shift register and serving to control the second frequency divider, and a stuffing frame synchronising circuit having inputs connected to outputs of the shift register and the superframe synchronising circuit and serving to control the third frequency divider.

11. A system as claimed in Claim 10 wherein the stuffing frame synchronising circuit comprises a recognition circuit, which serves to recognise the stuffing frame and to control the third frequency divider, and a monitoring circuit which serves to monitor the stuffing frame in the synchronous state.

12. A t.d.m. transmission system as claimed in Claim 10 or Claim 11 wherein the synchronising device is substantially as herein described with reference to Figs. 7 to 9 of the accompanying drawings.