GB1576623A - Television synchronizing apparatus - Google Patents

Description

(54) TELEVISION SYNCHRONIZING APPARATUS (71) We, RCA CORPORATION, a corporation organized under the laws of the State of Delaware, United States of America, of 30 Rockefeller Plaza, City and State of New York, 10020, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to television synchronization apparatus and especially to apparatus for synchronizing the television signals from two or more non-synchronous sources of video information read into memory.

In modern television programming, it is generally necessary to integrate a mix of external and studio video sources smoothly into live programs. An example of such a requirement is the increasing use of Electronic Journalism (EJ) facilities for on-thespot news broadcasts. The wide diversification of such program sources has emphasized the need for synchronizing systems to incorporate non-synchronous video signals originating outside the local studio. Integrating a non-synchronous source into an existing program presents a serious production problem, since it is necessary to lock the studio reference signals to regenerated synchronizing pulses and subcarrier from the outside signal which is known as gen-locking or to use additional sync generators for the proper timing reference. Gen-locking to the external non-synchronous source is particularly troublesome in that only one source at a time may be utilized and that source tends to disrupt the internal studio sync timing. The use of multiple sync generators is expensive and creates further operational difficulties in maintaining gen-lock between the multiple generators. Similar problems are encountered in network cable and satellite transmission systems even though expensive rubidium standards are used because changes in the electrical path length causes the color phase of the video signal to drift, even though the horizontal signal timing component may be relatively stable.

A video synchronizer may be advantageously used to reduce or overcome the problems of incorporating non-synchronous program sources into a local studio broadcast where the conventional gen-locking methods described above do not provide a satisfactory solution. A video synchronizer is primarily a digital device, which accepts a nonsynchronous video signal input from any external source, converts the signal from analog to digital format; stores the digitized signal in a memory; converts the digital signal back to analog form and processes the reconverted signal through a signal processing amplifier wherein sync, blanking and color burst signals are added to the output video signal. The digitized video information stored in the memory is read out at a rate which is synchronous with the local studio sync generator timing. Since the reconstituted video signal is now completely synchronous with the local studio reference, it may be used directly for mixing, special effects, etc., similar to the manner in which a live camera, a video tape machine or other studio source is used.

According to the present invention there is provided a system for processing video information signals in which incoming video signals comprising horizontal line signals are written into memory means, said horizontal line signals having an active video information interval and a horizontal blanking interval, said horizontal blanking interval having horizontal and burst signal synchronizing components, said burst signal components being in a repetitive phase sequence from one horizontal line to another, the system comprising memory means having preassigned fixed burst phasing for each storage element of said memory; input means to which said incoming video signals are applied and through which said incoming video signals are applied to said memory means; output means coupled to said memory means and to a source of independent reference signals; memory control means responsive to said incoming video signals and said reference signals for writing said video signals into and reading said video signals out of said memory; signal processing means responsive to said incoming video signals for developing a horizontal synchronizing and burst timing control signal indicative of the timing of said incoming video signals so that the active video information is written into the store; delay means operable on said control signal for delaying the writing into memory so as to write said active video image information interval into said memory means in accordance with said fixed burst phasing.

In the drawings: FIGURE 1 is a block diagram of a television signal synchronizer embodying the present invention; FIGURE 2 illustrates in graphical form typical television line and field standards useful in understanding the invention; FIGURE 3 is a block diagram of the coherent memory write signal logic embodying the present invention; and FIGURES 4a, 4b, 4c, 4d, 4e and 4f illustrate waveforms depicting the operation of the block diagram of FIGURE 3.

In FIGURE 1, a signal (Video In) from a non-synchronous source, such as an Electronic Journalism (EJ) camera, is coupled to an input terminal of an input video processor 10 in which the incoming video signal synchronizing components and burst timing information are separated from the active picture information. The separated timing information is coupled to a write clock generator 13 which develops timing information in the form of 14.3MHz pulses (four times the NTSC subcarrier frequency of 3.58MHz), synchronous with the incoming signal timing information, for enabling an analog-to-digital (A/D) converter 11, buffer 12 and write address generator 22. The active picture information portion of the incoming video signal is bandwidth limited to 5.5 Megahertz in the input video processor ]0 and coupled from the output terminal of video processor 10 to the input terminal of A/D converter 11, of known form, where the signal is converted (samples at a 14.3 Megahertz word rate) into digital form consisting of 8 bit parallel code words.

The signal output of A/D converter 11, in the form of a digitally samplcd input video signal, is coupled to a buffer 12 and. in turn, to picture memory 20 for storage. The digital picture information signal is stored at discrete locations in the memory in accordance with specific address codes referenced to burst, vertical and horizontal sync signals generated by the write address generator 22 in response to the related incoming signal timing information generated in the write address clock.

Memory 20 is constructed, for example, with memory integrated circuits, such as the Fairchild 40965DC Random Access Memory (RAM). A typical integrated circuit RAM of the type described has a storage capacity of 4096 bits of information. The total capacity of the memory 20 is determined by the number of bits of information desired to be stored. In a typical synchronizer of the type illustrated in FIGURE 1, constructed in accordance with known techniques and utilizing a clock rate of 14.3 Megahertz, a field memory store would require 7280 bits of memory (910 samples times 8 bits per sample) for each horizontal line period of 63.5 Microseconds, which yields a total of 1,863,680 bits of memory for storing the 256 lines of information corresponding to the 262 1/2 horizontal lines in a full field, as illustrated in FIGURE 2. The indicated reduction of horizontal line storage from 262 1/2 to 256 is a practical solution to reducing the expensive memory cost consistent with economical memory logic structure. As illustrated in FIGURE 2, the active picture area actually comprises 242 1/2 lines with the other 20 lines being utilized for the vertical blanking interval. The vertical blanking interval also contains other signal processing information, such as the Vertical Interval Test Signal (VITS) on lines 17 and 18; Vertical Interval Reference Signal (VIRS) on line 19; and the Field Source Identification Signal on line 20 - therefore, it is possible to completely store the 242 1/2 active horizontal information lines per field as well as the vertical interval signal processing information within the 256 lines of memory by beginning the line information storage at line 15.

If the synchronizer is to be of the full frame variety, which requires the storage of two complete fields, - the memory store would require 910 samples per line times 8 bits per sample times 256 lines per field times 2 fields or 3,727,360 bits of memory.

As previously described, the digital picture information is coupled from input video processor 10 to the memory store by means of a buffer 12. Buffer 12 provides a convenient means to overcome a limitation on the data read-in rate of the typical integrated circuit RAMs currently available. The 14.3 MHz clock rate at four times subcarrier was selected to provide sufficient resolution of the picture information being digitized in the A/D converter; however, the typical RAM data read-in rate is generally limited to a 2 MHz rate. Buffer 12, which is in the form of an 8 bit-serial-in/parallel-out configuration (SIPO) provides a convenient means of accommodating this difference in data rates.

Data is serially read into buffer 12 at the 14.3 MHz rate and may be read-out in parallel form at no more than one-eight of the read-in rate, thus readily adjusting the incoming signal to the data-into-memory information rate of 2 MHz.

In order to recover the picture information stored in the memory 20, the signal conversion process is reversed as follows: the data stored in memory is read-out of memory 20 into a parallel-in/serial-out (PISO) buffer, which is, in turn, coupled to a digital-toanalog (D/A) converter 31, which converts the 8 bit code word back to a conventional analog picture by timing information and read address information generated by read clock generator 33 and read address generator 23, which are synchronized to the local studio reference. The output of D/A converter 31 is coupled to an output video processor 32 in which the blanking interval, sync and burst corresponding to local studio reference are added to the recovered picture information to restore the output video signal to a complete composite video signal, as illustrated in FIGURE 2. Thus, the picture information, which was stored in memory 20 from a non-synchronous source is read-out of the memory synchronous with the local studio reference, which makes the signal suitable for programming production requirements of mixing, special effects and switching similar to the manner in which a live camera, VTR tape or other source is used.

Memory control 21 completes the synchronizer of FIGURE 1 and includes logic circuitry which responds to status signals from the write and read address generators identified in FIGURE 1 as ready-to-write and ready-to-read, respectively, so as to provide write and read signals to memory 20 to ensure that reading and writing into the same address location does not occur simultaneously as would be the case where nonsynchronous video sources may drift ahead and behind the fixed local studio reference.

Applying the principles of the present invention, the required memory storage capacity of memory 20, as described in conjunction with FIGURE 1, may be significantly reduced by constructing memory 20 in coherent form having a preassigned burst phasing of 0 or 1800 for each line store of the color video image portion of the composite video waveform. It is readily recognized that in a television signal synchronizer, the horizontal sync timing and burst phasing information contained in the horizontal blanking interval of the incoming video signal is utilized only for purposes of identification for proper writing-into-memory of the image portion of the video signal; and that new horizontal sync and bursts timing components synchronous with the local (studio) reference are established during the readout of the memory store 20. Since these incoming synchronizing components are discarded during readout, it is similarly possible in accordance with the invention to discard the incoming synchronizing components including the burst phasing information on the premise that they are well-known repetitive functions; therefore, the incoming color video information is written into memory 20 to be coherent with and in identity with the preassigned burst phasing. Discarding, i.e., not storing, the horizontal blanking interval information during each horizontal line reduces the time period of each line during which information is to be stored to 52.5 CLsec corresponding to the actual video image portion of the line, as illustrated in FIGURE 2. Utilizing the same clock rate of 14.3 MHz, as previously described, the number of samples per line to be stored is reduced from 910 to 768, thereby significantly reducing the overall capacity and cost of memory 20 by approximately 16%. However, discarding of the incoming burst signal component, which represents the color phasing of the video information, presents a further problem which must be resolved if the advantages of a coherent memory having a preassigned burst phasing are to be realized. In the NTSC color system, there are four distinct fields in a color signal with the burst phasing of each odd field being precisely 1800 from the succeeding odd field; thus, if field 1 is designated as having an initial burst phasing of 0 , field 3 will have a burst phasing of 1800, and, therefore, the even fields 2 and 4 are 1800 and 0 , respectively. Therefore, in a coherent memory not of four fields capacity and having a preassigned fixed burst phasing for example, fields 1 and 4 and 0 and fields 3 and 2 at 1800, it is necessary to modify the reading into memory of fields 3 and 2 so that these fields are stored with identical burst phasing to fields 1 and 4. FIGURES 3 and 4a-4f illustrate how write clock generator 13 and write address generator 22 of the apparatus of FIGURE 1 may be arranged to practise the principles of the invention, namely to provide coherence of the image information being written into a coherent memory store of other than four fields capacity in the case of an NTSC system.

The incoming horizontal sync timing and burst information from input video processor 10 appearing at terminal 15 of FIGURE 1 is coupled to a subcarrier crossover detector in the write clock generator 13 of FIGURE 1 illustrated in FIGURE 3 as follows. The horizontal sync of approximately 5 ILsec duration (waveform 4a) is coupled to the input terminal of a voltage controlled one shot multivibrator 100 which produces a pulse of approximately 2.3 ,usec duration (waveform 4b) timed from the leading edge of the horizontal sync pulse. The output signal of multivibrator 100 is coupled to a one-shot multivibrator 110 which produces a pulse of a duration greater than 140 nanoseconds timed from the trailing edge of waveform 4b and to the reset terminal R of a D flip-flop 130. The output signal from multivibrator 110 and the Q output signal from D flip-flop 130 are coupled to the input terminals of an AND gate 150. The burst subcarrier is coupled to a multiplier 140 where its frequency is doubled and in turn to terminal T of the D flip-flop where it serves as a trigger or clock signal for "D" type flip-flop 130. A biasing voltage +V is coupled to the enabling input terminal of flip-flop 130 to condition the Q output of flip-flop 130 for a LOW level.

Insofar as described, the operation of the subcarrier crossover detector of FIGURE 3 operates in the following manner. The incoming horizontal sync (waveform 4a) enables multivibrator 100 (waveform 4b), which, in turn, enables multivibrator 110 (waveform 4c) providing one input to AND gate 150 and resets D flip-flop 130 (waveform 4d which is the output of flip-flop 130) providing the other input to AND gate 150. The twice subcarrier frequency output of multiplier 140 (waveform 4e) then triggers "D" flip-flop 130 on the very next positive edge (at 2 times subcarrier frequency), which causcs the Q output of the D flip-flop to go low and disable AND gate 150. The trailing edge of the output pulse of AND gate 150 (waveform 4f) represents a precise location for a modified sync signal with respect to burst. which precise location is necessary when burst and sync are not stored so then their timing information is lost. Since the subcarrier burst signal is not defined in the television standards with respect to the leading edge of sync, it may happen that the output of AND gate 150 can vary in width from approximately 0 to 140 nanoseconds in time, with 0 time representing a coincidence between subcarrier and the leading edge of sync, so as to prevent the subcarrier crossover detector of FIGURE 3 from reliably indicating the burst phasing at the output of AND gate 150. To avoid this problem, a hysteresis feedback loop is incorporated in the circuit of FIGURE 3 by coupling the output of AND gate 150 to a low pass filter 120, which develops a voltage at its output representing the average width of the output pulse of AND gate 150. The output signal of low pass filter 120 is coupled to voltage controlled multivibrator 100 where it is utilized as a control voltage to modify the duration of the output signal of multivibrator 100 to ensure an adequate time difference for the generation of the output pulse from AND gate 150.

The output signal from AND gate 150, which represents a composite of the horizontal sync and burst timing of the incoming color video information, is coupled to terminal 16 of write address generator 22 of FIG URE 1 and in turn to switch Si, shown diagrammatically, which couples in a first position the composite horizontal sync and burst timing signal directly to the ready-to-write pulse generator in write address generator 22 in which the ready-to-write-into memory signal appearing at terminal 17 of FIGURE 1 is developed. In the other position of switch Si, the output signal of AND gate 150 is delayed in delay circuit 170 a fixed amount, 140 nanoseconds in the NTSC system, so as to delay the development of the ready-towrite-into memory signal, which effectively shifts the color image information by 1800 to coincide with the preassigned burst phasing of coherent memory 20. A field identification switch 190 enabled by the field identification signal of the incoming video signal is utilized to determine if the writing-intomemory is to be delayed in the following manner:- field 1 - no delay, field 3 - delay, field 2 - delay, and field 4 - no delay. Thus, the color video information is stored coherently in accordance with the preassigned burst phasing without loss of color coherency on read-out in a memory of significantly reduced capacity as compared to a memory constructed in accordance with the prior art practice of storing the entire horizontal line interval including the horizontal blanking interval in the memory.

The above described technique may be applied, by those skilled in the art, to construct a system for operating on one or more horizontal lines to function as a time-base corrector, where the delay sets the correction cyclically, because the conector, incorrect incoming timing information is not used for read-out.

Although the present invention has been described in terms of a composite video signal according to the NTSC television standards, the principles of the invention are equally applicable to other television standards such as PAL, PAL-M, and S.E.C.A.M.

These other standards do contain differences from the NTSC system which require modification to the portions of the synchronizer, among these are: the clock frequencies must be adjusted for differences in subcarrier frequency which determines the number of samples per line, i.e., 4.33 Megahertz in PAL versus 3.58 Megahertz in NTSC. Similarly, the capacity of the memory in terms of lines stored must be adjusted to accommodate the number of lines in each system, typically 625 in PAL, 525 in PAL-M, and 625 in S.E.C.A.M. In additon, the memory organ ization and controlling logic must be adjusted to the individual color signal differences in each system such as the eight unique fields in PAL in terms of burst phase sequence as against only four unique fields in terms of the NTSC burst phase sequence, while in SECAM the burst frequency in the form of an undeviated subcarrier alternates for succeeding lines between two different frequencies. The horizontal and vertical synchronizing signals of each television system must also be accommodated in generating the write addresses for writing-into-memory and generating the read addresses for reading-out of memory.

WHAT WE CLAIM IS: 1. A system for processing video information signals in which incoming video signals comprising horizontal line signals are written into memory means, said horizontal line signals having an active video information interval and a horizontal blanking interval, said horizontal blanking interval having horizontal and burst signal synchronizing components, said burst signal components being in a repetitive phase sequence from one horizontal line to another, the system comprising memory means having preassigned fixed burst phasing for each storage element of said memory; input means to which said incoming video signals are applied and through which said incoming video signals are applied to said memory means; output means coupled to said memory means and to a source of independent reference signals; memory control means responsive to said incoming video signals and said reference signals for writing said video signals into and reading said video signals out of said memory; signal processing means responsive to said incoming video signals for developing a horizontal synchronizing and burst timing control signal indicative of the timing of said incoming video signals so that the active video information is written into the store delay means operable on said control signal for delaying the writing into memory so as to write said active video image information interval into said memory means in accordance with said fixed burst phasing.

2. The system for processing video information signals as claimed in Claim 1, where in said video signals include a plurality of said horizontal line signals forming a television field, and said memory means has a plurality of said storage elements for storing said plurality of horizontal lines.

3. A video signal storing and read-out system substantially as hereinbefore described with reference to the drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

**WARNING** start of CLMS field may overlap end of DESC **. ization and controlling logic must be adjusted to the individual color signal differences in each system such as the eight unique fields in PAL in terms of burst phase sequence as against only four unique fields in terms of the NTSC burst phase sequence, while in SECAM the burst frequency in the form of an undeviated subcarrier alternates for succeeding lines between two different frequencies. The horizontal and vertical synchronizing signals of each television system must also be accommodated in generating the write addresses for writing-into-memory and generating the read addresses for reading-out of memory. WHAT WE CLAIM IS:

1. A system for processing video information signals in which incoming video signals comprising horizontal line signals are written into memory means, said horizontal line signals having an active video information interval and a horizontal blanking interval, said horizontal blanking interval having horizontal and burst signal synchronizing components, said burst signal components being in a repetitive phase sequence from one horizontal line to another, the system comprising memory means having preassigned fixed burst phasing for each storage element of said memory; input means to which said incoming video signals are applied and through which said incoming video signals are applied to said memory means; output means coupled to said memory means and to a source of independent reference signals; memory control means responsive to said incoming video signals and said reference signals for writing said video signals into and reading said video signals out of said memory; signal processing means responsive to said incoming video signals for developing a horizontal synchronizing and burst timing control signal indicative of the timing of said incoming video signals so that the active video information is written into the store delay means operable on said control signal for delaying the writing into memory so as to write said active video image information interval into said memory means in accordance with said fixed burst phasing.

2. The system for processing video information signals as claimed in Claim 1, where in said video signals include a plurality of said horizontal line signals forming a television field, and said memory means has a plurality of said storage elements for storing said plurality of horizontal lines.

3. A video signal storing and read-out system substantially as hereinbefore described with reference to the drawings.