GB1573310A

GB1573310A - Transistors

Info

Publication number: GB1573310A
Application number: GB2718879A
Authority: GB
Original assignee: Mullard Ltd
Current assignee: Philips Components Ltd
Priority date: 1977-02-09
Filing date: 1977-02-09
Publication date: 1980-08-20

Description

(54) TRANSISTORS (71) We, MULLARD LIMITED, of Abacus House, 33 Gutter Lane, London EC2V 8AH, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to transistors including a base region through which current flow is by hot charge carriers.

So-called "hot-electron transistors" are described on pages 587 to 615 of the book by S.M. Sze entitled "The Physics of Semiconductor Devices", published by Wiley Inter-science, copyright 1969. These transistors comprise a semiconductor body including a base region through which current flow is by hot charge carriers (electrons, in the forms described), and barrier-forming means which form with said base region emitter-base and base-collector barriers. The emitter-base barrier or barriers serves for injection of the hot charge carriers into the base region, and the base-collector barrier or barriers serves for collection of said hot charge carriers from the base region.

The barrier-forming means may be a metal-insulator barrier where the hot carriers are injected into the base region by tunnelling through a thin insulator layer, or a metal-semiconductor Schottky barrier where the hot carriers are injected into the base region by Schottky-type thermionic emission. In this latter case at least one of the barriers is present between the base region and a semiconductor region which is of one conductivity type and which forms an emitter region or collector region of the transistor.

A hot charge-carrier is one which is not in thermal equilibrium with the lattice. Thus a hot electron has an energy more than a few k.T above the Fermi energy (where k and T are Boltzmann's constant and the lattice temperature respectively), whereas a hot hole has an energy more than a few k.T below the Fermi energy.

As described in said book by Sze, different forms of hot-electron transistor have been previously proposed over many years but without producing a commercially feasible transistor. These previously proposed forms of hot-electron transistors have consisted basically of alternating layers of metal and insulator or semiconductor and metal, and some have included Schottky-barriers. A common feature of all these devices was that the base region has been formed by a thin sandwiched metal layer.

Such previously proposed devices have been technologically difficult to manufacture.

Interface problems have occurred between the different materials. The charge-carriers have to traverse a number of interfaces between different materials and through semiconductor and/or dielectric materials of different energy band gaps combined in a common device structure. This has resulted in poor carrier transport and poor emitter and collector efficiency.

According to a first aspect of the present invention a transistor including a base region through which current flow is by hot charge carriers, and barrier-forming means which form with said base region emitter-base and base-collector barriers, the emitter-base barrier or barriers serving for injection of the hot charge carriers into the base region, and the base-collector barrier or barriers serving for collection of said hot charge carriers from the base region, at least one of said barriers being present between the base region and a semiconductor region which is of one conductivity type and which forms an emitter region or a collector region of the transistor, is characterized in that said semiconductor region forms part of a semiconductor body in or on which said barrier-forming means are provided, in that another semiconductor region of said one conductivity type is present in said semiconductor body and forms said base region, and in that said hot charge-carriers are majority carriers in said base region.

Such a transistor in accordance with the present invention may be either a hot-electron or hot-hole transistor. Because it has such a semiconductor base region its emitter-base and collector-base barriers can be formed in the semiconductor body comprising said base region so that interface problems can be reduced (or even eliminated in some forms of the transistor). At least one of the barriers formed with the base region can comprise a substantially depleted semiconductor barrier region separating the base region from said semiconductor region which forms said emitter region or collector region of the transistor and which is also present in the same semiconductor body.

Thus, according to a second aspect of the invention there is provided a transistor comprising a semiconductor body including a base region through which current flow is by hot majority charge carriers and barrier-forming means which form with said base region emitter-base and base-collector barriers, said base region being a first semiconductor region of one conductivity type, a second semiconductor region of the one conductivity type forming an emitter region or collector region of the transistor, said base region having a higher doping concentration of the one conductivity type than the second region, one of said barrier-forming means being a semiconductor barrier region which separates the base region from said second region, said barrier region having an impurity concentration characteristic of the opposite conductivity type the magnitude of which determines the height of a potential barrier to the flow of charge carriers of the one conductivity type from both the base region and the second region, which barrier region forms depletion layers at zero bias with both the base region and second region and is sufficiently thin that said depletion layers formed at zero bias together substantially deplete the whole of said barrier region of mobile charge carriers of both said one and opposite conductivity types, the current flow through the barrier region being by charge carriers of said one conductivity type. The other of said barrier-forming means may be of known type such as a metal-semiconductor Schottky barrier, or it may comprise another substantially depleted semiconductor barrier region which separates the base region from a third semiconductor region of the one conductivity type also provided in said body.

The height of the potential barrier between the base region and the second region (and thus the magnitude of the current flow across the barrier region for a given bias voltage) is related to the magnitude of the impurity concentration characteristic of said opposite conductivity type in said barrier region. Such an impurity concentration may be formed by introducing into the semiconductor crystal-lattice radiation damage which has energy levels characteristic of said opposite conductivity type in the semiconductor; such damage centres may be formed by for example implantation of neutral impurity ions. However, in a presently preferred form, the barrier region is a semiconductor region doped with impurity atoms of said opposite conductivity type which form said impurity concentration of said barrier region; such doping permits the barrier region to have a more easily reproducible and very high impurity concentration of said opposite conductivity type.

Reference is invited to our co-pending Patent Application No. 11835/76, Serial No.

1573309 from which the present application is divided and which describes and claims a semiconductor device comprising a semiconductor body including first and second regions of one conductivity type and a barrier region which separates the first and second regions from each other, which first region has a higher doping concentration of the one conductivity type than has the second region. which barrier region is a semiconductor region having an impurity concentration characteristic of the opposite conductivity type the magnitude of which determines the height of a potential barrier to the flow of charge carriers of the one conductivity type from both the first and second regions the barrier region being sufficiently thin that depletion layers which it forms at zero bias with both said first and second regions merge together in said barrier region to substantially deplete at zero bias the whole of said barrier region of mobile charge carriers of both said one and opposite conductivity types, and means defining in the device a current path between the first and second regions through the barrier region, the current flow through the barrier region being by charge carriers of said one conductivity type.

The formation of such substantially-depleted semiconductor barrier regions and characteristics resulting therefrom which can be used in transistors in accordance with the present invention will now be described with reference to Figures 1 to 6 of the accompanying drawings. These Figures 1 to 6 are also described in said co-pending patent application.

Figure 1 shows the variation with depth of the net doping levels, electron energy and space charge for a semiconductor structure comprising a thin region of acceptor impurities in an n-type semiconductor body portion, in thermal equilibrium; Figure 2 is the potential diagram of a semiconductor device which is not in accordance with the present invention and which has a region structure similar to that of Figure 1; Figure 3 is a potential diagram for a semiconductor device which is claimed in said co-pending application but which is not in accordance with the present invention; Figure 4 is a cross-sectional view of a semiconductor body portion of a semiconductor diode which is claimed in said co-pending application but which is not in accordance with the present invention; Figure 5 shows the current/voltage characteristics of such a semiconductor diode as illustrated in Figure 4, and Figure 6 is a cross-sectional view of a semiconductor body portion of another semiconductor diode which is claimed in said co-pending application but which is not in accordance with the present invention.

Thereafter embodiments of the present invention which illustrate various features of the invention and their advantages will be described, by way of example, with reference to Figures 7 to 10 of the accompanying diagrammatic drawings, in which: Figure 7 is a potential diagram of a transistor which is in accordance with both the first and second aspects of the present invention, and which is also briefly described in said co-pending application; Figure 8 is a cross-sectional view of a semiconductor body portion of such a transistor as illustrated in Figure 7; Figure 9 is a cross-sectional view of a semiconductor body portion of an integrated circuit comprising a transistor in accordance with both the first and second aspects of the invention, and Figure 10 is a potential diagram of a further transistor in accordance with both the first and second aspects of the invention.

It should be understood that the drawings are only diagrammatic, and that, in particular, in the drawings of the device structures, various thicknesses have been shown exaggerated for the sake of clarity, whereas others have been reduced for the sake of convenience.

Reference will first be made, by way of introduction, to Figures 1 to 6 which relate to structures not in accordance with the present invention.

Figure 1 illustrates a simplified situation where a small number of acceptor atoms A are introduced into the bulk of an n-type semiconductor body portion of a substrate having a uniform doping concentration Nn to form a thin region 1 having a net acceptor concentration NA separating regions 2 and 3 of the substrate. Figure 1(a) shows the net acceptor or donor concentration N as a function of depth d in the substrate. Figure 1(b) is the corresponding electron energy diagram showing the energy band gap between the valence band edge Ev and the conduction band edge Ec, together with the Fermi level EF and the energy levels of the acceptors A adjacent Ev and of the donors D adjacent Ec.

Figure 1(c) shows the space charge distribution Q.

In the region 1 separating the n-type regions 2 and 3, the donor concentration has been overcompensated by a high concentration of acceptor impurity. However all the impurities in the narrow region 1 are depleted by the merging of the depletion layers formed naturally at the junctions 2-1 and 1-3 at zero bias. This results in the negative space charge shown throughout region 1 in Figure 1(c).

As commonly understood in the semiconductor art, a semiconductor region (such as the region 1) is said to be substantially depleted of charge carriers of both conductivity types when the number of mobile charge carriers of both conductivity types is negligible (usually for example at least two orders of magnitude less) compared with that of the net impurity concentration in said region.

The presence of the negative space-charge region illustrated in Figure 1(c) introduces band bending as shown in Figure 1(b), and a barrier to electron flow results. The height of this barrier is represented by Q)o in Figures 1(b) and 2.

Thus, the substantially depleted region 1 provides a potential barrier Qlo to the flow of electrons from both the first and second n-type regions 2 and 3 of the substrate. Figure 2 is a potential diagram which follows the conduction band edge and illustrates the behaviour of such a structure with opposite bias voltages applied between electrode connections to the first and second regions 2 and 3. The potential curve 10 illustrates the situation without the application of any bias voltages between the regions 2 and 3. The potential curves 11 and 12 are for when the region 3 is biased respectively negatively (V1) and positively (V2) with respect to the region 2. Vl and V2 represent respectively the negative and positive bias voltages measured relative to the Fermi level EF at zero bias. EF1 and E represent respectively the Fermi levels with negative and positive bias voltages V1 and V2. The barrier at zero bias voltage is 0. This barrier is reduced by the application of positive bias voltage V2. The potential barrier for electrons from region 3 under bias voltage V1 is represented byl. The potential barrier for electrons from region 2 under bias voltage V2 is represented by 2- Both l and 2 are less that 00. Because the doping concentration of region 2 is the same as that of region 3 l equals 2 when V1 equals V2. This would result in a symmetrical device which will turn-on in both bias directions at substantially the same value of V1 and V2.

A non-symmetric device is illustrated in Figure 3. This device structure has a substantially depleted barrier region 1 which is similar to that of Figures 1 and 2 and separates first and second regions 2 and 3 both of which are of one conductivity type, for example n-type.

However in this device structure the first region 2 has a higher doping concentration (n+) of the one conductivity type than has the second region 3. A current path defined by electrode connections to regions 2 and 3 is present between the first and second regions 2 and 3 through the barrier region 1. The current flow through the barrier region 1 is by charge carriers of said one conductivity type (i.e. electrons with n-type regions 2 and 3).

The barrier region 1 is a semiconductor region having an impurity concentration characteristic of the opposite conductivity type which is higher than the doping concentration of said one conductivity type in said barrier region 1 so as to provide the potential barriers to the flow of charge carriers of the one conductivity type from both the first and second regions 2 and 3 and to form depletion layers at zero bias with both the first and second regions 2 and 3. The barrier region 1 is sufficiently thin that said depletion layers formed at zero bias with both said first and second regions 2 and 3 merge together in said barrier region 1 to substantially deplete at zero bias the whole of said barrier region 1 of mobile charge carriers of both said one and opposite conductivity types. Apart from the depletion layers formed with region 1, regions 2 and 3 remain undepleted at zero bias.

An approximate solution of Poisson's equation in this situation gives: q. - s Ns. t. ..... (1) 2E.ò.

where q is the charge on an electron, E0 iS the permittivity of free space, e is the relative permittivity of the semiconductor material, o is the potential barrier, under zero bias conditions, for electrons crossing from region 2 to region 3, t is the thickness of the barrier region 1, and Ns equals (t.NA) and is the net space charge density in the barrier region 1.

Because Ns corresponds to the net impurity of said opposite type per unit area of the barrier region 1, it can be related to, for example, impurity ion doses which may be implanted to form such a barrier region 1.

For significant band bending to occur, (lo should be greater than, for example, k.T/q, where k is Boltzmann's constant and T is the absolute temperature. Therefore, from equation (1), for a thickness t of for example 100 A, Ns should be greater than approximately 2 x 1011 impurity atoms per cm However, if the Fermi level EF were to come within a few k.T of the valence band edge Ev in the barrier region 1, the barrier region 1 would no longer be depleted of mobile charge carriers of said opposite conductivity type so that p-n junction formation would occur. This limits the maximum value of (Zlo for that semiconductor, and sets an upper limit on the permissible magnitude of Ns for a given value of t. Thus, from equation (1), for a silicon semiconductor body, the value of Ns should be less than approximately 2 x 1013 impurity atoms per cm for a barrier region thickness t of 100 A in order to maintain that region substantially depleted.

Returning now to Figure 3, the n-type region 2 is more highly doped (n+) with donors than the n-type region 3. As a result the barrier IZll to electrons from region 3 under bias voltage Vl (region 3 biased negative with respect to region 2) is less than the barrier 2 to electrons from region 2 under bias voltage V2 (region 3 biased positive with respect to region 2 by V2 of equal magnitude to V1). Thus, the device will turn-on and conduct current at a lower voltage when region 3 is biased negative with respect to region 2 than when it is biased positive. Typically, the turn-on for negative bias (V1) may occur at less than 1 volt (the electrons flowing from n-type region 3 through barrier region 1 to n-type region 2), whereas the turn-on for positive bias (V,) may occur at more than 10 volts (the electrons flowing from n-type region 2 through barrier region 1 to n-type region 3). The actual values of Vl and V2 for turn-on are determined by the asymmetrical doping chosen for the regions 2 and 3. The doping concentration of the first region 2 may be made at least 2, or 3, or even 4 orders of magnitude higher than that of the second region 3.

The impurity of the barrier region 1 may be a shallow-level dopant which is of opposite conductivity type to said one conductivity type of the first and second regions 2 and 3. Such a shallow-level impurity forms a shallow energy-level in the band gap of the semiconductor material adjacent the opposite edge of the band gap to impurity of said one conductivity type. However, the barrier region 1 may instead be doped with a deep-level impurity of said opposite conductivity type. Such an impurity has an energy level deep in the band gap away from both the edges Ec and Ev of the band gap and towards its middle. A possible advantage of using such a deeper level impurity is that by providing a sufficiently high doping the potential barrier can approach a value corresponding to the deep energy level of the impurity which value is insensitive of the magnitude of the deep-level doping.

For a given thickness t, the number Ns of impurity atoms of said opposite conductivity type in the barrier region 1 generally determines the height of the potential barrier loo between the first and second regions 2 and 3, and thus the magnitude of the current flow across the barrier region 1 for a given bias voltage. In order to obtain maximum asymmetry in the characteristics it is advantageous to have a small thickness t and a high net doping Ns for region 1. Therefore, preferably the impurity concentration of said opposite conductivity type in barrier region 1 is, for example, at least one or two orders of magnitude higher than the impurity concentration of said one conductivity type in that region. Such a high concentration means that the barrier region 1 must also be very thin to remain depleted at zero bias. Typically barrier region 1 has a thickness of, for example, at most approximately 250 .

Figure 4 illustrates one specific form of a diode structure which has an asymmetric current-voltage characteristic as a result of its first region 2 having a higher doping concentration of the one conductivity type than the second region 3. This diode is therefore of the general type illustrated by the potential diagram of Figure 3. In this device, the first region 2 adjoins a surface of the semiconductor body 20 and is separated by the substantially depleted barrier region 1 from an underlying semiconductor body portion 3 which belongs to the second region of the diode. The surface-adjacent region 2 is therefore simply contacted by an electrode 22 provided on the semiconductor body surface. The region 2 is laterally bounded by an undepleted annular zone 24 of opposite conductivity type which extends sufficiently deeply in the body 19 to intersect the barrier region 1. The undepleted annular zone 24 acts as a guard ring similar to guard rings used in known Schottky diode configurations. The zone 24 ensures that the region 2 is laterally separated from the surrounding part of region 3 and not short-circuited thereto at the edge of barrier region 1. As will be described hereinafter such an undepleted zone 24 may be formed during the same doping step as is used to form the depleted barrier region 1. However as will be described with reference to Figure 4, zone 24 may have a doping which differs from that of said barrier region. This permits the doping and depth of the zone 24 to be chosen more independently so that zone 24 may form a higher barrier with region 3 than does barrier region 1.

The second region 3 of the diode shown in Figure 4 is part of an epitaxial layer present on a more highly conductive substrate 13 which is also of the one conductivity type. An electrode connection 23 to the region 3 contacts the back surface of the substrate 13. In this manner a simple discrete diode structure with opposite electrodes 22 and 23 is formed.

The diode structure of Figure 4 can be manufactured in the following manner. For the purpose of this example it will be assumed that the one conductivity type of the first and second regions 2 and 3 is n-type.

On a high conductivity n-type monocrystalline silicon substrate 13, an n-type silicon epitaxial layer 3 is grown in known manner. The epitaxial layer 3 may have a resistivity of typically 5 ohm-cm, for example, and a thickness of, for example, 12 microns. On the surface of the layer 3 a thermal oxide layer is grown in known manner for use as a dopant mask. Using known photolithographic and etching techniques annular windows are etched through the oxide layer where the annular zones 24 are to be provided in the epitaxial layer.

It will be understood that generally many diodes are manufactured simultaneously in the same semiconductor wafer by effecting the processing at many locations on the wafer and subsequently dividing the wafer to provide separate semiconductor bodies for each semiconductor device. However for the sake of simplicity the manufacturing process will be described solely in terms of the processing effected at one such location.

After opening the annular window in the oxide mask, acceptor dopant is introduced into the epitaxial layer 3 to form the p+ annular zone 24 extending to a depth deeper than that at which the barrier region 1 will be formed. Such dopant may be introduced by known techniques, for example thermal diffusion of boron. After forming the zone 24, the whole dopant mask is removed, the surface of the epitaxial layer 3 is cleaned, and a fresh insulating layer 26 is provided in known manner. This layer 26 may be of, for example, thermally grown silicon oxide having a thickness of, for example, 1200 A. By using known photolithographic and etching techniques, the insulating layer 26 is then provided with a window 21 which overlaps slightly the inner edge of the previously-provided p+ annular zone 24. Through the window 21 impurity ions are implanted while using the layer 26 as an implantation mask to form a highly-doped n+ surface region 2 and a very thin highly doped but substantially depleted barrier region 1. Preferably the ion energy and mass are selected to make the region 1 as thin as possible (for example approximately 150 A thick), and the ion dose is selected to make the region 1 as highly doped as possible. The ions for region 1 may be of a shallow-level acceptor impurity to overcompensate the donor impurity of the substrate in the region 1. A suitably massive acceptor ion is indium at an ion beam energy of, for example 20 keV. This energy for indium ions will produce a maximum impurity concentration for the potential barrier region at a depth of approximately 150 A spaced from the silicon surface.

The region 2 is formed by a donor implant of, for example, 10 keV antimony ions which gives the region 2 a depth of approximately 100 . The donor dose used for the diode region 2 of Figure 4 may overdope the inner edge of the p+ guard ring 24 where exposed at the window 21. Preferably the region 2 is implanted before the region 1 to reduce channelling of the implanted ions and so reduce the width of barrier region 1. For the same reason, the implantations are preferably effected at an angle to the major semiconductor crystal axes.

The implantations to form regions 1 and 2 may be effected at room temperature with doses typically between for example 1013 and 101 antimony ions/sq.cm. for region 2, and for example 5 x 1012 to 5 x 1013 indium ions/sq. cm. for region 1. Both implantations are subsequently annealed at, for example a temperature typically of 750"C and in high vacuum, without the occurrence of any significant diffusion. These ion doses for the barrier region 1 are higher than the net values of Ns suggested hereinbefore, since it is necessary to overdope both the epitaxial layer doping in region 1 and the donor impurities also in this region due to the implantation of region 2.

After annealing the implants, the n-type regions 2 and 3 are provided in known manner with electrode connections in the form of conductive layers 22 and 23 respectively. By providing the layers 22 and 23 which make a substantially ohmic connection to the regions 2 and 3, a majority carrier diode results. The electrodes 22 and 23 are typically of a metal, for example aluminium or titanium.

Figure 5 shows the current-voltage characteristics of such an asymmetric diode having the general structure shown in Figure 4 and manufactured using such a method. The diode of Figure 5 had an n-type epitaxial layer 3 of 4 ohm.cm. resistivity. The boron-diffused annular zone 24 was 0.5 micron deep and of circular symmetry with an inner diameter of 55 microns and an outer diameter of 90 microns. The window 21 in the oxide layer 26 was also circular with a diameter of 70 microns. The first region 2 was formed by an antimony implant dose 5 x 1013 ions/sq. cm. at 10 keV. The barrier region 1 was formed by an indium implant dose of 1 x 1013 at 30 keV. The implantations were annealed together for 15 minutes at 750"C in vacuo.

The current-voltage characteristics of Figure 5 were measured by applying forward and reverse bias voltages V1 and V2 across the diode electrodes 22 and 23 as indicated in Figure 4, and measuring the resulting current flow I. Under the forward bias condition V1 the higher doped n-type region 2 was biased to a positive potential with respect to the less highly doped n-type region 3, and characteristic I-V1 of Figure 5 was obtained. Under reverse bias condition V2 region 2 was biased negatively with respect to region 3, and the characteristic I-V2 was obtained. The abscissa of the graph of Figure 5 is the forward and reverse voltages V1 and V2 in volts, the ordinate of the graph is the current flow I through the diode in milliamp the devices of Figures 3 and 4 will be designated by the same references.

In the device illustrated in Figure 6, the annular zone 24 has been formed during the same doping step as was used to form the depleted barrier region 1. The advantage of such a feature is that the number of processing steps needed for the manufacture is significantly reduced and a very compact device structure can be formed. This can be achieved in the following manner. After depositing the epitaxial layer 3, thermally grown silicon oxide layer 26 is provided for example to a thickness of 1500 . Window 21 corresponding to the outline of the required first region 2 is then provided in layer 26 and ions for forming the first region 2 are implanted at the window 21 using the layer 26 as an implantation mask.

The device structure is then subjected to a dip-etch in, for example, dilute hydrofluoric acid to etch away about, for example, 400 A of the layer 26. This dip-etch therefore slightly widens the window 21. The widened window 21 is subsequently used as an implantation window for the barrier region implant which extends to the surface around the region 2 implant. The widened window 21 may also be used as a contact window for the electrode 22 contacting the first region 2; in this case electrode 22 also contacts the annular zone 24. The etch-widening of the window 21 and hence the width of the resulting annular zone 24 may be made sufficiently small that this zone 24 is also substantially depleted. However, a wide zone 24 formed during the barrier region implant is not fully depleted and so behaves similar to the diffused p-type zone 24 in the device of Figure 4. If desired, a further insulating layer may be deposited in the enlarged window 21 either before or after the barrier region implant, and a contact window may be subsequently provided in this further layer so as to expose only the region 2 for contacting by the electrode 22.

Another modification illustrated in Figure 6 is the inclusion of a zone 30 of enhanced doping concentration in the second region 3 in the depletion layer formed with said barrier region 1. The doping concentration of the zone 30 is higher than that in the underlying bulk of said region 3. Such an enhanced doping concentration can readily be formed by ion implanting in region 3 dopant ions which are of the same conductivity type as region 3, the implantation being effected at such an energy that these ions have a range in the semiconductor body slightly greater than that of the ions in the barrier region implant. If the zone 30 of enhanced doping concentration is located at least mainly within the zero-bias depletion layer which extends into region 3 from barrier region 1 there is a negligible effect on the asymmetric doping of regions 2 and 3. The zone 30 is therefore preferably provided within approximately 150 A of the barrier region 1. Such a locally enhanced doping serves to increase the magnitude of the electric field in the region 3 adjacent the barrier region 1.

As a result, the fall-off of the potential curve in region 3 shown in the potential diagram of Figure 3 becomes steeper, and carriers will more readily pass over the potential barrier between regions 2 and 3. A typical donor ion dose for forming the zone 30 may be, for example, between 2 and 5 x 1012 arsenic ions/sq. cm.

Figure 6 also illustrates a further modification in which the electrode 22 which contacts the first zone 2 is apertured.

The remaining Figures 7 to 10 are concerned with integrating the barrier region 1 and the first and second regions 2 and 3 of the Figures 3 to 6 structures with other semiconductor regions and electrodes to form transistors in accordance with the present invention.

Thus, an interesting majority carrier (unipolar) transistor structure in accordance with the present invention results when the region 2 is additionally contacted by a Schottky metal contact M. The Schottky contact acts as the emitter and injects electrons into the n-type region 2; this of course requires the Schottky contact to be operated under reverse bias. The n-type region 2 acts as the base and is provided with an ohmic contact 22 (the base contact) in addition to the Schottky contact M.

The n-type region 3 acts as the collector. It should be noted that in the base (region 2) of such a transistor structure the current is carried by majority charge carriers i.e. electrons in an n-type region 2. The emitter barrier (Schottky barrier) should be chosen to be higher than the barrier of the barrier region 1. The energy band diagram of such a transistor is shown in Figure 7. The energy of the majority carriers which carry the current in the base 2 between the emitter and collector is significantly higher than the Fermi energy so that such a transistor is a so-called "hot-electron transistor".

The present invention permits the fabrication of a hot-electron transistor in which, as illustrated in Figure 7, the base region is a semiconductor region 2 and the barriers are formed in the same semiconductor body. Such hot-electron transistors may have negligible minority carrier storage effects in both emitter and base and therefore be suitable for use at a fast speed or high frequency. They may also have a low base resistance by choosing a high doping concentration of the one conductivity type for the base region 2, and may be relatively insensitive to inhomogeneities in base doping. Therefore such transistors may have significant advantages compared with conventional bipolar transistors of the n-p-n or p-n-p type.

Figure 8 illustrates one specific form of such a hot-electron transistor in accordance with the present invention. The first region 2 has a high doping of one conductivity type (for example n-type) and forms the base region of the transistor. The emitter-base junction is formed with region 2 by barrier-forming means which in the form shown in Figure 8 comprise a Schottky electrode 40 of for example gold or nickel which contacts part of the region 2 to form the Schottky barrier. The base contact is formed by the electrode connection 22 to the region 2. The collector region of the transistor is formed by the second region 3 of the one conductivity type as described previously region 3 may be an epitaxial layer. The collector contact of the transistor shown in Figure 8 contacts the back surface of the highly doped substrate 13 also of the one conductivity type on which the epitaxial layer is provided. A zone 30 of enhanced doping concentration of the one conductivity type may also be included in the collector region 3 adjacent the barrier region 1. The substantially depleted barrier region 1 forms the base-collector barrier of the transistor.

During operation, the emitter electrode 40 is biased negatively with respect to the n-type base 2 which is itself biased negatively with respect to the collector electrode 23. The base and collector electrode connections 22 and 23 serve for applying the reverse bias voltage across the substantially-depleted barrier region 1. The emitter and collector electrodes define the main current path in the device which extends through the first region 2 and the barrier region 1 to the second region 3. As indicated in Figure 8, an a.c. input signal can be applied between the emitter and base electrodes 40 and 22, and an amplified output signal can be derived across a load R between the base and collector electrodes 22 and 23.

In a presently preferred form, the doping concentration of said first (base) region 2 below said Schottky electrode 40 has a maximum value spaced from the surface. This can be achieved by using higher ion energies for the implants. With reverse-bias conditions such a spacing introduces a potential drop between the emitter and the undepleted portion of base region 2 so that the potential of the collector barrier region 1 is shifted to lower potentials with respect to the emitter as reverse bias is increased. In this way an energy distribution is obtained which aids collector efficiency at the barrier region 1. Such a spacing is indicated in Figure 7 by the n and n+ symbols in region 2. The zone 30 of higher doping concentration locally provided in the bulk of region 3 is also indicated in Figure 7 by the n and n(-) symbols in region 3, the n(-) symbol representing the bulk doping of region 3. This locally provided zone 30 also aids collector efficiency in a manner similar to that previously described with reference to Figure 6.

Figure 9 illustrates part of an integrated circuit comprising a hot-electron transistor in accordance with the present invention. In this example, the second region 3 is formed by an island part of an epitaxial layer which is of the one conductivity type (for example n-type) and is present on a substrate 13 of the opposite conductivity type. The island 3 is electrically isolated in known manner from other island parts 53 of the epitaxial layer by the p-n junction 50 between the islands and the substrate 13 and by isolation walls 51 which laterally bound the islands. As is known in the integrated circuit art, such isolation walls may be formed by for example diffusion of dopant of the opposite conductivity type locally through the epitaxial layer thickness and/or by insulating material which may be provided by, for example, local oxidation of the epitaxial layer. After forming the separate islands the hot-electron transistor is formed in island 3, and other circuit elements are formed in the other islands 53. The various circuit elements are connected in the same integrated circuit by means of the electrode connections at the surface of the epitaxial layer. The circuit may be for example a logic circuit.

In the Figure 9 embodiment, the collector electrode connection 23 of the transistor contacts the surface of the island part 3. In order to reduce the collector series resistance a more-highly doped surface contact zone 54 and buried layer 55 both of the one conductivity type may be provided in known manner, as shown in Figure 9.

The hot-electron transistor in Figure 9 also differs from that in Figure 8 in that a plurality of emitter-base barriers are formed with said first region 2, so reducing the base resistance.

This multi-emitter structure is achieved by a plurality of Schottky contacts 40 which may be for example interdigitated with a plurality of base contacts 22.

As previously described, an annular zone 24 of a hot-electron transistor in accordance with the present invention need not have a different depth and doping to that of the substantially depleted barrier region 1, but may be formed during the doping step used to form the barrier region 1.

Figure 10 is the potential diagram of a further hot-electron transistor in accordance with the present invention. Instead of a Schottky electrode, this transistor has a third region 60 which is of the same one conductivity type as region 2 (for example n-type) and forms the emitter of the transistor. Region 60 is separated from the underlying first region 2 by a barrier region 61 which forms the emitter-base junction. This emitter-base barrier region 61 is a semiconductor region having an impurity concentration characteristic of the opposite conductivity type which determines the electrical properties of said barrier region so as to provide potential barriers to the flow of charge carriers of the one conductivity type from both the first and third regions 2 and 60 and to form depletion layers at zero bias with both the first and third regions 2 and 60. The emitter-base barrier region 61 is sufficiently thin that said depletion layers formed at zero bias with both said first and third regions 2 and 60 merge together in said barrier region 61 to substantially deplete at zero bias the whole of said barrier region 61 of mobile charge carriers of both said one and opposite conductivity types. Thus such a transistor has substantially depleted barrier regions 61 and 1 forming both the emitter-base and collector-base barriers, and the emitter, base and collector regions 60, 2 and 3 are all of the same conductivity type. The regions 61 and 60 may of course be formed by ion implantation.

The manner of manufacture for specific forms of hot-electron transistors of the types illustrated in Figures 7 to 10 and in particular the dopants, doping concentrations and thicknesses of their barrier region 1 and first and second regions 2 and 3 can be similar to those described for the diode structures of Figures 3 to 6. Thus, for example, a typical conductivity type determining doping concentration for the base region 2 is at least 1019 dopant atoms/cm3, which results from implanting at least 1013 dopant ions/cm2 over a thickness of approximately 100 . The electrode 22 of the device of Figure 4 may be apertured and the devices of both Figures 4 and 6 may include a Schottky contact to the region 2 within the aperture in the electrode 22, thereby converting these structures into hot-electron transistors.

It will be appreciated that hot-electron transistors in accordance with the present invention may be formed and used in an inverted sense so that the first and second regions 2 and 3 form respectively the base and emitter regions, and the substantially depleted barrier region 1 therebetween forms the emitter-base barrier.

It will be evident that many more modifications and applications are possible within the scope of the present invention. Although ion implantation has been mentioned as particularly convenient for forming the narrow substantially depleted barrier region 1 and, for example, the highly doped first region 2, other known techniques are also possible.

Thus, for example molecular beam epitaxy would be suitable for forming such thin doped regions with for example a III-V semiconductor material such as gallium arsenide. The lateral dimensions of regions grown by molecular beam epitaxy may be defined by subsequent localised processing, for example localised etch removal, localised overdoping, or the formation of semi-insulating zones using localised proton bombardment.

It will be evident that devices with opposite conductivity types can be provided in accordance with the invention. Thus, for example the first and second regions 2 and 3 may be p-type and the impurity concentration of the barrier region 1 may be formed by donor levels. It will also be evident that electrodes which serve for applying a bias voltage across the barrier region 1 between the first and second regions 2 and 3 and for defining in a semiconductor device a current path which extends between the first and second regions 2 and 3 through the barrier region 1 need not directly contact the regions 2 and 3 but may be indirectly connected thereto via further semiconductor regions or even further circuit elements of the device, depending on the particular device structure.

WHAT WE CLAIM IS: 1. A transistor including a base region through which current flow is by hot charge carriers, and barrier-forming means which form with said base region emitter-base and base-collector barriers, the emitter-base barrier or barriers serving for injection of the hot charge carriers into the base region, and the base-collector barrier or barriers serving for collection of said hot charge carriers from the base region, at least one of said barriers being present between the base region and a semiconductor region which is of one conductivity type and which forms an emitter region or a collector region of the transistor, characterized in that said semiconductor region forms part of a semiconductor body in or on which said barrier-forming means are provided, in that another semiconductor region of said one conductivity type is present in said semiconductor body and forms said base region, and in that said hot charge-carriers are majority carriers in said base region.

2. A transistor comprising a semiconductor body including a base region through which current flow is by hot majority charge carriers and barrier-forming means which form with said base region emitter-base and base-collector barriers, said base region being a first semiconductor region of one conductivity type, a second semiconductor region of the one conductivity type forming an emitter region or collector region of the transistor, said base region having a higher doping concentration of the one conductivity type than the second region, one of said barrier-forming means being a semiconductor barrier region which separates the base region from said second region, said barrier region having an impurity concentration characteristic of the opposite conductivity type the magnitude of which determines the height of a potential barrier to the flow of charge carriers of the one

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. conductivity type which determines the electrical properties of said barrier region so as to provide potential barriers to the flow of charge carriers of the one conductivity type from both the first and third regions 2 and 60 and to form depletion layers at zero bias with both the first and third regions 2 and 60. The emitter-base barrier region 61 is sufficiently thin that said depletion layers formed at zero bias with both said first and third regions 2 and 60 merge together in said barrier region 61 to substantially deplete at zero bias the whole of said barrier region 61 of mobile charge carriers of both said one and opposite conductivity types. Thus such a transistor has substantially depleted barrier regions 61 and 1 forming both the emitter-base and collector-base barriers, and the emitter, base and collector regions 60, 2 and 3 are all of the same conductivity type. The regions 61 and 60 may of course be formed by ion implantation. The manner of manufacture for specific forms of hot-electron transistors of the types illustrated in Figures 7 to 10 and in particular the dopants, doping concentrations and thicknesses of their barrier region 1 and first and second regions 2 and 3 can be similar to those described for the diode structures of Figures 3 to 6. Thus, for example, a typical conductivity type determining doping concentration for the base region 2 is at least 1019 dopant atoms/cm3, which results from implanting at least 1013 dopant ions/cm2 over a thickness of approximately 100 . The electrode 22 of the device of Figure 4 may be apertured and the devices of both Figures 4 and 6 may include a Schottky contact to the region 2 within the aperture in the electrode 22, thereby converting these structures into hot-electron transistors. It will be appreciated that hot-electron transistors in accordance with the present invention may be formed and used in an inverted sense so that the first and second regions 2 and 3 form respectively the base and emitter regions, and the substantially depleted barrier region 1 therebetween forms the emitter-base barrier. It will be evident that many more modifications and applications are possible within the scope of the present invention. Although ion implantation has been mentioned as particularly convenient for forming the narrow substantially depleted barrier region 1 and, for example, the highly doped first region 2, other known techniques are also possible. Thus, for example molecular beam epitaxy would be suitable for forming such thin doped regions with for example a III-V semiconductor material such as gallium arsenide. The lateral dimensions of regions grown by molecular beam epitaxy may be defined by subsequent localised processing, for example localised etch removal, localised overdoping, or the formation of semi-insulating zones using localised proton bombardment. It will be evident that devices with opposite conductivity types can be provided in accordance with the invention. Thus, for example the first and second regions 2 and 3 may be p-type and the impurity concentration of the barrier region 1 may be formed by donor levels. It will also be evident that electrodes which serve for applying a bias voltage across the barrier region 1 between the first and second regions 2 and 3 and for defining in a semiconductor device a current path which extends between the first and second regions 2 and 3 through the barrier region 1 need not directly contact the regions 2 and 3 but may be indirectly connected thereto via further semiconductor regions or even further circuit elements of the device, depending on the particular device structure. WHAT WE CLAIM IS:

1. A transistor including a base region through which current flow is by hot charge carriers, and barrier-forming means which form with said base region emitter-base and base-collector barriers, the emitter-base barrier or barriers serving for injection of the hot charge carriers into the base region, and the base-collector barrier or barriers serving for collection of said hot charge carriers from the base region, at least one of said barriers being present between the base region and a semiconductor region which is of one conductivity type and which forms an emitter region or a collector region of the transistor, characterized in that said semiconductor region forms part of a semiconductor body in or on which said barrier-forming means are provided, in that another semiconductor region of said one conductivity type is present in said semiconductor body and forms said base region, and in that said hot charge-carriers are majority carriers in said base region.

conductivity type from both the base region and the second region, which barrier region forms depletion layers at zero bias with both the base region and second region and is sufficiently thin that said depletion layers formed at zero bias together substantially deplete the whole of said barrier region of mobile charge carriers of both said one and opposite conductivity types, the current flow through the barrier region being by charge carriers of said one conductivity type.

3. A transistor as claimed in Claim 2, in which said second region has a higher doping concentration in the depletion layer formed with said barrier region than in the underlying bulk of said second region.

4. A transistor as claimed in Claim 2 or Claim 3, in which said second region is part of an epitaxial layer of one conductivity type which is present on a more highly conductive substrate of the one conductivity type, and an electrode connection to said second region contacts said substrate.

5. A transistor as claimed in Claim 2 or Claim 3, in which said second region is part of an epitaxial layer of one conductivity type which is present on a substrate of the opposite conductivity type, and an electrode connection to said second region contacts the surface of said epitaxial layer.

6. A transistor as claimed in any of Claims 2 to 5, in which the base region adjoins a surface of the semiconductor body and is separated by the barrier region from an underlying semiconductor body portion which comprises the second region.

7. A transistor as claimed in Claim 6, in which the surface-adjoining base region is laterally bounded by an undepleted annular zone of said opposite conductivity type which laterally separates said base region from part of said second region and which extends sufficiently deeply in the body to intersect said barrier region.

8. A transistor as claimed in Claim 7, in which said undepleted annular zone is doped differently from said barrier region.

9. A transistor as claimed in any of Claims 2 to 8, in which the barrier region is a semiconductor region doped with impurity atoms of said opposite conductivity type which form said impurity concentration of said barrier region.

10. A transistor as claimed in any of Claims 2 to 9, in which said impurity concentration of the barrier region is at least two orders of magnitude higher than any impurity concentration of the one conductivity type present therein.

11. A semiconductor device as claimed in any of Claims 2 to 10, in which said second region is a collector region, and a third region of said one conductivity type forms an emitter region of said transistor and is separated from the base region by a semiconductor barrier region which forms the emitter-base barrier, this emitter-base barrier region having an impurity concentration characteristic of said opposite conductivity type which determines the electrical properties of said barrier region so as to provide potential barriers to the flow of charge carriers of the one conductivity type from both the base region and the third region and to form depletion layers at zero bias with both the base region and third region, said emitter-base barrier region being sufficiently thin that said depletion layers formed at zero bias together substantially deplete the whole of said barrier region of mobile charge carriers of both said one and the opposite conductivity types.

12. A transistor as claimed in any of Claims 1 to 10, in which said barrier-forming means which forms the emitter-base barrier comprise a Schottky contact to part of said base region.

13. A transistor as claimed in Claim 12, in which the doping concentration of said base region below said Schottky contact has a maximum value spaced from the surface.

14. A transistor as claimed in any of the preceding Claims, in which a plurality of either emitter-base barriers or collector-base barriers are formed with said base region.

15. A transistor as claimed in any of the preceding Claims, in which said t-.a e region has a conductivity type determining impurity concentration of at least 1019 c1op--.nt atoms/cm3.

16. A transistor substantially as described with reference to any of Figures 7 to 10 of the accompanying drawings.