GB1572582A

GB1572582A - Circuit and method for digitally measuring signal level of pcm encoded signals

Info

Publication number: GB1572582A
Application number: GB4700/78A
Authority: GB
Original assignee: Northern Telecom Ltd
Current assignee: Nortel Networks Ltd
Priority date: 1977-03-03
Filing date: 1978-02-06
Publication date: 1980-07-30
Also published as: SE7802261L; FR2382807B3; DE2808849C2; DE2808849A1; JPS53109677A; FR2382807A1; JPS6052379B2; NL190462B; NL7801094A; NL190462C; SE435666B; CA1068408A

Description

(54) A CIRCUIT AND METHOD FOR DIGITALLY MEASURING SIGNAL LEVELS OF PCM ENCODED SIGNALS (71) We, NORTHERN TELECOM LIMITED, a Canadian company, of 1600 Dorchester Boulevard, West, Montreal, Quebec, Canada, H3H lR1, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates generally to pulse code modulation (PCM) systems and more particularly to a novel digital circuit for measuring the signal level of a PCM signal.

In conventional communication systems, such as the telephone system, it is usually necessary to determine the signal level on a transmission path as a measure of quality of performance. There are a number of approaches to determining the signal levels. One method consists in transmitting an analogue test signal of predetermined frequency and characteristic from one switching centre to another where the received signal is compared with the transmitted signal and a resulting signal level is determined. Another approach uses a loopback method whereby the test signal is looped back to the originating switching centre where the comparison is made. A variety of well known analogue measuring circuits and techniques have been developed to perform this function.

The communication systems presently being developed use digital encoding techniques such as PCM and time division multiplexing. In these systems the information appearing on both the switching and transmission paths is in digital form. However, the requirement of measuring the level of the signals on these paths is still present. Since the known measuring circuits and devices use analogue techniques, it is necessary to convert the digital signals into their analogue equivalent in order to measure the signal level thereof. This technique, although workable, is awkward, fairly complex and tends to be prohibitively expensive due to the necessity of providing highly accurate digital to analogue conversion equipment specifically for this purpose.

The invention provides a circuit for the direct digital measurement of signal levels of - a PCM encoded signal, thereby obviating the necessity of providing digital to analogue conversion equipment for that purpose. In the context of this application the "signal level of a PCM signal" should be taken to mean the signal level of an analogue signal into which this PCM signal would be decoded using a reference analogue to digital converter. In ad dition, the circuit of the invention may be implemented with a relatively small number of off-the-shelf integrated circuit components.

In accordance with the invention there is provided a digital circuit for measuring the level of a PCM signal representing an analogue signal and encoded in accordance with a pre determined companding law comprising a selector means having positions O-n for selec ting integers between 0 and n; a sampling cir cuit for successively sampling the input PCM signal 2n timers, n being determined by the selector means; means for converting each of the coded samples to its normalized power representation and for computing the average power of the samples; and means for deter mining the signal level equivalent of said average power in a conventional dBmO repre sentation of power levels.

Also in accordance with the invention, there is provided a method for measuring the signal level of a PCM signal using the digital measuring circuit of the invention.

The unit dBm is used for the expression of power levels in decibels with reference to a power of one milliwatt (0.001 watt). The decibel is ten times the logarithm to the base 10 of the ratio of a measured power P1 and a reference power Pr such that dB = 10 logs0 pt = 10 lOlo 001awtatts P. watts dBmO is Pr - g10 001 watts The units dBmO is as above but it defines an arbitrary zero point. By international recommendation, the zero point of a PCM signal representing a 1 KlIz tone is defined as being comprised of the following samples (mu -256 companding code): +97, +116, +116, +97, -97,-116, -116, -97.

An example embodiment of the invention will now be described in conjunction with the drawings in which: Figure 1 is a block diagram of a portion of a PCM telephone switching system; Figure 2 is a block-schematic diagram of a digital measurement circuit in accordance with the invention; Figure 3 is a functional sequence diagram of the circuit of figure 2.

The block diagram of figure 1 illustrates a use for the circuit of the invention in a PCM telephone switching system. There is shown a digital switching network 11 having input ports for connection to a codec 12 which contains analogue to digital and digital to analogue conversion circuitry; the codec in turn being connected to an analogue transmission facility 13.

The digital switching network 11 is also provided with an output port connected to a PCM signal measurement circuit 14 which has an output terminal for transmitting resultant level information to a central processor 15.

The circuit of figure 1 portrays the use of the digital circuit 14 for the measurement of a PCM signal in the determination of the characteristics of analogue interface sub-systems from analogue to digital and digital to analogue points in digital switching systems.

The central processor 1 5 selects the facility to be tested. In the case of the codec 12, and the analogue facility 13, the central processor 15 causes the digital switching network 11 to provide a digital connection or path from the codec 12 to the PCM signal measurement circuit 14. Since the digital path through the switching network 11 passes PCM signals essentially unchanged, the coded 12 is in effect connected directly to the measurement circuit 14. In operation, a test signal may originate at a distant switching network and be transmitted along the analogue facility 13. The signal is converted from analogue to digital format in the AID portion of the codec 12 and then sent through the digital switching network 11 to the PCM signal measurement circuit 14 which measures the level of the signal.The resultant information may be displayed on a visual display or sent to the central processor 15 for further processing.

The process is similar to that above if just the codec 12 is to be tested, except that the test tone originates from the digital tone generator 16 and that the analogue facility 13 is looped back on itself. As is conventional in the art, the central processor 15 is adapted to provide the necessary control signals to the circuits of the system.

Figure 2 is a block-schematic diagram of a PCM signal level measurement circuit such as may be used in the system of figure 1. A sampling circuit 100 is shown as having an input terminal for receiving a serial PCM input signal. The sampling circuit 100 may consist of a commercially available shift register adapted to perform serial to parallel conversion of data and an output register. Its output terminal is connected to a memory means 101 which may conveniently be a read-only-memory (ROM).The memory means 101 accepts an input signal W consisting of eight bits, seven quantity bits plus a sign bit and provides an output signal of 12 bits divided into a seven bit mantissa signal Ao and a five bit exponent signal A1. The sign bit connection may be omitted if the PCM-code format is of the sign and magnitude type where equal valued positive and negative samples differ only in the sign bit. These signals constitute the square of the linear representation of the instantaneous power of the input signal W.

The output terminals of the memory means 101 are connected to an accumulator 102 having two input terminals. The accumulator 102 consists of a parallel to serial shift register 103, a single stage synchronous counter 104, a one bit adder 105, and a 48 bit shift register 106.

The output signal Ao from the memory means 101 is converted from parallel to serial format in the shift register 103 and the output terminal thereof is connected to the one bit adder 105. The output signal Al from the memory means is provided to the counter 104 which counts the value of the signal A1 and produces an output pulse E which enables shift register 103 to send a signal S1 to the one bit adder 105.The one bit adder 105 is responsive to inputs from the 48 bit shift register 106 and signal Si from the parallel to serial shift register 103 for allowing the 48 bit shift register to be incremented by the value of the signal Si. The serial output signal B1 from the one bit adder 104 is also the serial output signal B1 of the accumulator 102. The 48 bit shift register is responsive to the signal B1 for producing a parallel output signal B0 which is also the parallel output signal Bo of the accumulator 102.

The counter 104 is responsive to signal A1 for producing an enable signal after a predetermined count corresponding to the value of the exponent as represented by the signal A1. The parallel to serial shift register 103 converts the signal Ao from its parallel format to serial format. The serial format output signal Sl is inhibited until the enable signal E is provided by the counter 104. The serial output signal Sl of the parallel to serial shift register 103 is provided to the adder 105 where it is added bit by bit to the contents stored in the 48 bit shift register 106. The addition of a sample to the accumulated partial sum takes place during a 48 bit shift of the 48 bit shift register. The delay introduced by counter 104 allows the new sample to be added tp the partial sum in the 48 bit shift register with the proper significance.

A selector circuit 109 determines n which defines the number of samples 2n. The output signal n is provided to the control circuit 115 for causing it to generate the necessary control signals and to the adder circuit 108 which adds the signal to counter 107 thereby presenting the counter with the value n. The counter 107 is also responsive to signal B1 and provides an output signal C1.

A shift register 110 acts as an output buffer for the 48 bit shift register 106. Connected to the output terminal of the shift register 110 is a second memory means 111. The output signal CO of the memory means 111 and the output signal C1 of the counter 107 are provided to a multiplication circuit 112 (described further below). Output terminals of the multiplication circuit 112 are connected to a memory means 113 which functions as a binary code to BCD converter. Memory means 111 and 113 may conveniently be read-onlymemories. The output signal D from the multiplication circuit 112 consists of a fractional component Do in a seven bit binary format and as integer component Dl in a seven bit binary format plus one sign bit.The signals are converted to BCD format in the memory 113 wherein each memory location contains the BCD representation of its respective address, each of the addresses corresponding to a possible one value of the D signal. The output terminal of the BCD converter may be connected to a visual display 114 or to a central processor 15 as shown in figure 1.

The control circuit 115 is responsive to an external sync signal from the central processor and to the signal n for providing the necessary control signals. The control circuit has 4 outputs, two clock signals, clock 1 and clock 2, display load and accumulator clear. Clock 2 signal runs 48 times as fast as clock 1 and is used for the timing needed in the accumulator 102. Clock 1 starts the sampling process in sampling circuit 100. The display load enables the memory 113 to provide an output signal to the display 114 after 2n samples.

Description of Operation The operation of the circuit of figure 2 will now be described in conjunction with the functional sequence diagram of figure 3.

As described earlier, the circuit samples a PCM channel on which there is a PCM signal representing an analogue signal. The test tone that defines OdBmO consists of the sequence of the following code samples of a 1 KHz signal: +97,+116,+116,+97,-97,-116,-116,-97 The number of samples 2n, designated as N, may be varied from 2" to 215 (1-32768) in steps of factors of two, and the corresponding integration time varies from .125 msec to 4sec.

The value of n is selectable by the selector circuit 109 which has positions 0-15.

An 8 bit serial sample is acquired by sampling circuit 100 from the serial PCM stream and converted to its parallel form W. The value of W is converted by the memory means 101 to a 12 bit work denoting normalized power such that

where Ao = 7 bit fraction, nominal range 64 to 127 Al = 5 bit exponent, range 0-24 K = 0.37012, a constant derived to facili- tate later conversion to dBm.

W = PCM code sample range 0 + 8031 Y = decoded value of the PCM code sample W Y is not seen as a signal due to the way memory means 101 operates. Y and W are related through the ,u-256 companding law.

CCITT Recommendation G.711, 1972 revised 1976 gives the elements of the Cl companding law.

The value of the sample W is used as the address of the memory means 101 to determine its corresponding normalized power. In this way it is not necessary to have hardware to perform the above calculation for every sample and Y does not exist as a signal. This is made possible by the finite range of values expected.

The accumulated sum of power samples is stored in linear form in the accumulator 102 as described earlier, by the 48 bit shift register 106.

After the power of 2n samples, as determined by the selector circuit 109, has been accumulated, output signal B0 and output signal B1 are available. The total output signal has a resolution of 15 bits, the fraction B0 has 9 bits and the exponent B1 has 6 bits.

The accumulated sum of power is expressed as:

ranges B0 = 256 to 511 B1 = 0-39 The fraction B0 is converted to its log2 representation CO, in the second memory means 111. The integer B1 is modified by subtracting N in the counter 107. This is equivalent to dividing the power sum by 2", to give the average power. A constant of 20 is added in said counter 107 to shift the range of the exponent upwards to facilitate subsequent decoding.The average power is now expressed bv:

and the binary log log B + 256 ranges = CO = 0to255 C1 = 5 to 44 To convert the values of C to dBm, C is multiplied by the constant 10 x logs02 which is 3 very close to 3 + 256 . Multiplication is accomplished in the multiplication circuit 112.

As is well known in the art an implementation of such a multiplier may consist of two parallel adder stages, the first stage forming: C1 = C + where 256 where C = Co + C1 which is obtained by connecting the signal path C to one set of the input terminals of the adder directly and connecting the signal path of C to the second set of input terminals of the adder in such a way that the signal C appears at the said second set of input terminals shifted 8 bits to the left.The output D is obtained by analogously combining C1 and 2C1 in the second adder stage to give: D = Cl + 2C = 3C1 = 3C + 236C = 3C + Th56 C = (3 + 256) x C where D = Do + D1 The resultant power level number (dBm) has a value between 15 and 135 with the foregoing constants having been chosen to result in 128 for OdBmO (i.e. the test tone). Thus by evaluating the result of the multiplication modulo 128 in the multiplication circuit 112 the sign bit is obtained.

The magnitude of the power level in dBmO is available as a 14 bit number with seven fractional bits Do and integer D1 bits are independently converted to Binary Coded Decimal (BCD) using the memory means 113.

The value in BCD has a range of - 99.9 to 6.9 dBmO and may be displayed on the visual digital display means 114 or processed further as mentioned above.

WHAT WE CLAIM IS: 1. A digital circuit for measuring the level of a PCM signal representing an analogue signal and encoded in accordance with a predetermined companding law, comprising: a selector means having positions O-n; a sampling circuit for successively sampling the PCM signal 2n times, n being determined by the selector means; means for converting each of the samples to its normalized power representation; means for computing the average power of the samples; and means for determining the signal level equivalent of the average power in conventional dBmO unit representation of power levels.

2. A digital circuit as defined in claim 1 wherein the converting means'is a first memory means wherein each location contains the square of the linear representation of its respective address, each of the addresses corresponding to a possible one of the coded samples.

3. A digital circuit as defined in claim 2 wherein the computing means comprises: an accumulator circuit responsive to the output signals from the first memory means and to clock signals from a control circuit for producing first and second output signals, the first output signal being a parallel data word consisting of the eight most significant bits of the accumulated sum of the normalized power of the samples, and the second output signal being a data word representing the position of the most significant one of the accumulated sum, a second memory means having a plurality of storage locations each containing the log2 value of its respective address, each of the addresses corresponding to a possible one of the first signals; means for addressing the second memory means at the address defined by the first signal; and circuit means for producing a third output signal representing the exponent value of the average normalized power of the samples.

4. A digital circuit as defined in claim 3 wherein the circuit means comprises, a counter circuit responsive to the second signal for producing the third output signal corresponding to the exponent value thereof on the basis of the value of the most significant bit of the second output signal and the counter means also being responsive to a signal from the selector means for subtracting the value of n from the third signal, whereby the third signal represents the average normalized power of the samples.

5. A digital circuit as defined in claim 3 wherein the accumulator circuit comprises: a counter circuit responsive to the exponent portion of the output signal from the first memory means for providing an enable signal after a predetermined count as determined by the exponent portion; a parallel to serial shift register adapted to be loaded with the mantissa portion of the output signal from the first memory means, and responsive to the enable signal for providing a serial output signal of its contents; a shift register and an adder circuit for determining the accumulated sum of the mantissa portions of said n samples.

6. A digital circuit as defined in claim 4 wherein the means for determining the signal level equivalent of the average power is a pair of multiplication circuits, one for providing the product of the third output signal and a conversion constant, and the other for providing the product of the output signal from the second memory means and the conversion constant.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

To convert the values of C to dBm, C is multiplied by the constant 10 x logs02 which is

3 very close to 3 + 256 . Multiplication is accomplished in the multiplication circuit 112.

As is well known in the art an implementation of such a multiplier may consist of two parallel adder stages, the first stage forming: C1 = C + where

256 where C = Co + C1 which is obtained by connecting the signal path C to one set of the input terminals of the adder directly and connecting the signal path of C to the second set of input terminals of the adder in such a way that the signal C appears at the said second set of input terminals shifted 8 bits to the left.The output D is obtained by analogously combining C1 and 2C1 in the second adder stage to give: D = Cl + 2C = 3C1 = 3C + 236C = 3C + Th56 C = (3 + 256) x C where D = Do + D1 The resultant power level number (dBm) has a value between 15 and 135 with the foregoing constants having been chosen to result in 128 for OdBmO (i.e. the test tone). Thus by evaluating the result of the multiplication modulo 128 in the multiplication circuit 112 the sign bit is obtained.

The magnitude of the power level in dBmO is available as a 14 bit number with seven fractional bits Do and integer D1 bits are independently converted to Binary Coded Decimal (BCD) using the memory means 113.

The value in BCD has a range of - 99.9 to 6.9 dBmO and may be displayed on the visual digital display means 114 or processed further as mentioned above.

WHAT WE CLAIM IS: 1. A digital circuit for measuring the level of a PCM signal representing an analogue signal and encoded in accordance with a predetermined companding law, comprising: a selector means having positions O-n; a sampling circuit for successively sampling the PCM signal 2n times, n being determined by the selector means; means for converting each of the samples to its normalized power representation; means for computing the average power of the samples; and means for determining the signal level equivalent of the average power in conventional dBmO unit representation of power levels.
2. A digital circuit as defined in claim 1 wherein the converting means'is a first memory means wherein each location contains the square of the linear representation of its respective address, each of the addresses corresponding to a possible one of the coded samples.
3. A digital circuit as defined in claim 2 wherein the computing means comprises: an accumulator circuit responsive to the output signals from the first memory means and to clock signals from a control circuit for producing first and second output signals, the first output signal being a parallel data word consisting of the eight most significant bits of the accumulated sum of the normalized power of the samples, and the second output signal being a data word representing the position of the most significant one of the accumulated sum, a second memory means having a plurality of storage locations each containing the log2 value of its respective address, each of the addresses corresponding to a possible one of the first signals; means for addressing the second memory means at the address defined by the first signal; and circuit means for producing a third output signal representing the exponent value of the average normalized power of the samples.
4. A digital circuit as defined in claim 3 wherein the circuit means comprises, a counter circuit responsive to the second signal for producing the third output signal corresponding to the exponent value thereof on the basis of the value of the most significant bit of the second output signal and the counter means also being responsive to a signal from the selector means for subtracting the value of n from the third signal, whereby the third signal represents the average normalized power of the samples.
5. A digital circuit as defined in claim 3 wherein the accumulator circuit comprises: a counter circuit responsive to the exponent portion of the output signal from the first memory means for providing an enable signal after a predetermined count as determined by the exponent portion; a parallel to serial shift register adapted to be loaded with the mantissa portion of the output signal from the first memory means, and responsive to the enable signal for providing a serial output signal of its contents; a shift register and an adder circuit for determining the accumulated sum of the mantissa portions of said n samples.
6. A digital circuit as defined in claim 4 wherein the means for determining the signal level equivalent of the average power is a pair of multiplication circuits, one for providing the product of the third output signal and a conversion constant, and the other for providing the product of the output signal from the second memory means and the conversion constant.
7. A digital circuit as defined in claim 6 and

further comprising a converter circuit for combining and converting the output signals from the multiplication circuits into the binary coded decimal equivalent and a visual display means for viewing the output signal thereof.
8. A method for measuring the signal level of an analogue signal represented by a PCM signal representing a predetermined frequency and encoded in accordance with a predetermined companding law, comprising the steps of: successively sampling the PCM signal 2n times, n being determined by a selector means having positions O-n; converting each of the samples to their normalized power representation; computing the average power of the samples; and converting the value of the average power into its signal level equivalent in the conventional dBmO unit representation of power levels.
9. A method as defined in claim 8 wherein the steps of computing the average power of the samples comprises the steps of: accumulating a total sum of the normalized power representations of the samples; and dividing the total sum of the normalized power representation of the samples by the number of samples to obtain an average normalized power of the samples.
10. A method as defined in claim 9, wherein the step of accumulating the total sum of the normalized power representation of the samples comprises the steps of: serializing the normalized power representations of the samples to obtain a serial format; and adding the serial format bit by bit to a partial sum of all previous serial format representations of the normalized power representation of said 2n samples to obtain the total sum of the normalized power representations of said 2n samples.
11. A digital circuit for measuring the level of a PCM signal substantially as described herein in conjunction with the accompanying drawings.
12. A method for measuring the signal level of an analogue signal represented by a PCM signal substantially as described herein in conjunction with the accompanying drawings.