GB1572419A - Data processing system - Google Patents

Description

(54) DATA PROCESSING SYSTEM (71) We, SIEMENS AKTIEN GESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to data processing and in particular to data processing apparatus having a multi-processor structure.

Conventional data processing systems having a uni-processor consist fundamentally of a central unit and peripheral devices, such as secondary stores and input/output devices. The central unit comprises a working store for system data and up to date programme data, and processing devices such as for example a central processor. The latter can, in earlier data processing systems, itself execute all control and calculating functions or can transfer various functions, such as, e.g. input/output procedures, to specialised processors. A typical data processing system of this type comprises one single processor for the actual programme processing, which in current multi-programme operation, processes the running operations quasi-simultaneously, i.e. in t.d.m. These processes are for this purpose artificially divided into small sub-components and classified in accordance with priorities. Apart from the store accesses which are to be coordinated, in specialised processors specific routines also assigned to other processors can run more or less independently.

At first glance a system structure of this type also appears to best comply with the technological development which has led to the initially relatively expensive processors having become to a considerable extent more rapid and efficient than the peripheral devices and the working store. In fact, a high- speed, efficient central processor appears to be sufficiently employed only in a data processing system having a plurality of peripheral devices in combination with a complicated operating system in the multi-programme operation. Apart from the degree of availability which is decisively governed by the freedom from faults of the central processor, a system structure of this type is subject to limitations in situations in which the central processor becomes increasingly occupied by the operating system itself in order to organise and coordinate simultaneous operation. Thus, on account of multi-programme operation, currently multi-stage working store systems of large capacity are already in use in average power data processing systems in order to ensure average store accesses of sufficient speed. Here the storage position administration necessitates a considerable outlay in the operating system, in particular in the case of indirect addressing mechanisms featuring additional address translation.

However, technological development in the field of cost-favourable circuitry and storage techniques has also led to other system structures, the multi-processor systems. Although proposals had already been made in the past along these lines, a decisive part was played by the fact that for some time cost-favourable micro-processors, albeit of relatively simple construction, have been available which were in fact drawn up so as to be already micro-programmable.

A review of multi-processor systems of this type is given for example in the article 'Performance and Control of Multiple Microprocessor Systems' in Computer Design, March 1974, page 81 ff, in which it is observed that the properties of the micro-processors, due to their technical construction and the technology employed, are governed by the system power rather than the store. Therefore, it is expedient for a plurality of micro processors to participate in one store. The general structure of a multi-processor system of this type therefore frequently provides a system bus line to which all the micro-processors on the one hand and the working store and secondary store, and an input/output system on the other hand are connected in parallel. Another possibility consists of connecting the system units via a switching network which, in contrast to the purely sequential mode of operation of a multiprocessor system having a unibus structure, facilitates simultaneous accesses to different storage modules so that storage cycles of the processors are less mutually disturbing. This structure, which is more efficient in respect of the system powder, requires a more considerable technological outlay as the switching network must connect a plurality of data channels of adequate data width to one another.

The system in question can either be a symmetrical system in which all the processors must be handled identically in respect of processing functions, or can be an asymmetrical system in which each processor specialises in a specific sub-function. The latter system can be quite expedient in data Processing systems provided for special functions when frequently recurring, similar sub-functions are executed by adapted, thus efficient and yet relatively simple processors.

However, this specialisation is less suitable for commercial data processing systems as then it is necessary to constantly redistribute different processes between a plurality of processors so that the associated data exchange becomes considerable in relation to the actual processing efficiency which further drops as a result of an unequal loading of the individual processors. In addition, the structure is liable to interference as one single disturbed processor is sufficient to cause a breakdown of the entire system if no redundancy is provided.

This redundancy is an inherent feature of symmetrical systems as every processor must be capable of assuming any function.

However, the operating system which serves for example to distribute the running processes between the individual processors tends to be more complex and hence more expensive. Here an important role is played by the assignment of a storage location of a modular working store to the current processes; i.e. those which are to be currently processed in the processors. In data processing systems having indirect addressing, further operating system capability is used for address translation. Thus it will readily be seen that via the internal data- and controllines of a data processing system of this type there run a plurality of processes which require an expensive priority control unit to prevent the system from blocking itself.

According to the present invention there is provided a data processing apparatus having a multi-processor structure, the apparatus comprising a common secondary store, a first bus line, one or more second bus lines, and a plurality of system units each including an operating processor and a respective store module directly linked thereto, in which the plurality of system units includes at least one main system unit connected to the first bus line and to the common secondary store and arranged, in operation, to control data transfer between the secondary store and the first bus line, a plurality of branch system units each connected to the first bus line and to the or a said second bus line, and a plurality of base system units each connected to the or a said second bus line, wherein the branch system units execute control functions for the base system units and the base system units are interchangeable with each other with respect to their processing functions during programme execution, and in which each system unit further includes a connection processor arranged, upon receipt of instructions from the operating processor of the unit, to establish and control, independently of the operating processor, data transfer across the bus line(s) to which the unit is connected.

Thus this realisation provides a multiprocessor system which is classified hierarchically and is of modular construction. In the lowest level, the actual process processing can be carried out purely locally, in contrast to uni-processor systems having a multi-stage working store system in which process data must be constantly transferred back and forth between the individual store hierarchies. The conventional pseudo-simultaneous operation of uni-processor systems is replaced by genuine parallel operation in the various base processors. It will be appreciated that the system, being arranged hierarchically, is not truly symmetrical, but that the base system units together constitute a symmetrical subsystem.

Micro-processors are of simple construction and relatively slow, and yet are costfavourable. Therefore, on account of the parallel operation, genuine multi-operation in the base processors is aimed at only to a limited extent and therefore the operating system for a data processing installation of this type becomes simpler than for example conventional subscriber operating systems.

The hierarchical structure permits the operating system routines to be advantageously distributed between the individual levels. The base processors themselves can be arranged to execute only operating system routines which are directly linked with the operation processing, such as, e.g. programme interruptions and activities for the execution of operation changes. Furthermore, they will normally undertake storage location administration only in their own storage module of the system unit.

In order to ensure that the system can be developed without reducing the system performance, the main processor is fundamentally only required to coordinate the accesses to the secondary store and to attend to the administration of operations, i.e. to catalogue the individual jobs taking place in the system and to distribute these between the processing base processors.

The remaining operating system routines are preferably undertaken by the branch processors. These routines comprise in particular the activation and deactivation of the assigned base processors. This area of functions can also comprise the possibility of loading the base processors with specific micro-programmes.

Preferably the operating processors are all of similar construction. Thus a modular, universal data processing installation can be constructed with only a few different, very highly integrated modules, i.e. microprocessors, bus line modules and storage modules and a simple, but nevertheless comfortable operating system. Similarly, the connection processors can conveniently be of similar construction to one another.

The above described processor functions in the individual hierarchy stages of the system indicate that in particular the branch processors are preferably mainly occupied with functions of data exchange with the main processor on the one hand and the connected base processors on the other hand.

The connecting processor can be of simpler construction than an operating processor and does not necessarily require to be micro-programmable as it attends to only one single function, the organisation of the data exchange via the connected bus lines.

The operating processor to which it is spatially firmly coupled is then freed of this function and can carry out a new request in parallel. Thus it is able to operate a larger number of subordinate operating processors and to attend to operating system routines on a larger scale.

In another aspect of the invention there is provided a data processing apparatus of the type described above when programmed such that the storage modules of the base system units contain microprogramme routines for executing a set of desired commands, that microprogramme routines for executing certain further commands are available in the branch system units, and that a base system unit operating processor, upon receipt of such a further command assumes a programme interruption state. Preferably the apparatus is also programmed such that, in the programme interruption state consequent upon receipt of a said further command, a base system unit operating processor feeds to a branch system unit a request signal for the required micro-programme routine and the latter is subsequently transferred page-wise into the requesting base system unit, and that then the command which has occasioned the programme interruption is processed therein by the operating processor of the base system unit.

If desired the apparatus may be programmed such that at the end of an operation and on the initiation of a command a base system unit operating processor firstly decodes said command to establish whether it is one of said further commands, and if it is, the base system unit operating processor assumes the programme interruption state and requires a branch system unit operating processor to handle the awaiting command itself and transfer the result into the requesting base system unit operating processor so that the latter can proceed with the processing of the operation.

An exemplary embodiment of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block circuit diagram of a data processing installation without connection processors; Figure 2 is a block circuit diagram of a data processing installation according to the invention; and Figure 3 is a block circuit diagram of a possible embodiment of a connection processor.

The data processing installation schematically illustrated in Figure 1 is constructed in purely modular fashion from a plurality of system units SU. Each system unit is to be united on a plug-in board and to contain, in addition to a storage module SM, an operating processor SP, ZP or BP. The operating processors which here have been shown merely schematically represent micro-processors which can be controlled by micro-programmes and employ the assigned storage module SM as working store.

The system units SU are arranged in hierarchical fashion. The lowest level is formed by the system units SU with operating processors referred to as base processors BP for the parallel processing of running processes. These are combined in groups with peripheral units PE and connected via base bus lines BB (only one of which is shown in Figure 1) to one of the system units SU of the central level. The operating processors of this level, referred to as branch processors ZP, are commonly connected via a branch bus line ZB to the main system unit SU of the highest hierarchy level. The latter contains an operating processor which is referred to as main processor SP and to which is connected the common data base of the system, a secondary store SSP of large storage capacity. Thus the data processing installation consists of a few standardised units, namely operating processors SP, ZP and BP each of which, together with a respective storage module SM, forms a system unit SU, and bus line modules ZB and BB for the data traffic between the system units.

The described structure means that the programme processing is carried out locally in base system units SU of the lower level and to this end the required programme data of a process are contained in the relevant storage module SM. In the system units at the most a few Processes are to take place simultan eous in order that every process instruction is carried out if possible without process changes.

The operating processors are relatively simply constructed micro-processors, and therefore cheap. Consequently it is possible to dispense with optimising the operating system of the data processing installation in such manner that all the system units of the processing level are constantly occupied. In spite of the fact that the operating system is convenient for the user, it is relatively simple, in particular as the components thereof are distributed between the operating processors of the various levels. The base processors BP undertake only the routines for the actual execution of operations, such as the processing of programme interruptions, programme change routines and the storage location administration in the connected storage module SM. This means, in particular, the replacement of storage pages no longer required in a process sequence and, in the case of a page fault, thus a storage page which has not been loaded during a process sequence in the storage module SM, the call-up of the required storage zone from the secondary store SSP.

The other operating system routines are handled by the operating processors of higher hierarchical stages. The main processor SP which is directly connected to the secondary store SSP can, however, in addition to the organisation of the access to the secondary store SSP only attend to other operating system routines to a limited extent iitis not to become overloaded, and thus the system is not to become blocked. However, accesses of this kind to the secondary store SSP are frequently required. They occur during the intermittent running and interruption of processes in the base processors BP following the completion of an instruction and in the case of all page faults. Therefore in more extensive systems, the main processor SP can attend only to the administration of the functions currently waiting in the data processing installation, i.e. can only catalogue the processes which are running and are still to be processed, and assign the corresponding programme data to specific storage zones in the secondary store.

The branch processors ZP undertake the remaining functions of the operating system.

In addition to the obvious capacity for processing sub-programme interruptions, they also activate and deactivate the operations in the base processors BP of the connected group of system units SU and control the input/output traffic across the peripheral units PE. There is a large emphasis in particular upon the actual data exchange across the connected bus lines ZB and BB, by which they are then blocked for other requests or, in the case of higher priority requests which necessitate more frequent programme interruptions.

Figure 2 shows a data processing system in accordance with one embodiment of the invention, in which, in order to free the branch processors, these are assigned an additional connection processor, the branch connection processor ZVP spatially directly assigned in the system unit SU, and which independently controls the data exchange.

For reasons of a homogeneous structure, however, all the system units SU then contain a connection processor SVP, ZVP and BVP of this type. This ensures that the principle of modularity is observed. The connection processors are likewise standardised, and thus can be exchanged with one another as modules, but do not require to be identical, in respect of construction, with the operating processors.

Figure 2 also shows a few amendments to the structure explained with reference to Figure 1: thus, by way of an optional extension, broken lines indicate a second system unit arranged in parallel to the first system unit SU with the main processor SP. In the event of a fault in the first system unit, this second system unit can undertake the functions thereof and thus prevent the blockage of the entire data processing system in the event of such a breakdown. Furthermore, it can relieve the first system unit of load, although for this purpose it requires an additional coordination connection, likewise marked in broken lines, between the two main processors SP.

A further measure likewise increases the availability of the system. Each branch connection processor ZVP is connected to a base bus line BB. In Figure 2, bus line switches BS schematically indicate that a system unit SU in the lower plane can be optionally switched through to one of two bus lines BBI BB2. As schematically illustrated, these switches are controlled by control signals which are emitted from the base connection processors BVP.

Finally Figure 2 indicates more clearly that system units are also used as programmable, peripheral control units PS to which, with an appropriate data transfer rate, a plurality of peripheral devices PG can also be connected.

These peripheral control units PS serve not only for data buffering and to match the data transport to different data channels, but also, for example, to recode data, and thus simplify the organisation of the input/output traffic across the peripheral devices PG from the viewpoint of the operating system.

It would appear superfluous to discuss in full detail the data processing installation which has already been explained in respect of its fundamental structures, as microprocessors, storage modules or bus line modules are known as such in respect of their construction. Therefore Figure 3 illustrates merely a possible embodiment for a processor employed as branch connection processor ZVP with reference to a block circuit diagram with the aid of which the cooperation between the various system units of the data processing installation is to be explained in detail.

The illustrated branch connection processor is classified into a programme control unit PST, a request control unit AST and an interface control unit SST. The programme control unit PST is the heart of the connection processor, and the commands which are executed therein control the data transfer, the handling of the data transmission procedures and the cooperation of its individual components.

In the schematic construction of the programme control unit PST, between an input bus line BUS1 and an output bus line BUYS2 there is firstly arranged a set of different registers, e.g. a command counter BZ and a request register AFR, the contents of which start the various procedures in the programme control unit PST. Also provided are operating registers AR which - like the request register AFR - are fundamentally predetermined in respect of their use but in part can also be freely used. The programme control unit PST also contains a calculating unit ALU with two preceding intermediate registers ZW1 and ZW2, both of which are connected to the input bus BUS1, whereas the output of the calculating unit is connected to the output bus BUS2.

As schematically indicated in Figure 3, the two bus lines of the programme control unit PST are connected to different points in the interface control unit SST. The latter represents the input/output interface of the branch connection processor via which it communicates with other processors in the data processing installation. A multiplex channel B-MUX is shown which possesses input/output registers and special control registers (not shown). It should also be considered as a bus line module via which the branch connection processor communicates with the base processors BP on the base bus line BB. A main processor terminal SPA and a branch processor terminal ZPA are constructed in similar fashion as interfaces to the main connection processor SVP and to the branch processor ZP. Finally the branch connection processor SVP can communicate with the storage module SM of its system unit via a store access control unit SZS.

The third control unit of the branch connection processor is the request control unit AST. This internal scanning device is to enable the programme control unit PST to start via the request register AFR in dependence upon various request origins. Requests of different types can be made to the branch connection processor ZVP both from the base processors BP and the main connection processor SVP and also from the branch processor ZP itself. These different types of requests must be recognised and distinguished from one another.

Occurring requests are to this end communicated to the request control unit AST on control lines STL via the individual modules of the interface control unit SST. An instruction, via B-MUX, from a base processor BP sets an assigned bit in a processor request register PAR, whereas requests from the two other processors via ZPA, SZS, each set one of two flip-flops FF1 and FF2. In this way requests from the main connection processor SVP and the branch processor ZP can be differently evaluated and accorded higher priorities.

The parallel bit outputs of the processor request register PAR (via a OR-gate OG) and the two flip-flops FF1 and FF2 (directly) are connected to a priority network PRN. The latter can operate in known manner, e.g.

purely cyclically relative to requests from the base processors BP, but can switch through requests from the main connection processor SVP and the branch processor ZP with priority. As indicated by broken lines, in the event of a line scanning process of this type, the contents of specific line words which define the control states of requesting units can be checked and are stored in the storage module SM or in the units of the interface control unit SST. The result is transferred via a control register SR2 into the request register AFR of the programme control unit PST and thus a specific programme routine is directly started.

A further control register SR1 arranged between the programme control unit PST and the priority network PRN indicates that this scanning process can also be influenced in programmed fashion by the programme control unit PST. Thus, for example, it is possible to stop the scanning cycle until the programme control unit PST is free for a further request. Finally, the request control unit AST also comprises a pulse generator TG which, within the connection processor, forms the central pulse train for the request scanning, but also for the programme control unit PST.

The above indicates that the data exchange within the data processing installationis to take place asynchronously and therefore is to be based upon an acknowledgement system. A request signal is statically held in the requested unit and following the setting up of specific request parameters sends an acknowledgement signal to the requesting unit. The latter subsequently transfers specific control criteria which define in detail the request origin, and which are transferred into the request register, whereupon a request routine, which has thus been established, can commence. At the end of this more or less extensive routine, where it is processed by a connection processor, there in any case occurs a further request, derived therefrom, to a branch processor or to the main connection processor to which the latter react in similar fashion. If the requesting processor is to be freed immediately following the transfer of the request, in a part of the assigned storage module SM reserved for data transfer procedures of this type, request parameters must be traced for example as line words, in order that the result can be clearly assigned to the forwarded request.

Under this condition, when the request parameters are transferred to the requested unit, the requesting unit can already reset the appropriately set request bit in the processor request register PAR and one of the two fli-flops FF1 or FF2.

ln the following we shall consider possible requests: the transfer of a new process into the data processor installation can only be carried out via a peripheral device PG. To this end the latter emits a request signal to its assigned, peripheral control unit PS. With an acknowledgement signal, the peripheral control unit PS requests a terminal signal from the peripheral device PG, receives the latter, decodes it, and transmits it across the chain of connection processors BVP, ZVP, SVP to the main processor SP. The latter classifies such requests into a queue and processes them at the appropriate time. It then transmits an acknowledgement signal in the opposite direction to the requesting, peripheral device PG as a confirmation that the operation or job has been initiated.

The requesting peripheral device PG interprets this acknowledgement signal as a request to load and start the desired programme. Again the main processor SP is requested via the chain of connection processors. The main processor now instigates a process table, and assigns the accepted operation to a branch processor and thus to its sub-system. When the branch processor ZP has been switched on, it classifies the operation into a queue and can activate it when one of the processing system units is free.

In this case the branch processor ZP receives, via the corresponding connection processors BVP and ZVP, a report from a base processor BP that a process can be stopped because this process has been completed or because firstly a slow input/output operation must be carried out. The branch processor ZP receives this message and classifies the assigned operation -- where necessary - into the queue. It directs an operation which is now to be started to the released base processor BP.

This operation will be assumed for example to be that just created. For an operation of this kind, in the secondary store SSP an appropriate storage zone has in fact been prepared by the main processor SP, although the programme data are not yet contained therein, and therefore an input transfer procedure is firstly necessary in order to transfer the operation into the processing system unit. The base processor BP of the processing system unit communicates this fact via the corresponding connection processors, including a branch connection processor ZVP and, in the case of different sub-systems a main connection processor SVP, to the peripheral control unit PS. During the a gramme change, a newly created operation is to be started. If, however, in the event of a programme change in a processing system unit an operation which has already once been stopped in the data processing system is to be re-started, the activated base processor loads the start address of this operation the commencement of the operation. Normally a page fault immediately occurs because the corresponding store page is not loaded in the assigned storage module SM.

If it is assumed that the storage module SM does not have any free page frames available, the base processor BP must release a store page in the storage module SM. This is usually a store page of an interrupted process. The base processor BP then calls up the main processor SP via the chain of connection processors BVP, ZVP, SVP and communicates to the main processor, in response to an acknowledgement signal, that the released store page is to be transferred into the secondary store SSP. As soon as this is possible, the main processor SSP directs its connection processor SVP to carry out the data transfer into the secondary store SSP indicating the appropriate storage zone in the secondary store. In the thus released page frames of the storage module SM of the processing system unit, the store page which was not available for the operation processing can now be transferred from the secondary store SSP in the opposite direction.

Here again the initiative arises from the base processor BP of the processing system unit.

It should have become clear from the above that in this data processing system a data transfer takes place to and from the secondary store SSP only in association with page faults. Thus, to relieve the interface of this store from load, neither at the beginning nor at the end of the operation are programme data explicitly transmitted from the secondary store SSP or into the secondary store.

In addition further requests can occur which will only be referred to briefly here; thus the end of a programme stop is handled similarly to the stopping of an operation. The base processor of the processing system unit communicates this programme end via the connection processors BVP and ZVP to its assigned branch processor ZP in that it transmits an end signal in addition to a stop characteristic.

The branch processor ZP subsequently withdraws this operation from the queue and transmits a corresponding end signal to the main processor SP which cancels the operation.

Furthermore, a running operation can also be interrupted externally. An appropriate request signal from a peripheral device PG is decoded, as interruption signal, by the base processor BP of the peripheral control unit PS. As this base processor BP is unable to immediately establish in which processing system unit the process is being handled, it transmits an interruption signal, together with a terminal signal, to the main processor SP via the corresponding connection processors BVP, ZVP and SVP. The main processor SP handles this request, establishes the branch processor ZP to which it has transferred the associated operation, and forwards the request to the latter. The latter then transfers the request to the base processor BP which is handling this process and in which a programme interruption is triggered.

The above description of the system activities has shown that a large part of the operating system routines is restricted to simple data transmission procedures. On the other hand, the operating system of conventional data processing systems comprising one or several processors and a multi-stage working store system, as is known also has numerous functions of storage location administration and organisation of the multiprogramme operation by time slice formation etc.

These functions of the operating system are substantially reduced by the principle of parallel, local processing of processes employing cost-favourable although relatively slow micro-processors, and spatially linked storage modules, which however are limited in their capacity. This principle also proves particularly interesting because special programme analyses have indicated that in commercial data processing installations comprising a subscriber operating system, most machine commands are required only rarely. It is in fact the simplest machine commands which are used by far the most frequently.

In the case of the limited storage capacity in the storage module SM of a system unit SU it would therefore be inexpedient to store the micro-programme routines for all machine commands entirely in the storage modules SM of the processing system units. Even a limitation to micro-programme routines with which, for example, on average 90% of all run commands must be processed, results in an entirely out-of-proportion reduction in the requisite storage space, as in fact the most rarely employed commands necessitate extensive micro-programme routines for their execution. However, on average in the case of every tenth command of a running operation, the corresponding micro-programme routine is not directly available to the processing base processor BP in the assigned storage module SM, which corresponds to a page fault. There are several possibilities of handling this page fault. The most obvious possibility of handling this fault in the same manner as a page fault in programme data in the above described manner cannot be used simply because the large number of such page faults would block the interface to the secondary store SSP in the main connection processor SVP.

However, the three-stage processor structure permits the main processor SP, or the main connection processor SVP in the case of rarer machine commands, to be bypassed.

As the storage modules of the central level can be employed to a large extent by operating system routines, the second possibility consists of keeping micro-programme routines for rare machine commands therein. This is because even with a relatively low storage capacity of the storage module SM of e.g. 64 kbytes this storage space will be adequate in by far the majority of cases. Only in exceptional cases of a 'genuine' page fault, would a few more, extremely extensive micro-programme routines have to be loaded, page-wise, from the secondary store SSP into the storage module SM assigned to the branch processor ZP.

On the other hand, in the case of a 'nongenuine' page error, the micro-programme routine missing from the base processor BP could be loaded page-wise directly from the storage module SM of the superordinate branch processor. ZP into the storage module SM of the base processor BP.

In addition, a third possibility consists in assigning the processing of a rare command to the branch processor ZP. For example, an appropriate flag bit in the individual machine command can distinguish normal machine commands to be processed by the base processor BP itself from rare machine commands which are then handled by the superordinate branch processor ZP. On the initiation of a machine command, the base processor BP firstly decodes this flag bit, and m dependence thereupon, produces a signal for a temporary programme interruption in the event of a rare command which is interpreted as a request for command processing in the superordinate system unit of the central processing level.

As to which of the two last-mentioned possibilities is to be given preference is dependent upon the system configuration.

The former is consistent with the principle of local processing of processes in the base processors, but increases the number of genuine and non-genuine page faults and thus also increases the number of page fault routines. Otherwise, the loading of the branch processors ZP is increased, so that consequently the groups of processing system units assigned to the latter are limited or it is necessary to accept longer programme interruptions in the base processor.

It should also be added that with an increasing degree of integration of microprocessors, it can be expected that the most frequent micro-programme routines will be able to be accommodated actually on the micro-processor module itself instead of in the storage module. Also in this case, the two above explained possibilities exist. Routines not present in the module can be loaded from the working store, i.e. from the actual storage module or that of the branch processor, or the relevant commands can be transmitted to the branch processor for processing.

WHAT WE CLAIM IS: 1. A data processing apparatus having a multi-processor structure, the apparatus comprising a common secondary store, a first bus line, one or more second bus lines, and a plurality of system units each including an operating processor and a respective store module directly linked thereto, in which the plurality of system units includes at least one main system unit connected to the first bus line and to the common secondary store and arranged, in operation, to control data transfer between the secondary store and the first bus line, a plurality of branch system units each connected to the first bus line and to the or a said second bus line, and a plurality of base system units each connected to the or a said second bus line, wherein the branch system units execute control functions for the base system units and the base system units are interchangeable with each other with respect to their processing functions during programme execution, and in which each system unit further includes a connection processor arranged, upon receipt of instructions from the operating processor of the unit, to establish and control, independently of the operating processor, data transfer across the bus line(s) to which the unit is connected.

2. Data processing apparatus as claimed in claim 1 in which the operating processors are all of similar construction.

3. Data processing apparatus as claimed in claim 1 or 2, in which the connection processors are all of similar construction.

4. Data processing apparatus as claimed in claim 1, 2 or 3, including, as a peripheral control unit for at least one peripheral device, a further base system unit connected to the or a said second bus line for communication with other base system units and at least one branch unit.

5. Data processing apparatus as claimed in any one of the preceding claims, when programmed such that the storage modules of the base system units contain microprogramme routines for executing a set of desired commands, that micro-programme routines for executing certain further commands are available in the branch system units, and that a base system unit operating processor, upon receipt of such a further command, assumes a programme interruption state.

6. Data processing installation as claimed in claim 5, programmed such that, in the programme interruption state consequent

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. the large number of such page faults would block the interface to the secondary store SSP in the main connection processor SVP. However, the three-stage processor structure permits the main processor SP, or the main connection processor SVP in the case of rarer machine commands, to be bypassed. As the storage modules of the central level can be employed to a large extent by operating system routines, the second possibility consists of keeping micro-programme routines for rare machine commands therein. This is because even with a relatively low storage capacity of the storage module SM of e.g. 64 kbytes this storage space will be adequate in by far the majority of cases. Only in exceptional cases of a 'genuine' page fault, would a few more, extremely extensive micro-programme routines have to be loaded, page-wise, from the secondary store SSP into the storage module SM assigned to the branch processor ZP. On the other hand, in the case of a 'nongenuine' page error, the micro-programme routine missing from the base processor BP could be loaded page-wise directly from the storage module SM of the superordinate branch processor. ZP into the storage module SM of the base processor BP. In addition, a third possibility consists in assigning the processing of a rare command to the branch processor ZP. For example, an appropriate flag bit in the individual machine command can distinguish normal machine commands to be processed by the base processor BP itself from rare machine commands which are then handled by the superordinate branch processor ZP. On the initiation of a machine command, the base processor BP firstly decodes this flag bit, and m dependence thereupon, produces a signal for a temporary programme interruption in the event of a rare command which is interpreted as a request for command processing in the superordinate system unit of the central processing level. As to which of the two last-mentioned possibilities is to be given preference is dependent upon the system configuration. The former is consistent with the principle of local processing of processes in the base processors, but increases the number of genuine and non-genuine page faults and thus also increases the number of page fault routines. Otherwise, the loading of the branch processors ZP is increased, so that consequently the groups of processing system units assigned to the latter are limited or it is necessary to accept longer programme interruptions in the base processor. It should also be added that with an increasing degree of integration of microprocessors, it can be expected that the most frequent micro-programme routines will be able to be accommodated actually on the micro-processor module itself instead of in the storage module. Also in this case, the two above explained possibilities exist. Routines not present in the module can be loaded from the working store, i.e. from the actual storage module or that of the branch processor, or the relevant commands can be transmitted to the branch processor for processing. WHAT WE CLAIM IS:

1. A data processing apparatus having a multi-processor structure, the apparatus comprising a common secondary store, a first bus line, one or more second bus lines, and a plurality of system units each including an operating processor and a respective store module directly linked thereto, in which the plurality of system units includes at least one main system unit connected to the first bus line and to the common secondary store and arranged, in operation, to control data transfer between the secondary store and the first bus line, a plurality of branch system units each connected to the first bus line and to the or a said second bus line, and a plurality of base system units each connected to the or a said second bus line, wherein the branch system units execute control functions for the base system units and the base system units are interchangeable with each other with respect to their processing functions during programme execution, and in which each system unit further includes a connection processor arranged, upon receipt of instructions from the operating processor of the unit, to establish and control, independently of the operating processor, data transfer across the bus line(s) to which the unit is connected.

2. Data processing apparatus as claimed in claim 1 in which the operating processors are all of similar construction.

3. Data processing apparatus as claimed in claim 1 or 2, in which the connection processors are all of similar construction.

4. Data processing apparatus as claimed in claim 1, 2 or 3, including, as a peripheral control unit for at least one peripheral device, a further base system unit connected to the or a said second bus line for communication with other base system units and at least one branch unit.

5. Data processing apparatus as claimed in any one of the preceding claims, when programmed such that the storage modules of the base system units contain microprogramme routines for executing a set of desired commands, that micro-programme routines for executing certain further commands are available in the branch system units, and that a base system unit operating processor, upon receipt of such a further command, assumes a programme interruption state.

6. Data processing installation as claimed in claim 5, programmed such that, in the programme interruption state consequent

upon receipt of a said further command, a base system unit operating processor feeds to a branch system unit a request signal for the required micro-programme routine and the latter is subsequently transferred page-wise into the requesting base system unit, and that when the command which has occasioned the programme interruption is processed therein uy the operating processor of the base system unit.

7. Data processing installation as claimed in claim 5, when programmed such that at the end of an operation and on the initiation of a command a base system unit operating processor firstly decodes said command to establish whether it is one of said further commands, and if it is, the base system unit operating processor assumes the programme interruption state and requires a branch system unit operating processor to handle the awaiting command itself and transfer the result into the requesting base system unit operating processor so that the latter can proceed with the processing of the operation.

8. A data processing substantially as herein described with reference to Figures 2 and 3 of the accompanying drawings.