GB1570620A

GB1570620A - Fuel injection systems for internal combustion engines

Info

Publication number: GB1570620A
Application number: GB4781076A
Authority: GB
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1975-11-18
Filing date: 1976-11-17
Publication date: 1980-07-02
Also published as: FR2332434B1; FR2332434A1; DE2551639A1; JPS5263524A

Description

(54) IMPROVEMENTS IN AND RELATING TO FUEL INJECTION SYSTEMS FOR INTERNAL COMBUSTION ENGINES (71) We, ROBERT BoscH GmbH, a German Company of Postfach 50, 7000 Stuttgart 1, Germany, do hereby decalre the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a device for determining the length of injection control signals which are to be supplied to injection valves of an internal combustion engine, the injection time being, among other things, dependent upon the speed, air throughput in the intake manifold and temperature of the engine.

In a known fuel injection system for controlling at least one injection valve in an engine in dependence upon the air throughput, direct voltage signals are formed in a computing circuit which are proportional to the air throughput and to the crank shaft speed. These signals are further processed as analogue signals in direct-voltage amplifier stages. The direct-voltage amplifier stages in such analogue computers must be balanced very precisely so that difficulties may arise concerning their longterm stability.

Furthermore, such analogue computing circuits are sensitive to the influence of interference pulses. This leads to difficulties particularly when such devices are used to operate motor vehicles since interference pulses may arise uncontrollably in these, for example, through the ignition system or direction indicators.

A feature of the invention is to improve such fuel injection systems so that the sensitivity to interference pulses is substantially reduced and correcting processes are no longer required.

In accordance with the present invention there is provided a device for determining the duration of injection control signals which are to be supplied to injection valves of an internal combustion engine, the injection time being dependent inter alia upon the speed, air throughout in the intake manifold and engine temperature, said device having an air quantity meter, which produces a proportional output voltage, a temperature probe for location in the region of the engine, a tachometer, a computing circuit which computes from these data the length of the injection pulses, a first counter, which is arranged to be supplied during a predetermined crankshaft angle with a counting frequency (fML) proportional to the air intake quantity per stroke, an analogue-digital transducer, which is regulated by feedback and processes the output voltage of the air quantity meter, a signal whose frequency (fv) is proportional to the engine temperature (v) being supplied to a digital multiplying circuit for joint processing with other operating parameter of the engine to produce an output frequency (fkl), there being associated with the multiplying circuit an addressable memory whose stored data values emitted successively in dependence upon other operating parameters is multiplied with the engine temperature frequency (fv), the arrangement being such that the output frequency (fkl) of the multiplying circuit is supplied to a summing point together with at least one other frequency derived from at least one other operating parameter to form a total correction frequency (fk) and another counter being provided which takes over the content of the first counter and is counted out with the total correction frequency (fk), the length of time from the takeover point to the attainment of a predetermined counter content of the other counter being a measure of the length of the injection duration (te).

The invention is therefore concerned with a - digital computing circuit for determining the injection time of injection control signals which are to be supplied to at least one injection valve in an engine, the circuit being acted upon on the input side basically by analogue signals which are derived from the operating behaviour of the engine.

Since such digital computing circuits may be operated at extremely high frequencies in a very rapid cyclical sequence, the maximum number of faults which may be produced even in the presence of very frequent interference pulses is negligible; it is also particularly advantageous that, when constructing a digital computing circuit for determining the injection time in a fuel injection system, basically integrated circuits may be used, it being possible for each motor vehicle to associate different behaviour patterns, for example, in the case of heating up, in the form of a set-value memory with the fuel injection system which depending upon requirements recalls the necessary data from the set-value memory by addressing it. When changing from one motor vehicle to another, all that is then necessary is the exchange and suitable programming of the set-value memory.

The invention is described further hereinafter, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a diagrammatic block diagram of a first embodiment of a digital fuel injection system, wherein the central memory stores data for other individual computers used in a motor vehicle and the access of the individual computers is effected through data lines common to all computers; Fig. 2 illustrates a second embodiment of a digital fuel injection system in which the block diagram of Fig. 1 is shown in greater detail and in which the memory is exclusively associated with the fuel injection system; Fig. 3 illustrates the detailed construction of a multiplying circuit for use in the circuits of Figs. 1 and 2; and Fig. 3a illustrates the dependence of the output frequency fa over input frequency fe in a so-called DDA-multiplier.

The fuel injection system shown in Fig.

1 comprises a main computer 1 having an associated control part ib which may be a divider circuit and is used to adapt the entire system to the available number of cylinders of the associated engine. Connected after the main computer 1 is a voltage correction circuit 2 to which the output pulse sequence of the main computer is suDnlied which basically determines the injection time per stroke by the length of its individual pulses. The voltage correction circuit which is acted upon by the fluctuating supply voltage, processes the pulse sequence te of the main computer supplied to it in such a manner that the influence of possible fluctuations of the power supply upon the onen and closed times of the injection valves is removed.The pulse sequence, corrected in this manner and having pulses of length ti. at the output of the voltage correction circuit 2 then passes through an output state 3 to the inlection valves, which are preferably constructed as electro-magnetic injection valves, so that they open for the time ti and supply a metered fuel quantity to the relevant associated cylinder or the intake manifold, such quantity corresponding to the length of the applied injection control signals.

The main computer 1 is so constructed tthat it has a counter or a register which, during a specific gate time T which is inversely proportional to the engine speed n, counts upwards an air quantity frequency fLM supplied to it or registers in such a way that after the gate time has elapsed a specific counter reading is associated with each frequency supplied to it. In other words, the counter may alternatively be a so-called stochastic counter, this being explained in greater detail later on. After the gate time has elapsed, the counter- or register-reading is counted down at a correction frequency fK also supplied to the main computer 1 until attainment of the initial counter reading at the beginning of the gate time.The time from the beginning of downward counting at the correction frequency until attainment of the pre-determined counter final reading, which in a normal counter or register corresponds to the value 0, is a measure for the effective injection time te.

It may be seen from the diagram of Fig.

1 that three different input values are thereby supplied to the main computer 1, namely the earlier mentioned air quantity frequency fLM, which is preferably produced in a preconnected signal processing or "interface" circuit 4 according to regulating circuit principles from an analogue signal, a correction frequency fK and a speed datum such as a speed frequency fn. The analogue signal for the air quantity frequency fLM may be the output signal of a potentiometer which, depending upon the position of an air meter in the engine intake manifold, preferably alters in proportion to the air quantity passing through the intake manifold. If proportionality cannot be achieved in this manner, specially suited and known correction circuits may be used.

This means that, basically, input signals of an analogue type are supplied to the interface circuit 4 at its input A; the circuit 4 is so constructed that it produces from these analogue input signals either synchronised output signals which indicate existing working conditions of the engine or in the case of continuously varying, constantly occurring working states proportional frequencies which may preferably be indirectly processed by the digital computing circuit of the fuel injection system.

As input signals for the connection circuit or "interface" circuit it is therefore possible to consider, for example, idling- or fullload switching signals derived from the accelerator position; signals which are pro portional to the temperature of the engine e.g. analogue output voltages gained by means of temperature-dependent elements in the vicinity of the engine, so-called NTCresistors may preferably be used; signals which represent starting of the engine and finally signals which define the engine itself as a regulating path to the extent that, from the composition of the exhaust gases, an electrical variable switching state is achieved which is a measure of the stoichiometric composition of the fuel-air mixture supplied to the engine.For this purpose a so-called "oxygen probe" or Probe is preferably used which alters its output voltage abruptly in the vicinity of the air number X equal to 1.0.

Air number A is defined as the ratio of air quantity to fuel quantity which is supplied to the engine. The value X equals 1 in the air number is produced with a stoichiometric fuel-air mixture. From all these and possibly other input signals indicating the working state of the engine, the circuit 4 forms output signals which may partially occur simultaneously, as may be the case for example when starting from idling taking the engine temperature into accoount, and which also occur singly during continuous running of the engine. However, usually all input signals indicating the working state of the engine must be further processed taking the engine temperature into account. A more detailed description is given hereinafter with reference to Fig. 2 of the production of several of the output signals of the circuit 4.

The correction frequency fK required for counting down the register content of the main computer 1 is supplied to the main computer through a correction computer 5 which may be constructed in differing ways. In the simplest case, the correction frequency produced by the correction com puter 5 may be a constant frequency; usually, however, it is dependent upon different operating parameters of the engine and in fact particularly upon the engine temperature. Tn computing the correction frequency, the correction computer considers, for example, a plurality of actually existing factors and parameters of the engine, for example idling (LL), full load (Vl). starting (so). temserStllre of the engine, starting boost after idling, temperature-denendent starting boost, temneraturedependent and time-dependent subsequent starting function, Psrtinl load state, correction factor in A-regulation, various correction factors being poseihleq and possihiv other working states which are not listed for reasons of clarity in the total review of the system.

It is clear however that these above mentioned operating parameters are different for almost every type of engine since each engine has different characteristic fields of these factors relative to one another and in dependence upon the engine temperature.

It is therefore a requirement that it is possible to gain from the input signals, which are in themselves relatively simple to acquire, data about the operating state of the engine for the computing circuit which are in keeping with this type of engine and enable computing of the correction frequency.

The present fuel injection system therefore has a set-value memory to which are supplied a plurality of data values which are to be tested and which are in keeping with each operating state of the engine to be supplied with fuel injection pulses, the temperature dependence also being particularly considered.

In the embodiment of Fig. 1 there is provided in addition to the correction computer 5 an address computer 6 which computes from the preferably synchronised switching and state signals supplied to it from the engine (which may alternatively be defined as status signals) an address which is additionally dependent upon the temperature of the engine and using this address interrogates the memory to test the specific value to be considered when computing the correction frequency. If, as in the embodiment of Fig. 1, further individual computers for the running of the engine are preferably provided, for example firing point computers, gear computers and the like, the memory may take the form of a central main memory 7 which is then only required once but must have a sufficient capacity to supply all individual computers connected to it.The addressing of the central main memory 7 with the addresses from the address memory 6 and derived from the status signals is then effected through an adaptation circuit 8 which establishes connection between the associated singlepurpose computer and the central main memory 7. The intermediate circuit 8, which may also be termed ' "bus-interface-circuit" if the only once occurring data- and belaying-lines 9 are designated but lines, receives the address for the access to the central main memory 7 as, for example, an 8-bitparallel word from the address computer 6, converts this address depending upon the number of available bus lines into binary sub-word packets, for example each into two 4-bit words, checks the belaying of the bus lines on a separate belaying line provided with the reference number 10, belays the bus lines if thye are free, and transmits the address in binary word packets serially to the central main memory 7. The businterface circuit 8 then waits for the transmission of the addressed data from the main memory, receives this in the illustrated embodiment, which includes 4 bus lines, in two-times 4-bit words and takes back the belaying of the belaying line. The received data may then be passed on as an 8-bit word serially to the correction computer 5. The flow control of these processes is effected advantageously by means of a counter in individual timed stages.

The entire process run-off of this computing circuit occurs in synchronism so that a main divider (not shown) is also provided which produces all the control cycles required in the circuit of Fig 1 by dividing the basic timing frequency of, for example, 600 KHz. The main divider circuit produces corresponding multiplex cycles for the main computer, access cycles for the flow control in the address computer, regulating frequencies for the working states, subsequent starting, starting boost, A-regulation and the like. Timing control frequencies also required for pressing the analogue input switching signals supplied to the connection circuit 4 into a compulsory synchronised grid.

The illustration of Fig. 2 shows another embodiment of a digital computing circuit in a fuel injection system which is shown in greater detail and in which the memory for the correction computer is associated with this directly and exclusively so that there is no need for the address computer and the bus-interface circuit of Fig. 1.

The digital fuel injection system of Fig. 2 is characterised mainly by a particularly low total circuit outlay, mainly because of the use of a new interpolation process for the determination of memory values in the correction computer 51 and the possible use of stochastic counters in the main computer 1.

In describing the circuit diagrams of Fig.

2 one proceeds firstly from the partial circuit zone 4 which produces from an analogue input voltage an air quantity frequency fML which is proportional to the intake air quantity of the engine.

An external analogue voltage UML is supplied to the circuit for producing the air quantity frequency fML. This voltage UML is gained, for example, by means of a potentiometer 11 whose tappings 12 is displaced by a baffle flap 13 which is disposed in the intake manifold 14 of the engine and is deflected in dependence upon the intake air quantity. There is no necessity to go into greater detail about the production of the analogue air quantity voltage U}\IL which is possibly proportional to the air quantity by means of correction measures; this voltage passes as an analogue voltage to the non-inverting i.e. positive input of a comparator 16 which may be, for example, a differential amplifier.An analogue voltage is also supplied to the inverting input of the comparator 16, more detail about the achieving of this voltage being given hereinafter but its level, as may be seen, determines the sign or the type of output signal of the comparator 16, The comparator 16 is so constructed that, for example, when the air quantity votlage Un is greater than the voltage supplied to the other input, its output signal assumes a first logic state, for example, the state 0 and if the air quantity voltage UAII, is smaller than the voltage supplied to the other input, the comparator output assumes for example the logic state 1.The output of the comparator 16 is connected to the sign input of a dual forwardbackward counter 18 so that the sign of the output signal of the comparator 16 determines in which counting direction the forward-backward counter 18 counts a counting frequency fx which is supplied to a second input.

The dual forward-backward counter 18 forms with an associated series multiplier 19 a number-frequency transducer or a socalled DDA-circuit 20 wnich is also known as a digital- differential-analyser.

For the better understanding of the mode of operation of the DDA-multiplier 20, a possible embodiment of such a multiplying circuit is firstly described with reference to Fig. 3. A DDA-multiplier may basically take the form of a series multiplier or a parallel multiplier, a binary word being multiplied with a basic frequency. Since the parallel multiplier is more complicated, in the present embodiment a DDA-series multiplier is used and the operation is such that the individual points of the binary word applied thereto are evaluated with the basic frequency. An output frequency is then produced which as a DDA-frequency may be subsequently irregular but which has the advantage that it may be converted back into an analogue voltage using relatively simple means, for example by integration with an RC-member.

From the diagram of Fig. 3 it may be seen that the frequency fe, which is supplied to a counter 21, emerges as the input frequency for the series multiplier. The counter produces from the input frequency fe a plurality of sub-frequencies whose pulses are offset relative to one another in such a manner that an addition of these sub-frequencies is possible to form a total frequency. In the simplest case, these subfrequencies may be produced by means of a - successively connected chain of bistable trigger members or flipflops each of which reduce the input frequency by 50%.The binary word by means of which the DDAmultiplier of Fig. 3 evaluates the subfrequencies produced by it lies at the output of a register 22: these may be, for example, the parallel outputs of the dual forward backward counter 18 of Fig. 2 but alternatively, as is explained later, they may be the parallel outputs of an intermediate memory, set-value memory of the like. The sub-frequencies pass through a connection line 231 from the counter 211 to the ipnut (s) of AND-gates 24 whose other inputs are supplied with the bit of the binary word which evaluates this frequency from the counter or memory 22l. The frequencies thus formed at the outputs of the ANDgates 24 are combined by a subsequently connected OR-gate 25 into a total output frequency fa.The connection of the individual frequencies to the points of the binary word controlling the AND-gates 24 is such that the highest frequency is connected to the MSB (most significant bit) i.e.

with the higher value bit of the binary word, the lowest frequency being connected to the LSB of the binary word. The result is a mixture of the most varied frequencies depending upon the evaluation supplied by the binary word at the series multiplier. There is therefore produced for the output frequency fa through the input frequency fe (see Fig. 3a) a functional dependence whose slope is determined by the binary word applied to the series multiplied. The general formula for such a DDA-multiplier is therefore fa = Zi. fe, Zi being the binary word, which varies in dependence upon the sign supplied to the dual forward-backward counter 18 of Fig. 2, at the parallel output of the forward-backward counter.

As an input frequency for the series multiplier 19 of Fig. 2, a basic timing frequency fo is used which may be, for example, 600 KHz. The output frequency fML of the series multiplier 19 is then proportional to the intake air quantity per stroke, this output frequency fML being fed back to the input of the circuit part 41 which operates to this extent as an analogue-digital transducer, feedback being through an intermediate circuit 21 for pulse shaping. This shaping circuit 21 serves simultaneously to compensate for the influence of possible power supply fluctuations, i.e. it is so constructed that the pulse amplitude of the fML-frequency supplied to its input varies with the mains voltage UB also supplied to it in such a way that there is simultaneous compensation of this voltage.The output of the shaping circuit 21 is connected through a resistor 22 and an earthed capacitor 23 (which both operate as simple digitalanalogue transducers) to the inverting input of the comparator 16 so that a feedback and regulation of the functioning of the entire circuit results since output frequency fML is continuously compared with the analogue air quantity input voltage UML.

The air quantity frequency fML produced in this manner and mentioned above passes to the main computer I and in fact to the input of a forward counter 27. The coutner 72 counts the air quantity frequency fML during an angle segment of the crank shaft revolution so that a control circuit 28 is provided which is acted upon by the speed of the crank shaft of the engine and which, for example on the occurrence of a speed pulse through a line 29, causes the counting in of the air quantity frequency in the forward counter 27 and stops the upward counting process of the counter 27 after, for example, 60 of crank shaft rotation. The counters 27 is then reset through a line 30 and a delay network 31. A counter reading is produced in the forward counter 27 which corresponds to the air quantity divided by the speed.The binary number formed in the counter 27 is surrendered in parallel to another counter 28, an intermediate memory 29a possibly being provided which at the moment of takeover pulses from the control circuit 28a takes over the counter reading 27 so that this counter is again ready for the next counting process. A divider circuit 32 may be associated with the control circuit 28a, said divider circuit reducing the speed pulses supplied to it from the control circuit 28 depending upon the number of engine cylinders and producing the takeover- pulses for the content of the intermediate memory 29a onto the subsequently connected counter 28 in the form of a backward counter.Simultaneously with the takeover pulse, a bistable circuit element, for example a flipflop 33 is triggered into one of its states; as a result of supplying the correction frequency fK whose production is described later in greater detail, the backward counter 28 counts downwards and on reaching a predetermined counter reading, for example zero, produces an output pulse which is also supplied through the line 34 to the flipflop 33 which is consequently triggered back into its initial state. The length of the station time of the flipflop 33 so gained is a measure for the length of the injection time and corresponds to the earliermentioned preliminary pulse length te. A zero-identifying circuit 35 is associated with this backward counter 28 for identifying zero.The forward counter 27 and the backward counter 28 may alternatively, as mentioned earlier, take the form of stochastic counters and more detail is given of this hereinafter.

The production of the correction frequency fK is now described in greater detail.

For this purpose, an interpolation counter 37 which is influenced by a control device 36 is provided which produces at its output a word, which in this embodiment com prises 5 bits, and which supplies it as a partial address to a set-value memory 38.

The control device 36 reacts to the operating parameters of the engine in such a way that the condition data required for the actual running of the engine pass to the interpolation counters 37 which forms a partial address from this, as already mentioned. This address is completed in the embodiment by three other bits derived from the MSB-parallel outputs of a series multiplier 39; these three outputs form the three LSB for the address of the set-value memory 38 which comprises 8 bits in toto.

The above-described partial circuit for producing the correction frequency operates somewhat similarly to the DDA-multiplier of Fig. 3, already described with reference to the circuit 41; only with the difference that the binary word lying at the series multiplier 39 for evaluating the individual sub-frequencies is an 8-bit word from the set-value 38. The supply voltage of the series multiplier 39 is a relatively low frequency fv, which is proportional to the engine temperature. Such a frequency is gained, for example, by means of an oscillator 40 which is supplied with the engine temperature as a resistance value and is so constructed that its output frequency may be controlled in dependence upon a resistor; such oscillators are known in the art and need no further explanation.As a result of the parallel derivation of three MSB-points of the series multiplier 39 to form the LSB (in the embodiment of Fig. 3) for the address of the memory 38, a particularly simple interpolation circuit is achieved for addressing the memory and for gaining an output frequency fA of the series multiplier 39 which takes into consideration the pertinent operating states of the engine. It is self-evident that the dual forward-backward counter 41, which is acted upon by the output frequency fA of the series multiplier 39, is still part of this interpolation circuit since the output frequency fA is delineated in this counter over a predetermined period as a binary counter reading. In parallel to the counting frequency fA for the dual forward-backward counter, a sign passes the forward-backward counter 41 and determines its counting direction.

The interpolation counter 37 which produces the five MSB of the address for the memory 38 runs cyclically through the individual working states of the engines and produces their address when informed by the control device 36 that this working state actually exists. In this case, the working state, for example full load, is addressed by the interpolation counter 37; the 5-bit address for this working state is then completed by the three MSB at the parallel output of the series multiplier 39, i.e. the divider counter of the series multiplier 39 is used simultaneously as an x-counter for the memory addressing.

On the other hand it is also possible for several working states of the engine to be present simultaneously, for example starting boost after idling on starting the engine and heating-up. In this case, the control device 36 allows the interpolation counter 37 to run through these parallel working states cyclically and to address them, the control device only supplying a takeover pulse through the line 43 to a memory 42 connected after the forward-backward counter 41 when all parallel working states have been run through cyclically once. In this way, the output frequencies for the serially run through working states, which are understandably different owing to different addressing of the set-value memory 38, are summed in the forward-backward counter 41.

In the presence of a new operating state, which is transmitted to the control device 36 by the analogue ipnut signals A in their totality, an initial counter content of the forward-backward counter 41 may be predetermined by the action of a pre-connected initial-value memory 44 which, if required, may also be switched over cyclically in a suitable manner through a line 45 by the control device 36. In this case, the forwardbackward counter begins its counting process with a set initial value; at the end of the cycle predetermined by the interpolation counter 37, the counting content passes in accordance with the takeover pulse from the control device 36 into the intermediate memory 42 in which the sum of the correction factors is therefore present.This intermediate memory 42 then forms again with its parallel output the binary word which is converted by an associated series multiplier 47 in the above described manner into a frequency. This supply frequency of the series multiplier 47 is therefore half of the basic cycle, i.e. fo/2, since in the present embodiment a second correction partial frequency is produced separately which relates to the so called "X-regulation" of the engine.

It is of course possible to produce more than these two separate correction frequencies as individual partial frequencies but on the other hand data values may alternatively be received in the memory 38 which permit incorporation of the A-regu- lation in the above described cycle.

The sum of the correction values pertaining to a given working state is therefore present in the memory 42 for the duration of the cycle determined by the control device 36 (in so doing the control device may identify through the connection line 48 to the counter 37 the latter's state) and the associated series multiplier 47 forms a correction partial frequency using the binary word in the memory 42.

The second correction partial frequency is gained from the voltage which is supplied by the previously mentioned probe in the exhaust system of the engine. The voltage of the X - or oxygen probe UA is supplied to a Schmitt-trigger 49 which, depending upon the state of the Voltage produces an output voltage which is identified as a sign voltage by a subsequently connected forward-backward counter 51.

Depending upon the sign of the output voltage of the Schmitt trigger 49, the counting direction is determined for the forwardbackward counter 51 whose counter reading therefore normally fluctuates by a predetermined value depending upon the probe voltage UA. In this case too there is an association of a series multiplier 52 which is supplied with a counter frequency fo/2 and which in the previously described manner forms a DDA-frequency from the binary number in the forward-backward counter 51 as another correction partial frequency fkll. The correction partial frequency fkl originating from the series multiplier 47 and the more recently mentioned correction partial frequency 1k" are combined (summation point 53) and form the correction frequency fk at which the backward counter 28 of the main computer 1 is counted.

Mention was made earlier of the fact that the counters 27 and 28 may be so-called stochastic counters, i.e. counters whose initial values, if they are ideal stochastic circuits, are almost statistically distributed and are not at the outset determined. It is self-evident that in the case of the stochastic counters used here there is naturally a defined initial sequence of counter readings which, however do not rise or fall regularly but may assume absolutely any conceivable value but a value which may be determined in advance since it is a component which is defined in circuit terms.Such a stochastic counter is preferably formed by a simple series of flipflops, for example, so-called D-flipflops (delay-flip-flops) to whose inputs the counting frequency may be supplied and wherein two or more outputs of the successively connected flipflops are connected by a coupling member to the input of the first flipflop. When a counting frequency is supplied, a counter reading initial sequence results which is certainly not arbitrary but defined and yet does not rise or fall regularly and which may be defined as a forward counting direction and which may be run through by the stochastic forward counter 27.The stochastic backward counter 28 may then correspondingly be so constructed that it runs through the initial sequence defined as a forward direction in the opposite direction, this ensuring that a desired and precise initial result may be obtained by the co-operation of both stochastic counters 27 and 28 as may easily be understood.

The mode of operation of the circuit of Fig. 2 is therefore briefly summarised so that the voltage proportional to the air quantity is converted into a frequency in that the output of the comparator 16 controls the counting direction of the forwardbackward counter 18 which has a word length of 8 bits and in which therefore the quantity ML is stored. By means of a DDAmultiplier 19 an air quantity frequency fML is obtained therefrom which produces the comparison for the comparator 16 after pulse shaping in the shaping stage 21 and by analogue mean-value formation. In connection with the subsequently connected forward-backward coounter operating is an integrator, the comparator 16 therefore regulates the produced air quantity frequency so that it corresponds to the analogue input voltage.Although the word length supplied for the air quantity ML per stroke in the integrating forward-backward counter 18 is relatively short at 8 bits, a far greater accuracy is obtained owing to the regulating circuit formation in the time means than corresponds to the word length of the forward-backward counter 18. The engine speed, which may be relatively low, is then counted out periodically at this air quantity frequency fML. For this purpose only a stochastic counter is required as already mentioned. After the counter content of the forward-backward counter 27 is taken over in the result memory 29a, the latter contains the uncorrected injection time which leads to a total injection pulse as a result of down-counting with the sum of the correction frequencies fk.The interpolation circuit for producing the correction partial frequency fkl also reduces the circuit outlay since part of the address for the memory 38 is produced in the associated DDA-multiplier 39 itself. Several interpolations may be effected one after another with regard to time and the result is then present as a sum in the forward-backward counter 41. Any operating parameters may be incorporated in the initial value of the interpolation; the X-regulation operates with a separate integrator whose output frequency then produces the correction frequency in co-operation with the interpolater output frequency. Since downward-counting is effected with the correction frequency fk, a low correction frequency represents injection enrichment.

The RC-member formed from the resistor 22 and the capacitor 23 has a time constant Tv which is also a measure of the accuracy of the analogue-digital conversion. This time constant should therefore be selected at Tv = 2. accuracy. fMLmin The number-frequency conversion by the forward-backward counter 18 and the DDAmultiplier 19 also has a time constant whose value is determined by varying the counting frequency fx and may correspondingly be so adapted that Ti = 2 Tv.

In the X-regulation a time constant adaptation is obtained, for example, when the counting frequency for the forwardbackward counter 51 is selected, for example in the area of magnitude of the engine speed.

It is also advantageous that the series multiplier during h-integration and the conversion of the sum of the correction values in the memory 42 into a frequency should be less expensive since they could also use the non-coincident partial frequencies of the multiplier of the input stage. It was mentioned earlier that, instead of series multipliers, so-called parallel multipliers may be used, these not being illustrated in the drawings. Such a parallel multiplier operates with an adding device in such a way that the members formed by the counters or integrators are multiplied by themselves again and again in the multiplier, the greater this number, the more frequent the runthrough, the result of these runthroughs is the desired DDA-frequency in the analogue-digital conversion.

Attention is directed to our other UK Application Nos. 47804/76, 47805/76 and 478096 (Serial Nos. 1,570,617, 1,570,618 and 1,570,619) filed concurrently with the present Application.

WHAT WE CLAIM IS:- 1. A device for determining the duration of iniection control signals which are to be supplied to injection valves of an internal combustion engine. the injection time being dependent inter alia upon the speed, air throughout in the intake manifold and engine temperature, said device having an air quantity meter, which produces a proportional output voltage, a temperature probe for location in the region of the engine, a tachometer, a computing circuit which computes from these data the length of the injection pulses, a first rounter, which is arranged to be supplied during a predetermined crankshaft angle with a counting frequency (fML) proportional to the air intake quantity per stroke, an analogue-digital transducer, which is regulated by feedback and processes the output voltage of the air quantity meter, a signal whose frequency (fv) is proportional to the engine temperature (v) being supplied to a digital multiplying circuit for joint processing with other operating parameters of the engine to produce an output frequency (fkl), there being associated with the multiplying circuit an addressable memory whose stored data values emitted successively in dependence upon other operating parameters is multiplied with the engine temperature frequency (fv), the arrangement being such that the output frequency (fkl) of the multiplying circuit is supplied to a summing point together with at least one other frequency derived from at least one other operating parameter to form a total correction frequency (fk) and other counter being provided which takes over the content of the first counter and is counted out with the total correction frequency (fk), the length of time from the takeover point to the attainment of a predetermined counter content of the other counter being a measure of the length of the injection duration (te).

2. A device as claimed in Claim 1, in which the addressable memory includes an address computer which, in a cyclical sequence and controlled by an intermediate circuit acted upon by analogue input signals indicating the operating state of the engine, computes addresses for a central main memory which stores the data values corresponding to the operating states.

3. A device as claimed in Claim 2, in which the addresses computed by the address computer are supplied through an intermediate circuit to the central memory, said intermediate circuit being connectible with other optionally provided individual computers to a data connecting line which is common to all the individual computers and is connected to the central main memory.

4. A device as claimed in Claim 1, including a comparator for producing the air quantity frequency (fML), one of the inputs of the comparator being supplied with a voltage (UML) proportional to the air quantiy per stroke while the other input is supplied with a feedback analogue value corresponding to the produced air quantity frequency (fML), the output signal of the comparator indicating the counting direction of a dual forward-backward counter acted upon by a counting frequency (fx), and a number-frequency converter being provided for converting the counter reading which is formed in the forward-backward counter and which is proportional to the air quantity.

5. A device as claimed in Claim 4, in which the number-frequency converter is constructed as a DDA-multiplier in the form of a series multiplier which is so connected that a comparatively high input frequency supplied to it is divided into a plurality of non-coincident partial frequencies which are selected in dependence upon their associated location of the word

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. Tv = 2. accuracy. fMLmin The number-frequency conversion by the forward-backward counter 18 and the DDAmultiplier 19 also has a time constant whose value is determined by varying the counting frequency fx and may correspondingly be so adapted that Ti = 2 Tv. In the X-regulation a time constant adaptation is obtained, for example, when the counting frequency for the forwardbackward counter 51 is selected, for example in the area of magnitude of the engine speed. It is also advantageous that the series multiplier during h-integration and the conversion of the sum of the correction values in the memory 42 into a frequency should be less expensive since they could also use the non-coincident partial frequencies of the multiplier of the input stage. It was mentioned earlier that, instead of series multipliers, so-called parallel multipliers may be used, these not being illustrated in the drawings. Such a parallel multiplier operates with an adding device in such a way that the members formed by the counters or integrators are multiplied by themselves again and again in the multiplier, the greater this number, the more frequent the runthrough, the result of these runthroughs is the desired DDA-frequency in the analogue-digital conversion. Attention is directed to our other UK Application Nos. 47804/76, 47805/76 and 478096 (Serial Nos. 1,570,617, 1,570,618 and 1,570,619) filed concurrently with the present Application. WHAT WE CLAIM IS:-

1. A device for determining the duration of iniection control signals which are to be supplied to injection valves of an internal combustion engine. the injection time being dependent inter alia upon the speed, air throughout in the intake manifold and engine temperature, said device having an air quantity meter, which produces a proportional output voltage, a temperature probe for location in the region of the engine, a tachometer, a computing circuit which computes from these data the length of the injection pulses, a first rounter, which is arranged to be supplied during a predetermined crankshaft angle with a counting frequency (fML) proportional to the air intake quantity per stroke, an analogue-digital transducer, which is regulated by feedback and processes the output voltage of the air quantity meter, a signal whose frequency (fv) is proportional to the engine temperature (v) being supplied to a digital multiplying circuit for joint processing with other operating parameters of the engine to produce an output frequency (fkl), there being associated with the multiplying circuit an addressable memory whose stored data values emitted successively in dependence upon other operating parameters is multiplied with the engine temperature frequency (fv), the arrangement being such that the output frequency (fkl) of the multiplying circuit is supplied to a summing point together with at least one other frequency derived from at least one other operating parameter to form a total correction frequency (fk) and other counter being provided which takes over the content of the first counter and is counted out with the total correction frequency (fk), the length of time from the takeover point to the attainment of a predetermined counter content of the other counter being a measure of the length of the injection duration (te).

formed in the forward-backward counter to form a total output frequency (fML).

6. A device as claimed in Claim 4, in which the number-frequency converter is constructed as a DDA-multiplier in the form of a parallel multiplier, the binary word formed in the forward-backward counter being added in an adding device with a predetermined frequency and the number of runthroughs being evaluated as the air quantity frequency (fML).

7. A device as claimed in Claim 5 or 6 in which the air quantity frequency (fML) formed at the output of the DDA-multiplier is supplied to a forming stage in which the amplitude of the air quantity frequency (fML) receives a pulse-shaping compensation in accordance with the fluctuating main supply voltage (UB) of the motor vehicle, the output voltage of the forming stage being supplied to a subsequently connetced integrating RC-member which is connected to the other input of the comparator.

8. A device as claimed in Claim 5 including a set-value memory to which a first partial address is supplied from a counter depending upon the operating state of the engine, the parallel output terminals of the latter memory being connected to a DDA-multiplier for converting the interrogated memory value into a frequency, the counting frequency (fv) supplied to the DDA-multiplier being proportional to the temperature (v) of the engine, the arrangement being such that for interpolation a second partial address for the set-value memory is derived in parallel from the MSB-outputs of the series multiplier, and the output frequency (fA) of the series multiplier being supplied to a subsequently connected dual forward-backward counter for the summing of chronologically successive interpolations.

9. A device as claimed in Claim 8, in which the forward-backward counter, which is acted upon by the output frequency (fA) of the series multiplier for taking over an initial value, is connected to an initial-value memory.

10. A device as claimed in Claim 8 or 9. in which a control device, which evaluates the operating states of the engine and controls the counter in the set-value memory which produces one partial address, is provided for the cyclical formation of partial addresses corresponding to operating states, the control device causing, in a cyclical sequence with the occurrence of other operating states, a take-over of the counter content of the forward-backward counter by taking over pulses into a correction-value memory and resetting of an initial value of the forward-backward counter, and the content of the correction-value member being convertible by means of an associated series multiplier into a first correction partiål frequency fkl).

11. A device as claimed in any of Claims 1 to 10, in which the one other operating parameter is the oxygen content of the exhaust gas scanned by an oxygen probe in the exhaust of the engine, which provIdes an analogue output voltage (UA) which passes through a threshold value voltage circuit to a dual forward-backward counter for determining its counting direction, and in which there is associated with the dual forward-backward counter a series multiplier which converts the voltage (UA) continuously integrated in the forward-backward counter into another correction partial frequency (fkll) which forms with the first correction partial frequency (fkl) at said summing point the total correction frequency (fk) for counting out the backward counter.

12. A device as claimed in any of Claims 1 to 11, in which the counter content of the forward counter which counts out the air quantity frequency (fML) during a pre determined chrankshaft angle is supplied to a result counter whose counter content is supplied to the backward counter which is counted out by the total correction fre quency (fk).

13. A device as claimed in one or more of Claims 1 to 12, in which the forward counter and the backward counter for de termining the length of the injection pulse are stochastic counters comprising a num ber of successively connected flip-flops hav ing initial values which are fed back through logic circuits in such a manner that a de fined initial sequence of counter readings is produced in a static distribution.

14. A device as claimed in one or more of Claims 1 to 13, in which, when the uncorrected value in the result memory is taken over in the backward counter, an initial flipflop is set in one of its switching states and is triggered back into its initial state on attainment of a predetermined counter reading in the backward counter by a logic identifying circuit so that the station time of the flipflop corresponds to the injec tion time (te).

15. A device as claimed in one or more of Claims 1 to 14, in which the control device having an associated interpolation counter is so connected that simultaneously occurring operating states are converted in chronological succession by interpolation into an output frequency of the series multi plied in the set-value memory and are stored in a summed form as a result in the sub sequently connected forward-backward counter, the correction value being trans mitted, if other operating states arise, in a cyclical sequence by clearing the dual forward-backward counter and possibly by setting a new initial value (from the initial value memory).

16. A device for determining the duration of injection control signals for the injection valves of an internal combustion engine, substantially as hereinbefore particularly described with reference to and as illustrated in the accompanying drawings.