DE2413015A1 - ELECTRONIC FUEL INJECTION DEVICE - Google Patents

Description

6 Franklin! arr: hU- \ n / O
SchnecksnofsiT. 27 - ie !. j '(70/9

March 18, 197 ^ Gzt / Ra.

North American Rockwell Corporation, El Segundo, California Electronic fuel injection device

The invention relates to control systems for fuel injection systems and in particular an electronic controller for fuel injection systems for controlling a pulse width or duration. It is known that the use of fuel injection systems instead of carburetors for machines with controlled ignition has certain advantages that on the greater control and adaptation options are based on the type of internal combustion engine in question. It is therefore possible reduce fuel consumption, increase performance and above all to reduce the proportion of unburned components in the exhaust gases, especially the proportion of hydrocarbons, Oxides of nitrogen and carbon monoxide. This latter advantage is in terms of air pollution from great importance.

The use of common, well-known injection pumps and injection systems is generally very expensive. In addition, tolerance problems arise in these conventional injection systems and a generally sluggish response. Many fuel injection systems have heretofore been proposed. Typical

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see examples of such injection systems are in US patents 3 456 628, 3 710 763 and 2 980 090. the Devices disclosed in these patents demonstrate something of the prior art. However, these systems also show still lack and flaw. Hence, new and improved fuel injection systems are required. These new fuel injection systems use sophisticated electronic control systems, especially in a largely integrated metal oxide semiconductor design (MOS / LSI).

Analog-to-digital converters are particularly useful where analog signals are used for processing in digital control computers to be converted into digital signals. This type of application is widespread, especially in electronic applications Fuel measurement and injection systems, the digital control computer use.

Many of these analog-to-digital converters have analog sensors whose output signal is a function of their variable resistance is. Typical sensors of this type are thermistors, chromium-nickel wires or the like. With these typical sensors their resistance value varies as a function of temperature. Of course, in a particular application, a sensor that has a has a suitable bandwidth and a suitable parameter adapted to the phenomenon to be measured, in most analog-to-digital converters be used.

According to the invention, an analog-digital converter is provided which is provided with a filter circuit and has at least one electrical Has sensor for generating a signal that turns out to be

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the corresponding analog value of a specific parameter changes. The analog signal is converted into a digital signal. The analog signal and a signal representing the digital signal are compared with one another, the digital signal Can be corrected to reflect changes in the analog signal caused by changes to the electrical sensor caused.

The analog-to-digital conversion can, however, also be carried out by means of a sawtooth signal voltage source, which is a Provides control signal that is processed in the analog-to-digital converter. High and low voltage levels are used for the Operation of the circuit fixed. These high and low levels control the active and inactive parts of the circuit. A logic combination circuit responds to the level in order to selectively switch parts of the digital circuit on or off and a control function for the sawtooth voltage Supply circuit.

A special real-time digital computer is used to calculate the width or duration of the fuel injection pulses. If the fuel is injected under constant pressure, the pulse duration determines the amount of fuel that is consumed in every cylinder of the engine. The pulse duration determines the time during which the fuel injection pump is in operation during each revolution of the machine. The calculator uses data from the to calculate the pulse duration external sensors, data stored in internal permanent memories and a command program that is stored in an additional permanent memory is saved.

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Another digital circuit is plaguing the The correct time is provided for the supply of a control signal for the purpose of ignition or actuation of the fuel injection device. The circuit is mainly operated by control signals from the distributor or the computer to ensure the correct sequence and to determine the duration of the control signals.

Exemplary embodiments of the present invention are shown in the drawing and are described in the following description explained in more detail.

Show it:

Fig. 1 is a block diagram of a fuel injection device according to the invention,

2 shows a circuit diagram, partly as a block diagram, of an embodiment of the analog-digital converter according to the invention,

3 shows, partly as a block diagram, a circuit diagram of a further embodiment of one according to the invention Analog-to-digital converter,

4 is a graphic representation of the analog exponential sawtooth signal used to control the circuit arrangement is used according to Fig. 3,

FIG. 5 is a block diagram of an embodiment of one in FIG Fuel injection device according to Fig. 1 used computer to calculate the pulse duration,

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6 shows a block diagram of a further embodiment of the fuel injection device according to FIG. computer used to calculate the pulse duration,

7 shows the logic combination of an embodiment in the injection control circuit of the fuel injection device according to Fig. 1 used delay circuit, and

8 and 9 are block diagrams showing an embodiment of the fuel injector in the injection control circuit according to Fig. i used logic circuits for control and ignition or Actuation of the injection device.

1 shows a block diagram of the electronic control part of a fuel injection device. Many the electronic components used in this device are already known. A special detailed description these known components should therefore be omitted here, since it is assumed that a person skilled in the art is able to provide a specific Configuration of the individual components depending on the type the rest of the circuit, the structural design of the fuel injection device, etc. to be carried out.

The sensors 10 can be a sensor or a plurality of sensors such as thermistors, strain gauges, potentiometers, etc., which are able to detect environmental conditions such as temperature, Determine pressure, positions and the like. The sensors 10 are connected to analog-digital converters 11. the

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Analog signals generated by the sensors 10 are converted into digital signals by the analog-digital converters 11. The digital signals from the analog-digital converter Ii are fed to the computer 12 for calculating pulse durations. Of the Computer 12 provides signals to pulse generator 16 as described below.

The distributor 13 is a standard type of distributor that is usually is found in any self-propelled vehicle and is equipped with a second set of contacts to generate a reference or identification signal once per engine revolution. The distributor 13 can be any signal generating device whose output signal is functional with the Angle of rotation of the machine or crankshaft is connected. This output signal indicates the operating status of the relevant unit at. In the present embodiment, the manifold is 13 for example arranged in such a way that it is sent once per revolution of the motor (to establish a reference position) and to the individual Cylinder emits pulses for each piston revolution. For example, an 8-cylinder engine generates eight individual distributor signals and a motor revolution signal every revolution of the motor. In other cases it may be desirable or suitable to have this signal from a crankshaft or some other suitable Arrangement.

The signals generated by the distributor 13 are fed to detectors 1h , which can be any suitable detectors, such as reed relays, magnetic sensors, logic gates or the like. The detectors speak to the from

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Distributor 13 to produce an output signal, that the operating state of the distributor and thus the control state of the device, i.e. the operating state of the Motor represents.

The signals emitted by the detectors 14 are fed to an injection controller 15. The injection controller 15 responds to these signals and generates control signals that further control the operation of the engine and the operating status Show. For example, the injection controller 15 can finalize the ignition of the injection drive device or take over the like. The injection control signals are called Function of the operating state of the engine generated, as will be explained in more detail in the following description. The one from the Signals emitted from the injection control 15 are fed to the pulse generator 16, which receives signals from the computer 12.

The pulse generator 16 processes it from the injection control 15 and the computer 12 supplied signals to generate output signals, the driver circuits 17 are supplied will. The driver circuits 17 are conventional control circuits which are used for the actual fuel injection pumps or to control similar devices. The signals output from the driver circuits 17 are Injectors 18 (or other equivalent devices) supplied to control their operation.

It can be seen from this that the signals fed to the driver circuits 17 and injection devices 18 have functions of the pulses supplied by the pulse generator 16. The impulse

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generator l6 supplies pulses which are a function of the actual operating speed of the motor and which are set by the distributor 13, the detectors lh and the control circuit 15. In addition, the pulses represent functions of other factors such as temperature, pressure or the like, which are detected by the sensors 10 and converted into digital signals by the analog-digital converter 11, which are then processed by the computer 12.

In a first embodiment of the analog-to-digital converter according to the invention is a variable resistor for generating an analog voltage signal at a given point of the Circuit used. The analog voltage is converted into a digital signal. One representing the digital signal The feedback signal is compared with the analog signal. The difference between the feedback signal and the analog signal is used for the quantization or digitization circuit to control by digitizing or quantizing the analog signal. A filter circuit is with the digital Circuit and the comparator or comparator connected to control the digitized signal and the feedback signal to smooth out.

A suitable voltage source 110 for generating an essentially constant voltage is connected via a connection point 124 to one connection of a resistor R ^. The resistor R _T is a calibration resistor and can be used in some applications

JLt

Twists are omitted. The other terminal of the resistor R _T is connected to one terminal of a variable resistor R "at the connection point 120. The other terminal of the

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Resistor R ~ is connected to a suitable reference potential, eg ground. The resistor Rg can be a temperature sensitive resistor, such as a thermistor on a chrome-nickel wire, as already mentioned. The analog voltage Vg is generated at connection point 120. This means that the resistors R1 and R2 form a voltage divider between the voltage source I10 and ground. The voltage V _g is a puncture of the resistance values of the resistors R _T and R ₀ . The following applies to the voltage V "

^V S = R ₈ + R _L * ^V B

The signal V _g is applied to the inverting input terminal of a differential comparator 119. The non-inverting input terminal of comparator 119 is connected to terminal 122 to receive the feedback voltage signal V _p . The feedback _{voltage V p} is generated by a filter circuit 118 shown in dashed lines. The filter circuit 118 includes resistors R. and R ₃ connected in series between the voltage source 110 (ie, connection point 124) and ground. Their common connection is formed by the connection point 122.

A capacitor C is parallel to the resistor R _ß and between the connection point 122 and ground. In addition, a resistor R _{c is connected} between the connection point 122 and the connection point 121. The connection point 121 is each connected to a connection of the switches S1 and S2. The switch S2 is between the connection points 121 and 124 (i.e. voltage

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241301S

source 110), while the switch S2 is between the connection points 121 and ground. A digitized resp. Voltage Vj representing quantized voltage is am Connection point 121 is generated. At connection point 123 xvird Release signal (overflow) is generated, which is fed to switch S1 directly and to switch S2 via an inverter 117. In this way, the switches S1 and S2, each released by a high-level or "correct" input signal see mutually exclusive actuable.

The connection point 123 is to the output connection of an adder 113 connected. The adder 113, the overflow signal is connected to receive a signal consisting of η bits from an accumulator 112 and the accumulator 112 feeds. Typically, the accumulator 112 has a plurality of flip-flops, one by one with the stages of the adder 113 are connected. The accumulator 112 also receives clock signals from a clock 111. The clock 111 generates a relatively high frequency signal. In a preferred embodiment, the clock 111 can provide a signal having a frequency of about 330 kHz. The clock signal of the clock generator 111 is also fed to a divider 114, which is a second Clock signal to the clock input terminal of an up / down counter 115 feeds. The up / down counter 115 supplies the adder 113 with a plurality of bits (n bits) Signal too. The counting down or decrementing input terminal of the up / down counter 115 is direct with connected to the output of the differential comparator 119. Additionally is the output of the comparator 119 to the up-counting or incrementing input terminal of the counter 115 via

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connected to the inverter il6. Accordingly, when a clock signal is present from the divider 114, the counter 115 is set by means of a each signal generated by the comparator 119 is counted up (or counted down). The output terminal of the counter 115 is connected to a suitable user device 125. In the drawing, although a series connection is shown, it however, a parallel connection or transmission can also be provided be.

In the operating state, the clock generator 111 carries the relatively high-frequency Clock signals to the clock input terminal of accumulator 112. When the clock signals are applied, each Flip-flop in accumulator 112 flipped to the previously stored Store signal in the appropriate stages of the adder 113. This transfer of information becomes common made during the pulse leading edge or (trailing edge) of a clock signal. After that, this is done in this way in the The signal stored in the accumulator 112 is fed back to the adder 113. This process, also known as accumulative Can be referred to as recirculation, is continued with each clock signal, whereby the signal stored in the accumulator 112 and thus in the adder 113 is in the form of a linear Modulo 2 increase grows.

In addition, the clock signals are fed to the divider 114, which divides the clock signal by a divisor which corresponds to the number of bits in the signal stored in the accumulator 112. In a preferred embodiment, the clock signal is divided by a divisor 2. This second clock signal, ie the ^{clock signal divided by the divisor 2 n} , is added to the clock

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Connection of the up / down counter 115 supplied. The counter 115 runs at a much lower frequency than that Accumulator 112 clocked or operated. If the counter 115 is clocked, the input signal which counts up or down can be can be recorded by the operational counter 115. The signal in up / down counter 115 is a direct function of the output signal generated by the difference comparator 119.

The signal or memory content of the counter 115 is continuously fed to the adder 113 and added to its content. Since the contents of the adder 113 are added to the contents of the accumulator 112 at the next clock signal of the clock generator 111, the contents of both the accumulator and the adder reflect the changes determined in the counter 115. Thus, the content of the counter 115 is added to the content of the accumulator 112 with a periodic frequency f which is determined by the frequency of the clock signal. The adding process also has a corresponding period T _c .

The content of the counter 115 and the content of the accumulator 112 each comprise η bits. If the bit of the content of the accumulator 112, which has the highest significance, is added to the bit of the highest significance contained in the counter 115, overflow bits occur periodically as a result of the additions (controlled by the clock signal). These overflow bits cause an overflow voltage. It can be seen that after 2 ⁿ bit times the number of overflows is given by:

Number of overflows = 2 ¹ ^ "-! = N

V2 ⁿ /

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2413Q15

The overflow output of adder 112, namely the overflow voltage, is a binary signal. This signal has a period duration d or a pulse duty factor d which is proportional to the whole number N, that is to say to the content stored in the up / down counter 115. The duty cycle averaged over 2 ⁿ cycle times is equal to the number of overflows multiplied by the duration of each overflow, divided by the period of 2 ⁿ cycle times and can thus be expressed as follows:

_d = -J2 = -ü

2 ⁿ T 2 ⁿ

From this it can be seen that with constant N the overflow signal is a periodic signal whose period T, is always less than or equal to 2 ⁿ T or:

In view of the relative operating frequencies, i.e., in view of in view of the fact that counter 115 is much slower than adder 113, N appears to remain constant during a typical operation.

The overflow signal emitted by the adder 113 is used to directly control the generation of the signal Y ^ . That is, the signal voltage Vp by selectively connecting the connection point 121 to V _ß or ground by means of the Sehalter Sl and

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S2 is generated. The switch S1 is closed and thus the voltage source V _{β is} connected to the connection point 121 when the overflow signal is "correct". Conversely, the switch S2 is closed, whereby the connection point 121 is connected to ground if the overflow signal is "false". When the switch S1 is closed, the switch S2 is open and vice versa. In addition, it can be seen that the duty cycle and the period of the signal V ^ are equal to the duty cycle and the period of the overflow signal. Since the DC component of a binary voltage, such as V _D , is proportional to its duty cycle, the DC component is also proportional to N. The DC component or low frequency component of the V ^ signal varies between V "and ground in accordance with the duty cycle of the overflow signal, which controls the mode of operation of the switches S1 and S2. If the overflow signal has a high clock ratio, the switch S1 is closed more frequently and thus more frequently than the switch S2. Accordingly, V ^ at connection point 121 has a low-frequency component with a relatively high voltage level, that is to say a voltage level which is closer to voltage V _β . Of course, the reverse process creates the reverse stress condition.

The signal V ₀ is fed to the filter circuit 118 shown in dashed lines. The low pass filter circuit 118 processes the voltage V ₀ and effectively smooths its pulsating amplitudes. The filter circuit provides a substantially constant output signal Vp (ie the feedback voltage) as a function of the input signal V _D. The DC voltage component of the feedback signal V n fluctuates between

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V ". and V " _mav as a function of or controlled by

.1 / IQXIl * χ * ΠκϊΧ _#

Value of N (i.e. the number of overflows on adder 113). The following applies:

^V F ^{= V} F min. ⁺ ^ ^V F max. " ^V F min.) -,

2 ⁿ

ν _π . = τ? 2— L · _ — __. ν

F mm. R. R ₇ , + R "Rr, + R. Ii _n B

- BAC . ^V F max. ~ R _A R _B + R _ß R _c + R _A R _ß ' ^V B

By appropriate selection of the resistance values of the resistors R _A and Rg in relation to the resistance R ~ the voltages can

V ₁ -,. and V " _me ^. equal to the minimum and maximum values r now. r max.

can be set by Vg. Since V _{g min} and V _g functions

from R ₀ . ^ and R _{c mo} ^. it can be shown that the following applies: ο mxn. ._ ^ ö max.

^V S max. _± _ ^R L ^ ^R S max. " ^R S min.

^R C ^V S min. ^R S min. ^ ^R S max. ⁺

RVV R R

^Ά Α S ^{max. - V} S min. S max. - ^a S min.

^R C ^V B ^V S ~ max. ^R S min. ^{+ R} L

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The time constant of the filter circuit depends on the values of the resistors R., R.sub.n and _R.sub.c as well as on the capacitance of the capacitor C. The time constant results from the equation;

R R R

^{A ö} °. C.

R _A R _B + R ₅ R ₀₊ R _A R ₀

This time constant must be large enough so that the output signal Vp is not more than a least significant bit during a period of the overflow output of the adder 112 changes. The time constant can be defined as:

¹ F " ^{d 1} C

If the time constant is too large, the operating bandwidth of the converter is reduced.

The resistors Rt and R _g form a voltage divider between the voltage source 110 (ie the voltage V _β ) and ground. A signal voltage V _g is sampled at connection point 120. The voltage V _g changes with the resistance of the resistor Rg. The resistance R _g changes as a function of temperature or some other quantity to be measured. The signal voltage V _g represents the changes (if there are changes) of a specific _{function represented by the resistor R g} . This signal is in analog form. In order to be able to use it in a digital computer, the analog signal must be digitized, as it is, for example, in the forward / backward

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Counter 115 happens. The digitized signal becomes the user device 125 supplied.

In order to bring the digitized signal up to date in accordance with the conditions present at the sensor Rg, the digitized signal and the scanned signal are compared with one another. The signal voltage V _g at connection point 120 and the feedback voltage Vp at connection point 122 are fed to the differential comparator 119, as already mentioned. The comparator 119 compares these signals and produces an output signal that is a function of the difference in the signal voltage and the feedback voltage. The output signal of the difference comparator 119 is used to count up or count down the counter 115 depending on the sign of the output signal. The up / down counter 115 is clocked once during each period of 2 clock times, as already described. Accordingly, when each clock signal is applied, the signal stored in counter 115 is changed in the corresponding direction (as a function of the signal applied to the upward and downward counter inputs). If the content of the counter 115 changes in accordance with the signal output by the comparator 119, the contents of the adder 113 and the accumulator 112 change Change in overflow voltage. When the overflow voltage changes, the voltages Vjj and V _{p change} . Accordingly, the voltage V _{g is} "regulated" until the signal generated by the comparator 119 alternates between correct and incorrect. In this way the content of counter 115 does not change (with the exception of the bit

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lowest valence) and the overflow voltage remains essentially constant. The filter circuit 118 is able to smooth the relatively high-frequency ripple that may appear in the V ^ signal, so that the voltage V _{p is} a relatively smoothed analog signal. This relatively smoothed signal can be better compared with the analog signal V _{g in} order to generate a suitable output signal from the comparator 119.

There is thus a circuit for converting an analog signal generated by an analog sampling device into a digital signal, which is then digitally processed, e.g. in a digital computer. The digital signal becomes one Circuit supplied which essentially converts the digital signal back into an analog signal. A filter circuit prepares this converted analog signal for the purpose of feedback and comparison with the original analog signal. To this Way, the relationship between the digital signal and the original analog signal can be continuously updated And the digital signal provides a more accurate running representation of the analog signal. A special The advantage of this circuit arrangement is that only a very small number of analog precision circuits components is required and that the implementation of the Analog signal is made into a digital signal regardless of the supply voltage. The translator is not attached to a specific one Kind of sensors, as long as the sensor used has a suitable bandwidth. Used in this embodiment the sensor has a resistance value as one of a quantity to be measured and digitized (such as temperature) corresponding parameters.

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Of course, certain modifications can be made to the converter. For example, the calibration resistance It, not applicable in certain cases. A calibration resistor can also be used at opposite ends of the sensor resistor will. The ratio of the resistance values of the calibration resistor and sensor resistance is a function of the required and / or desired accuracy of the circuit arrangement. A certain preferred ratio between the clock frequencies, the number η of bits, the filter time constants and the bandwidth of the sensor. Furthermore are Modifications to the various digital circuits and thus changes in the interaction of these circuits are possible.

Another embodiment of the analog-digital converter according to the invention uses an exponential sawtooth signal for digitizing an analog voltage. Several comparators compare the sawtooth signal with different analog signals, to control a logic circuit. The logic circuit controls various registers in which a digitized Version of a sampled analog signal is generated.

In Fig. 3 the circuit diagram of this embodiment of an analog-digital converter is shown. The voltage source 110, which supplies a substantially constant voltage Vg, is connected to the connection point 231. A voltage divider network, which has the resistors R _ß , R _g and R _ß , is connected between the connection point 231 and a suitable reference potential, for example ground. The resistors R _ß and R _c are fixed resistors, while the resistor R _{g is} variable

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Resistance, e.g. a potentiometer, is. The resistor R "is connected in series between the resistors R _ß and Rp. The common connection 215 of the resistors R "and R" is connected to the inverting input terminal of a differential comparator 211. The common connection 216 of the resistors Rg and Rp is connected to the inverting input terminal of a differential comparator 213. The tap of the resistor Rg is connected to the inverting input terminal of a differential comparator 212. The non-inverting input connections of each differential comparator 211, 212 and 213 are connected to the connection point 21 * 4 of the sawtooth generator circuit 235. The generator circuit 235 generates an exponential sawtooth voltage V _p which is fed to the differential comparators via the connection point 214. The signals V ™ and V, are generated at terminals 215 and 216, respectively, and set the upper and lower limits of the operating voltages of the circuit, as will be described below. The sampled or detected signal V _g is generated at the tap of the resistor Rg. The resistor Rg can be a conventional potentiometer which is driven by a control element, the position of the control element being fixed.

The sawtooth generator circuit 235 has a resistor R. and a capacitor C _{A connected} in series between a connection point 231 and ground potential. The common connection of the resistor and the capacitance, the connection point 214, is also connected to one connection of a resistor R _D. A switch SIl is connected to the other terminal of the resistor Rjj and ground. The control terminal of the switch SIl is connected to the logic circuit, as will be described below. In one embodiment, the switch

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SIl have a typical field effect transistor whose source-sink path lies between the resistor R _ß and ground and whose control electrode is _{supplied with the Q HL} control signal.

The logic circuit includes a D-type flip-flop 217 whose D input terminal is connected to the output terminal of the differential comparator 213 to receive _{the signal Q L.} The clock connection of the flip-flop 217 receives the system clock signal C. The flip-flop 217 is used to synchronize the signal Q _L with the system clock. The Q output terminal of the flip-flop 217 feeds the signal Q _{DL to} an input terminal of an AND gate 222.

The output terminal of the comparator 213 signal Qt is also via an inverter 219 to the K input of a JK flip-flops 218 supplied. That at the output connection of the comparator 211 output signal Q n becomes the J input terminal of the JK flip-flop 218 is supplied. The system clock signal C is also fed to the clock terminal of the flip-flop 218. That The signal Qtj output at the Q output terminal of the flip-flop 218 is fed to the switch SIl and causes a discharge the capacitance C. to ground. The output signal Q ™ _ becomes generated at the Q output terminal of flip-flop 218. This connection has one input of an OR gate 224 and one third input of the AND gate 222 connected.

_{The output signal Q s} emitted at the output connection of the comparator 212, which _{denotes V p} ^ i Vg, is fed to an output connection of the OR gate 224. Another entrance

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Connection of the OR gate 224, the output signal of the detector 240 is fed. The remaining input terminal of the OR gate 224 is supplied with the signal Q _HL . The output terminal of the OR gate 224 is connected to the D input terminal of the D-type flip-flop 223 and an input of an AND gate 225. Another input terminal of the AND gate 225 is connected to the ^ output terminal of the flip-flop 223. The clock signal C is fed to the other input of the AND gate 225 and to the clock terminal of the flip-flop 223. The signal Q _pE is a clock pulse for each “false” - “correct” transition of the output of the OR gate 224.

_{The signal Qp E} output at the output connection of the AND element 225 is fed to the clock input connection of a register 226. The output terminals of the register 226 are connected to the user device 125. Although a parallel connection is suggested, it is also possible to connect the register 226 in series with the user device 125.

The Qut output signal emitted at the Q output connection of the flip-flop 218 is fed to the D input connection of a flip-flop 220 and an input of an AND element 221 and the control connection of the switch SIl. The clock signal C is fed to the clock terminal of the flip-flop 220. _{The signal Q DH} t output at the Q output connection of the flip-flop 220 is fed to the reset connection of a register 227. The signal ^ mjr emitted at the 'Q output terminal of the flip-flop 220 is fed to another input of the AND gate 221. The clock signal C is fed to the third input of the AND element 221

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leads. The output terminal of the AND gate 221 is connected to the clock input terminal of a register 229. The output of the AND element 221 consists of a clock pulse for each transition from (λ, τ from false to correct. An adder 23Ο is connected in such a way that it receives parts of the information content of register 227, while register 229 receives signals from adder 230 receives and supplies signals to adder 230. Register 227 is connected in such a way that it supplies signals to adder 228 and receives signals from adder 228. Adder 228 also receives signals from register 229 , namely the signal P, is fed to the register 226. The same signals are fed to the detector 240, which feeds the signal M, which represents the condition P = 2 ⁿ -2, to the OR gate 224. The content of the register 226 becomes the _{User device 125} supplied in accordance with the signal Q pE, as already mentioned.

The operation of the circuit can best be understood if FIGS. 3 and 4 are considered together. The resistors R. and R _D together with the capacitance C ^ and the switch SIl form a sawtooth generator network 235. A typical exponential sawtooth signal 100 is shown in FIG. The signal shown in Fig. 4 is shown a little exaggerated for explanatory purposes. The sawtooth signal 100 represents the voltage V _F which is generated at the connection point 214 of the network 235. The sawtooth voltage V i oscillates between the upper voltage V ^. and the lower voltage V ,. This oscillation is essentially controlled by selectively opening and closing the switch SIl at the appropriate time.

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In addition, the voltage V _F rises exponentially from the amplitude value V 1 to the amplitude value V "during the time T". The resistance values of the resistors R. and R _c are therefore chosen so that the nominal value of Tp

R nom ~ * C
where T _{n is} the period of the system clock signal C.

Furthermore, the voltage divider formed by the calibration fixed resistors R _n and R _n together with the potentiometer R _g is used to generate _{voltages V 0.} , V ^ and V _g. The voltage Vg depends on k, the ratio of the resistance between the tap and the lower connection of the potentiometer, based on the total resistance of the potentiometer. V _g is therefore proportional to the quantity scanned or to the parameter represented _{by the resistor R g.} The signals generated by the voltage divider network are fed to the differential comparators 211, 212 and 213, as already mentioned. These signals are compared with the feedback voltage Y ″ generated by the sawtooth generator 235. The following equations apply to the individual voltages:

R _n + k R _Q

^V S "Rg + Rg + R _c ^V B

^R C

v. v

^V L "R _B + Rg + R _c ^V B

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R _B +

As can be seen from the following, the interaction of the various signals is at least a function of the time in which Vp reaches any particular voltage V. above V _L. This time is denoted by t, the value of t for V _p = Vj ₁ = T _R , as already mentioned. The following applies in general:

= V ₁ . + (V _n - V,) (1 -

where T = RC. The equation relating to V " can thus also be expressed as:

" ^v

b -t / r

^V B In ^V B - V ^T R - ^V L

Now become V, and Vtt by the corresponding expressions above replaced, the latter equation can be written:

^T R = ^R A ⁰ A

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From this last equation it can be seen that T ″ does not depend on the supply voltage V _ß , this assumption being based on the assumption that changes in the voltage V ″ extend over longer times than T ″. This can easily be achieved in that V _ß is filtered accordingly. It can thus be shown that:

R _A C _A in

_a c _A

- ^V

where Tg is the time it takes V _p to rise from V ^ to the sampled voltage V _g. From this equation it can be seen further, that there is only one value of T _g for each particular value of Vg and that increases with increasing V _g Tg.

Since the digital generation of the output signal P only _{depends on T ß} (as can be seen from the following), the digitized data are not dependent on slow changes in the supply voltage. T _R is only a function of resistance and capacitance values, so that any change in T _R must be caused by changes in resistance and / or capacitance values. Therefore, T _{R is} limited to slow changes since resistance and capacitance values change substantially with temperature, and the thermal time constants associated with these components are usually much greater than the period of change T _R. The digital control device should normally only make small corrections during many sawtooth periods. For this reason, only occur in the generation of the digitized signal

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negligible errors as a result of changes in the values of the resistance and capacitance components with temperature on.

After the operation of the sawtooth generator and the voltage divider is described in detail as well as their interaction to generate the various voltage signals, the exact mode of operation of the entire circuit will now be described.

The digital control device is essentially a variable increment counter formed by the register 227 and the adder 228, the content of the register 229 representing the variable increment. The upper bits of register 227, »A ₀ through A _n ., Create a digital number that, with time

increases linearly and its nominal end value (if V "= V _n . is €)

NI
equals 2 ^χ .

Normally, the converter circuit shown in Fig. 3 is supplied with power at time TO. At the time TO, the voltage Vp is lower than the voltages V ", V _g or V" because the capacitor C. should be discharged. For this reason, each comparator 211, 212 and 213 produces an incorrect output signal. A false signal is to be understood here as a binary zero, a signal of low level, a relatively negative signal or the like. Each of these terms is used interchangeably below. _{The signals Q H} , Q _g and Q _L generated by the comparators 211, 212 and 12 are therefore all false signals.

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In general, the sawtooth voltage V i at time T1 equals Vj, the output of the comparator 213 being correct, which causes the AND gate 222 to clock the register 227 with the system clock C. As a result, the content of register 229 is added to that of register 227 once during each cycle time, the result being stored in register 227. The outputs of AND gates 225 and 221 are false, which prevents the register contents of registers 229 and 226 from changing. At time T2, when V _g = V n, the output of DC2 is correct, whereby the output of AND gate 225 is correct during one clock time. As a result, register 226 is clocked once, as a result of which the digital number P is transferred to register 226, where it is stored until it is brought up to date at time T2 of the next cycle. At time T3, when V _p = V ", the output of DCl is correct, so that the Q output terminal of flip-flop 218 is at the correct potential at the next clock time. As a result, the switch SIl is closed and C. discharged to ground _{via R ß.} The time T4 represents the beginning of a new sawtooth cycle.

If the output of DCl is correct, the signal Q., _{L will} be correct at the next cycle time. The signal Q ₁ TT in conjunction with the signal QDjjl causes the output of the AND gate 221 to clock the register 229 once. With this clock, the error in P (Pp-Pp ₁ ) is fed back to register 229 in such a way that the error contained in P is reduced at the end of the next cycle.

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More specifically, the false signal Q ″ is applied to the J input of the JK flip-flop 218. In addition, the wrong signal Q _{s is} fed to an input of the OR gate 224. The false signal Q _L is supplied to the D input terminal of the D-type flip-flop 217 and to the K input of the flip-flop 218 via the inverter 219. Therefore, when the system clock signal C is applied, the wrong signal present at the D input terminal of the flip-flop 217 is copied or transmitted directly to the output terminal of the flip-flop 217 _{as the wrong signal Q DT.} This signal is fed to an input of the AND gate 222. Causes also the same clock signal the generation of a false signal Q _"L at the Q output terminal of flip-flop 218 and a proper Q" _L signal on ^ -Ausgangsansehluß of flip-flop 218. The Q output _HL is the D-input of the Flip-flops 220 and the control input of the switch SIl supplied. The wrong signal 0 ™ causes the switch SIl to be switched off and non-conductive. As a result, the sawtooth voltage V _F on the capacitor C begins to rise in the usual manner.

In the meantime, the correct signal "θ ™" is an input of the AND gate 222 has been supplied to enable its operation as a function of the remaining signals.

The signal Q ™ of the flip-flop 218 is also fed directly to an input of the AND element 221. The wrong state of this signal causes the AND gate 221 to be blocked at this time. Accordingly, the output signal from AND gate 221 (which serves as a clock signal for register 229) is not present. There is therefore no interaction between the adder 230 and the register 229. In the same way, the false state of the signal Q _DL causes the AND gate 222 and 229 to be blocked

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thus prevents the operation of the register 227 with respect to the adder 228.

With a further increase in the sawtooth voltage V “, the voltage Vp reaches the value V- at time T1. With this voltage condition, the comparator 213 generates an output signal Q _L with the correct level. This signal with the correct level is fed to the D input of the flip-flop 217 and, via the inverter 219, to the K input of the flip-flop 218. When the next clock signal C is applied, the correct signal present at the input connection of the flip-flop is transmitted or allowed to pass and fed to an input of the AND element 222. The same clock signal has essentially no effect on flip-flop 218 in that both the J input and K input are both false. Therefore, the correct Q _HT signal is maintained by flip-flop 218. Correspondingly, two correct input signals are fed to the AND element 222, the AND element 222 being enabled by means of each positive rise in the clock signal C. As a result, the register 227 is effectively clocked by means of the clock signals C via the AND element 222. In this operating state, the register contents of registers 227 and 229 are added with each clock signal. In other words, the register contents of the A register 227 are fed to the adder 228 and then fed back to the register 227 again before the next clock signal. At the next clock signal, the register contents of the A register 227 are added to the contents of the adder 228 (the previous register contents of the A register 227) and then fed back to the A register 227. It can be seen that information is stored in the A register 227 in a linear, ramp-like, increasing form.

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be chert. In the meantime, the rest of the circuit remains in the same condition as previously specified. That is, the register contents of registers 229 and 226 change to this extent not when the outputs of AND gates 221 and 225 remain false.

_{If the voltage V p} rises further, the voltage V _{n reaches the value V g} at time T2. At this point in time, the signal Q g generated by the comparator 212 becomes correct. As a result of this signal state, the output signal of the AND element 225 becomes correct during a cycle time. _{The output signal Qp E} emitted by the AND gate 225 clocks the register 226 once, whereby the digital number P is transferred from the designated part of the register 227 to the register 226, where it is stored until it is updated at time T2 of the next cycle Stand is brought.

The voltage V n continues to rise until it is equal to or greater than Vjj. When Vp = V ", the comparator 211 produces a correct output signal Qtt. This correct signal is now fed to the J input of the flip-flop 218, which receives an incorrect input signal at its K input terminal. _{The signal Q H} t therefore becomes correct at the next clock signal, since the signal at the J input of the flip-flop 218 is correct. The correct signal Q _H j is fed to the activating connection of the switch SIl, whereby the switch SIl is energized and connects the connection point 214 to ground via the switch and the resistor R _n . As a result, the capacitor C. is discharged and the voltage V "at the connection point 214 drops to zero.

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241301S

_{The signal Q 1} ,, generated by the flip-flop 218 is of course now wrong. This false signal is fed to an input terminal of the OR gate 224 and an input of the AND gate 222. As a result, the AND gate 222 blocks. As a result of the correct signal Q _g , the OR gate 224 generates a correct output signal. Accordingly, the signal Q _{pE will be correct} until the next clock signal if the correct signal at the D input terminal of the flip-flop 223 causes the (J output to be changed to a false signal. The register 226 is clocked by Qp n, and the digital Data (P) is transferred to this register and stored in it until it is updated during the next sawtooth cycle.

The correct signal Q, τ applied to the D input terminal of the flip-flop 220 also becomes an input terminal of the AND gate 22i supplied. The {J ™ ™ signal remains until the next one subsequent clock pulse C in the correct state. The AND gate 221 therefore receives all correct ones during a clock pulse Input signals and generates a proper output signal which is fed to the clock input terminal of register 229.

The time T4 represents the end of a certain cycle or the beginning of the next cycle. The time segment T3 to T4 is shown exaggerated for the sake of better illustration. In the cyclical mode of operation, time T4 can be viewed as a variable analogous to time TO. The sawtooth voltage V n thus begins to rise again when the initial conditions for the flip-flops and the gate circuit are present due to the discharge of the voltage V _p to a level below V ^. This means,

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the signals Qt, Q _s and Qjr are all false signals if the initial conditions exist, including the false state of the signal Qttt, in which the switch SIl is switched off or non-conductive.

The switching processes described run cyclically or in a recirculating manner. The voltage V "rises and falls as a function of the mode of operation of the switch SIl. While the voltage V _p changes cyclically, the signals Q _x , Q _s and Q “are cyclically driven from the wrong to the correct state. The signals stored in the various registers, such as, for example, register 227, register 229 or other registers, continue to interact with one another and with the various adders. In addition, the state of the signal Q _{g changes} depending on the variation of the signal Vp. That is, the voltage V „reaches the level of the voltage V _g at different times, which depends on _{the voltage of V g.} The operating state during which the register content of register 227 is transferred to register 226 changes accordingly. This means that the _{time required for V p} to reach the voltage level V _g controls the signal generated by the register 227, since the register 227 works in a recirculating sawtooth-like function with the adder 228 only as long as clock signals C are fed to the AND gate 222 after the voltage V _{p has reached} the voltage level V i. Accordingly, the signal is eventually transferred to register 226 and user device 125 therefore changes as a direct function of the level of voltage V _g . An additional feature of the analog-to-digital converter is that a suitable detector 240 for receiving the signals P from

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- 3h -

Register 227 is attached. These signals produce an output signal of the detector when the signals P are a

P = 2 ⁿ - 2

represent defined function. If this signal state is reached, a correct signal is fed to the OR gate 224, that, if the other two inputs are wrong, a correct signal of a clock signal duration from the AND gate 225 to transfer the register contents of the D register 226 to the user device 125.

The analog-digital converter thus uses a sawtooth-like signal to control the digitization of an analog one Signal. The sawtooth or ramp function also imposes high and low limits on digitization, so that an im essentially the same mode of operation is ensured. That is, the same part is always used during each cycle of the sawtooth signal is used.

The analog-to-digital converter does not respond to slow changes in the supply voltage and has a compensation log circuit and circuits that make the analog-digital converter relatively insensitive to changes in resistance and capacity values.

FIG. 5 shows a detailed block diagram of the calculator, denoted by the reference number 12 in FIG. 1, for calculation the pulse duration or pulse width shown. The calculator 12 has several inputs 50 to 55. Though only six here Inputs are shown, can of course in practice any

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Any number of inputs or signal sources can be used. Each of the inputs or each signal source emits the digital signal associated with a specific sensor or converter. These digital signals are generated by the analog-digital converters 11. For example, digital signals can be generated, represent the engine temperature, atmospheric pressure or the like. These signals are referred to as signals Sl, SlA to SNB. The digital signals designate various environmental conditions indicated by the sensors 10, as well as manual ones Entries and / or oak entrances. The signal sources 50 to 55 carry the digital input signals of an address selection logic circuit 56 to.

As will be described below, the input signals from the signal sources 50 to 55 serve as address signals for the Data memory 57. The address logic circuit 56 receives suitable signals from the program memory 6i to enable the transmission of address selection signals from the signal sources 50 to via the address selection logic circuit 56 to the memory 57 to enable. The program signals from the program memory 6l are also combined with the digital input signals, to form part of the address for data memory 57. The program memory 6l, which is the control program of the Hechnersystem receives input signals from the program address counter 62. The counter 62 advances step by step and sequentially actuates the memory 61.

The output terminals of the address selection logic circuit 56 are connected to the data memory 57. From the circuit 56 emitted signals serve essentially to the specific Storage cell or the storage space in the data memory

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to select. The output terminals of the data memory 57 are connected to some input terminals of an accumulator 59. Other input terminals of the accumulator 59 receive control signals from the program memory 6i. The accumulator 59 is connected to a buffer memory 60, so that data stored in the accumulator 59 is selectively shifted to the buffer memory 60 and can be returned from the program memory 6l with appropriate commands.

In addition, two memories, which have a special function table 58 and a number table 64, also receive Signals from the accumulator 59. The special function table 58 also supplies signals to the accumulator 59 again. The charts 58 and 64 are also controlled by the program memory 61, although a connection in the drawing for better clarity with the memory was omitted. Other connections of the accumulator 59 are connected to input connections of a shift register 63 connected. Other input terminals of the shift register 63 are connected to output terminals of the number table 64 connected. In addition, the program memory 6i is connected in such a way that a control signal is supplied to the shift register 63 will. The output terminal of the shift register 63 is to a user device such as that shown in Fig. I Pulse generator 16 connected. The pulse duration signal is generated at the output terminal of the shift register 63.

Looking at FIGS. I and 5 together, it can be seen that that a real-time digital computer can be used for a vehicle fuel injection system. The fuel injector is shown schematically in Fig. 1, while a

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Embodiment of the calculator is shown in FIG. At this Device is injecting fuel into an internal combustion engine or the like controlled in order to achieve environmental benefits. The fuel in the engine is under fixed Injected pressure, the duration of the injection pulses determines the amount of fuel that is in each cylinder of the engine. The duration of the injection pulse (for fuel) is a puncture of the duration of the computer generated pulse duration signal, since the injector is controlled by the signal. For example, electromagnetic Injectors with known properties are actuated in accordance with such a signal. As long as the signal is present the injector is in a prescribed condition and can, for example, inject fuel allow into the engine.

The fuel injector responds to environmental conditions which are detected by means of sensors 10 arranged on the vehicle. The sensors 10 generate analog signals. These analog signals from the sensors 10, which denote environmental conditions, are converted into digital signals. The digital signals are fed to the computer 12, the duration of the Pulses are determined which are fed to the individual injection devices as a function of the signals emitted by the sensors 10 should be. Basically, the digital computer has a memory in which empirically determined data is stored which designate the environmental conditions detected by the sensors 10. The computer then generates 12 a pulse which is supplied to the pulse generator 16 (together with the control signals from the control circuit 15). The im-

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pulse generator 16 feeds the signal to the injection driver circuit 17, which is essentially the injection devices operated to allow (or prevent) the fuel from being injected into the engine. The fuel injection is thus a direct puncture of the characteristics of the pulses generated by the computer 12.

As already mentioned, the signals generated by the sensors 10 are generally analog signals. The analog-to-digital converter 11 converts the analog signals into digital signals. The digital signals are transmitted via the signal sources 50 to 55 (see Fig. 5). These digital signals are continuously fed to the address selection logic circuit 56 fed. In this way, the current status or condition detected by the various sensors is at all times available for the calculator to update the information immediately.

The computer is under the overall control of the program memory 6l. This program memory can be a suitable Have built-up memory with a command program stored therein. Usually the program memory is 6l a read-only memory, such as a diode arrangement or a metal oxide semiconductor field effect transistor read-only memory. The program address counter 62 is any suitable free running counter with a corresponding one Frequency as determined by the processing speed of the computer. The counter 62 can be any suitable oscillator, such as a crystal-controlled oscillator or the like as well as one or more counting switches

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functions, depending on the requirements. The program— address counter 62 continuously supplies periodic signals to the program memory 6l. The output from the counter 62 Signals clock or drive the program memory 6l sequentially through the stored command program. This will make the Operation of the computer 12 is controlled sequentially. The specific switching steps or program instructions (in detail explained later) are executed in response to the drive signals from the counter 62.

At the beginning, the program memory 61 carries a signal from the address selection logic circuit in response to a signal from the counter 62 56 to. This signal can consist of several bits and is a function of the relevant to be performed by the computer Command. This command (signal) is stored in a memory location that is addressed by counter 62. The signal output by the program spexcher 61 is essentially an address or enable signal which is applied to logic circuit 56. When the corresponding signal from Program memory 6l is output, the signal from one of the signal sources 50 to 55 (i.e. the digital source signal Si-SNB) individually transmitted by the address selection logic circuit 56. The source signal and the command signal from the memory 6l are combined to form a new address signal for to form the data memory 57. The data memory 57 can also a read-only memory, such as a read-only memory, into which the information has been read and stored are. The data memory 57 works largely as a so-called look-up table.

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Is the address signal from the address selection logic circuit 56 (under control of the program memory 6l) on Data memory 57, the information stored at the addressed memory location is fed to the accumulator 59. This information is also transmitted in accordance with the standard logic linkage and can be a command require from program memory 6l. The program memory 6i is thus continuously guided or clocked by the counter 62 through the instruction sequence until each signal source 50 to 55 is activated or addressed and the information have been addressed and used at the corresponding storage locations of the data memory 57.

Regardless of the signal source in question, which was accessed and whose data storage location was addressed, the information stored in the data memory 57 (e.g. in the form of 10-bit binary signals) is fed to the accumulator 59 and processed by him. This data transfer naturally takes place under the control of the program memory 6l.

In a preferred embodiment, accumulator 59 may include input select logic circuitry, an adder, and have a storage register. The input selection logic circuit is made by logic signals from the program memory 6l controlled. The link signals depend on the commands executed and are used to link information from buffer memory 60, data memory 57 or the special function table 58 to inputs of the adder. Additional link signals from the program memory 6l link the storage register of the accumulator (or zero) with

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the adder. The content of the adder is then shared with the storage register of the accumulator 59 linked. The resulting process is typical of accumulating registers with selective Multiple data inputs, namely the content of the accumulating The register is replaced by the sum of the contents of the accumulating ■ register (or zero) and the selected input data will.

The temporary storage register 60 is a changeable memory, namely a storage register for partially processed information. Data from the accumulator 59 can be transferred to the buffer register under control by logic signals from the program memory 6l 60 are fed. When the instruction program stored in the program memory 6l determines that the 60 stored information is to be further processed in the computer, the storage register 60 linked to the accumulator 59 again.

During a typical operation, during which the program address counter 62 continues counting, the program memory 6l outputs a sequence of logic signals as a function of the in it stored command program. These link signals enable the sequentially selected sources received data can be used to address the data memory 57 (in connection with the source selection signals), The source selection signals are also used to select a specific table (memory location) stored in the data memory 57 is used, and the data from the source is used to store a specific one in the selected table Address data point.

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The data used in the data memory 57 are accumulated in the accumulator 59. The accumulation of data from the data store is only one form of command, and other instructions cause partial accumulations of Data is stored in the buffer while additional partial accumulations are generated.

After the accumulator 59 has received a certain information assumes mationstatus and the program memory 6l arrives at a specific command in the stored program the information from the accumulator 59 is fed to the special function table 58. Table 58 can be an additional Read only memory, such as read only memory (or even part of memory 57). The signal from the accumulator 59 is effective with respect to the table 58 as an address signal. The data stored in table 58 in the addressed memory location is correspondingly Information supplied to the accumulator 59 (under control of the program memory 6i) and acts there as newly saved information.

The information stored in the accumulator 59 can be taken from the whole number (i) and the mantissa or the fractions (F) can be viewed as consisting of a logarithmic signal. The mantissa or the fraction (F) of the information in the accumulator 59 is fed to the number table 64 for processing. The integer part (I) of the information stored in the accumulator 59 is fed directly to the register 63. Essentially, the signal received from the memory location in the number register 64 addressed by the signal (F) is im Register 63 saved. The one denoting the whole number

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Signal part (I) is then fed to the shift register 63 in order to the information contained therein to the corresponding number of digits, which by the integer part of the in the accumulator 59 stored signal is represented to move on. This operation is of course under the control of the Program memory 61. Once this operation has been completed, the pulse duration signal (PW) represents the pulse duration or Pulse width of the signal to be supplied to the fuel injectors.

For a better understanding of the mode of operation of the one shown in FIG. 5 A calculation example is to be explained in the following. The calculator is to be used to generate the Generate signal PW. The algorithm for the circuit and the motor can be defined as follows:

PW = PW _SB (1 ₊ E ₈₁ K _S1A K _S1B ) (1 ₊ E ₈₂ K _S2A K _S2B ) .. (I ₊ E ^

_SB (1 ₊ E ₈₁ K _S1A K _S1B ) (1 ₊ E ₈₂ K _S2A K _S2B

' ^K SNA (equation l)

PW the final pulse duration,

_{PWg B} the basic or initial pulse duration determined by the basic ambient sensor SB,

Eg. that of the data obtained from the environmental sensor Si certain enrichment factor and

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Kg., And Kg _{1B are} factors that are determined by data from the environmental sensors SiA and SiB and with which the enrichment factor Ε _σ . is to be multiplied.

Equation 1 for calculating the pulse duration is of course only to be understood as representative. Each of the corresponding terms can change. Furthermore, any of the corresponding Constants are set equal to one or zero, whereby the individual terms drop out of the equation or in Modified with respect to other terms.

If only a single term is used, then equation 1 is simplified to equation 2:

PV = PV _SB (I ₊ E ₈₁ K _S1A K _S1B ) (Equation 2) The following values are used to balance the term:

N = 1 20th % E. Sl = 90 % K SiA ⁼ 75 % K SiB ⁼ so:

PW = PW _SB (1 + 0.20, 0.90, 0.75) PW = PW _SB (1 + 0.135)
PW = PW _SB 1.135

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This increases the final pulse duration (PW) by a factor of 13.5 in relation to the basic pulse duration (PVg ₅ ).

The above equations are in the basic form A = QRS. Since this equation can also be written:

LoggA = loggQ + loggR + loggS (equation 3) or as

log A log ( ^QRS ) (10g ₁₁ Q + lo _gl , R + log ^ S) A = B ^ü = B ^ö = B ^Ö ° °

(Equation k)

it is useful to transfer the arithmetic operations from the computer to logarithmic To have the basis carried out. When using logarithms, those appearing in the various equations can Multiplications can be carried out by means of additions.

The computer (see FIG. 5) uses the digital data from the environmental sensors 10 (see FIG. 1), which represent air temperature, pressure in the manifold and the like, as addresses for the read-only memory 57, which stores data in the form of binary numbers Basic pulse duration (PW _gB ), which represent enrichment (E) and scale factors (K). These numbers are read out of the memory and processed in the arithmetic part of the computer as it is determined by the instruction program also stored in the program memory 61. Since the data representing the signals are stored as logarithms

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chert, the calculator can use these numbers to calculate the pulse duration in accordance with that described below Use command program.

In accordance with equation 1, the program address counter 62 begins the arithmetic operation by supplying a signal to the program memory 61 which enables a specific part of the address selection logic circuit 56. More precisely, the signal from the program memory 6l selects the logic circuit 56 or enables it, whereby the digital binary signal S1 of the source 50 is selected. The signal S1 (together with a part of the command signal from the program memory 6i) is used as the memory address signal and supplied to the data memory 57. In accordance with an additional signal from the program memory 6l, the data stored in the memory location Sl are selected and the E _c . representing information is supplied to the accumulator 59 and stored there. Depending on the operation of the accumulator 59, the information stored therein can be fed to the intermediate memory 60, specifically controlled by the program memory 61. Conversely, what is the normal case, the information log _ßl E _g . remain in the accumulator 59, and the program memory 6l is switched on in order to select or enable the logic circuit 56 for processing the signal S2 from the source 5i. The signal S2 (and the command signal) acts as an address signal and addresses the data memory 57. The signal information stored under the memory address S2 is then fed to the accumulator 59 under the control of the program memory 61. In this way, the signal l ° g _{B: J} Kg _{2 is} stored in the accumulator 59.

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If the accumulator 59 has an adder circuit, the signals become log ^ .E. and 1 ⁰ Sd- | K _{S2 is} immediately added as suggested above. This arithmetic operation is continued until the signal stored in the accumulator 59 represents the sum of the logarithms of the signals E _g -, Kg ₁ A and Kg _1B . This accumulated signal is used as an address signal for the special function table 58. As mentioned, the table 58 can be a separate plague repository or a part of the data repository 57. This particular feature is a mechanical function only and is determined by the amount of memory used in the circuit.

However, this address signal (ie the sum of the logarithms) addresses the table 58 and produces an output signal which _{denotes the log B2} (I + (Bi)), where M is the table address. This signal represents the overall function or term 1 + E .. (as shown in Equation 1). This signal is represented as log _B2 (X) and fed to the accumulator 59 under the control of the program memory 6l. The signal is also supplied to the buffer memory 60 in accordance with an instruction from the program memory 61.

Every other one of the individual terms in Equation 1 is applied to the calculated the same way. In addition, each term is added to the number previously stored in the buffer memory 60. The new number is then in the buffer 60 and represents the new sum.

Finally, by continuing this processing process under the control of the program memory 6l, the total input

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Research factor (TE) accumulated. This pactor lets himself represent as:

1Og ₅₂ TE = log _B2 / Ti + E ₃₁ K _S1A K _S1B ) (1 ₊ E ₈₂ K _g2A K _g2B ) ...

(Equation 5)

The address is now obtained from the basic environment sensor SB under the control of the program memory 6i, and the term Information representing PWg ″ is stored in the data memory 57 obtain. This signal is added to the other signals (TE) and stored in the accumulator 59. The result of this Addition (L) is the logarithm of the calculated pulse duration, which can be expressed as follows:

L = I + P (equation 6)

the signal is now represented by the whole number or code number (i) and the mantissas or fractions (F). The mantissa signal (F) is used as the address for the number table 64. The signal F serves as the address signal for table 64. The information stored at the address in table 64 is controlled by program memory 6l, i.e. the binary number stored there, fed to register 63. In addition, the code number signal is thereupon (i) fed from accumulator 59 to register 63. Controlled by the program memory 6l, the register 63 shifts the stored ones Data of table 64 by one place to the left.

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This operation causes both the code number and the mantissa parts of the signal in accumulator 59 to be entered into register 63. After the signal from table 6k has been shifted one place to the left, the resulting number or signal in shift register 63 represents the number PV. This number is used to determine the time increment during which an injector is actuated.

The computer shown in FIG. 5 described so far would need a large amount of data storage. This means that the memory would require 50 to 55 memory locations for each signal source, to be multiplied by the number of points or locations on the curve that represent each of these functions. For the case, for example, that 16 signal sources (one basic source, five actual parameters and two modifiers for each Parameters) as well as 256 points on each characteristic Curve are present, the memory would be 4096 memory locations require. In the event that each memory location is represented by a ten-bit digital number, would more than 48,000 bit storage spaces may be required.

If, on the other hand, the embodiment of an interpolation computer system shown in FIG. 6 is used, the same 16 source signals and 17 parameter points on the characteristic curve only 272 memory locations (2720 bits) require.

When using the interpolation approximation, a normalization device 65 is placed between the data memory 57 and the accumulator 59 switched. In addition, there is an address storage register

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with the address selection logic circuit 56, the data memory 57 and the normalization device 65 connected. In this circuit arrangement, operations similar to those in the circuit arrangement run according to FIG. 5, with the exception that the part with the highest significance and the part with the lowest significance of the address information processed separately. For example, the most significant part becomes the an address signal from the logic circuit 56 representing data information indirectly to the data memory 57 supplied via the address register 66 in order to facilitate the transfer of information from the memory to the standardization device 65 to effect. The remainder of the address information from logic circuit 56 is (via address register 66) the normalization device 65 is supplied. Besides, that will Address signal from address selection logic circuit 56 dem Storage register 66 supplied and stored there. In some cases, register 66 can process the address signal to increment the highest significant part of the address and deliver a one's complement of the least significant part. These interconnections allow a linear interpolation to be carried out on two adjacent memory locations in the data memory 57 with two adjacent and related Commands in the program memory 6l. In this way, the information is stored in the data memory from the described storage location 57 is fed to the accumulator 59 via the normalization device 65. The program memory 6l then effects an incrementation of the memory register 66 by one count, whereby the next data storage location in the data memory 57 is addressed and access takes place. The information located at this memory location is then transferred to the accumulator 59 via the Normalization device 65 supplied. This has the effect that the other

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two adjacent memory locations stored in the data memory 57 Information is normalized and summed up, whereby an averaged information signal is supplied to the accumulator 59, the one between the two adjacent Represents lying interpolated value. A smaller memory can therefore be used because the same information is used more often and averaged values are calculated. This avoids having all intermediate values must be saved in separate storage locations.

If the data connection shown in Fig. 6 in dashed lines 64A is made between the accumulator 59 and the table 64, the output signals of the number table 64 can be entered directly into the accumulator. Also becomes the connection shown by dashed line 57A is used, the accumulator 59 can be used / to address the data memory 57 directly. With the help of this The computer can make interconnections or interconnections by entering suitable commands into the program memory 6i programmed to process extremely complex arithmetic expressions for the pulse duration or pulse width.

The digital computer described can be specially designed for fuel injection systems use. The calculator can add, multiply, divide and generate special functions. Its use is therefore not limited to fuel injectors.

In Fig. 7 the logic operation of an embodiment of the delay logic circuit is shown, which in Fig. I Injection control circuit 15 shown is used. One

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suitable source 338, such as a battery or the like, is connected to a delay circuit 324 by means of a switch 339. The output terminal of the delay circuit 324 is connected to the reset terminal of a plurality Flip flops connected as shown. The reset signal (POR) is transmitted, for example, from the delay element 324 to the reset terminal of the Flip-flops 320 supplied.

The data input port of copy or D-flip-flop 320 receives an identification signal from the distributor signal source 340. The signal source 340 emits distributor signals and can use the distributor 13 shown in FIG. 1 as well as the detector 14. The identification signal occurs once during each motor revolution and sets a reference point fixed in the cycle. A clock signal (C) is applied to the clock input terminal of the flip-flop from a suitable clock generator (not shown) 320 supplied. The clock signal (C) has a higher frequency than the frequency of the signal source 340 given signals. For example, the clock signal (C) can be supplied with a frequency of 20 kHz.

Flip-flop 320 is a type of flip-flop that is often referred to as a copy or D-type flip-flop. That is, da · dem Data — the signal applied to the input port is activated when a Transfer clock signal to the Q output terminal. Such flip-flops thus transmit the input signal to the output terminal when the leading pulse edge (i.e. the positive Pulse edge) of the clock signal. The flip-flops therefore act as edge-delay flip-flops.

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The Q output terminal of flip-flop 320 is connected to the data input terminal of a copy flip-flop 321 and to an input of an AND gate 322. The clock signal terminal of the flip-flop 321 receives the clock signal (C). The reset terminal R of the flip-flop 321 receives the reset or POR signal from the delay element 324. The Q output terminal of the flip-flop 321 is connected to the other input terminal of an AND gate 322. The output terminal of the AND gate 322 generates the signal RP _5, a one-time clock signal which occurs during the positive transitions of the identification signals, and is connected to the K input terminal of a JK flip-flop 323. The clock terminal of flip-flop 323 receives the clock signal (C). The J input connection and the set connection of the flip-flop 323 both receive the POR signal from the delay element 324. The Q output connection of the flip-flop 323 generates a clear signal which is fed to the flip-flops shown and is used in connection with FIG. 8 will be described.

Another signal emitted by source 340, the distribution signal, becomes the data input terminal of a copy flip-flop 325 supplied. The distributor signal represents the actual signals generated by the distributor and has an or multiple signals for each cylinder of the engine. The clock input of flip-flop 325 receives the clock signal (C). Of the The reset terminal of the flip-flop 325, together with the reset terminal of the flip-flop 326, receives the POR signal from the Delay element 324. The Q output terminal of flip-flop 325 is connected to the input terminal of a copy flip-flop 326 and connected to one input terminal of an AND gate 327. The clock signal (C) is applied to the clock terminal of the flip-flop 326

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fed. The Q output terminal of flip-flop 326 is with connected to the other input of the AND gate 327. The AND element 3 ^ 7 generates the output signal DP, which is a one-time Is the clock signal and occurs in the event of positive transitions or jumps in the distribution signal. The output terminal of the AND gate 327 is connected to the increment input of a reference counter 328 connected. The reset input of the reference counter 328 receives the signal RP from the AND gate 322. The clock signal (C) is connected to the clock terminal of the reference counter 328. The reference counter 328, which can be a multiple bit counter, generates an output signal REF consisting of several bits, which is fed to the circuit arrangement shown in FIG.

The signal DP of the AND gate 327 is also the reset el1 input terminal of a counter 329, which is also can be a multiple bit counter. The clock terminal of counter 329 receives the clock signal (C). The increment input port of the counter 329 is connected to the output terminal of an AND gate 331 via an inverter 330. the Input terminals of the AND gate 331 are connected to the output terminals of the counter 329 and receive on-off signal labeled DT consisting of several bits. The output of AND gate 331 is also applied to the data input terminal a copy flip-flop 334 is supplied. Of the The set terminal of flip-flop 334 receives the reset signal POR. The clock terminal of the flip-flop 334 receives the signal DP from the AND gate 327. The (J output terminal of the flip-flop 334 provides a start signal (CRANK) and is connected to one input terminal of an AND gate 335. Another entrance

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connection of the AND gate 335 is to the output terminal of a Digital comparator 333 connected. One set of input terminals (A) of digital comparator 333 receives the one of several Bits of signal DT from digital comparator 329. The same signals are applied to the input terminals of a state— Detector 332 is supplied, which generates an output signal DFT which is supplied to the circuit arrangement shown in FIG will*

The other set of input terminals (B) of the digital comparator 333 receives signals DT _T "from a threshold memory 336. The address input terminal of the threshold memory 336 receives a multi-bit delay signal generated at the output terminal of a threshold counter 337. The delay signal is also fed to the circuit arrangement shown in FIG.

The reset terminal of the threshold counter 337 receives the signal DP from the AND gate 327. The increment input terminal of the threshold counter 337 is connected to the output of the AND gate 335 mentioned above. The clock connection of the threshold counter 337 receives the clock signal (C).

The AND gate 335 receives the output signal from the digital comparator 333 and an output signal PWOK from a digital comparator 338. The digital comparator 338 receives a signal PW from the computer 12 as an input on the Α set of its input connections. _{Comparator 338 receives a signal PW TH} from a signal source 342 on the B set of its input ports.

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In operation, the circuitry shown in Figure 7 essentially controls a delay output signal as follows is described. To start up the circuit arrangement, the voltage source 338 is closed by closing the switch 339, e.g. by activating the ignition of a vehicle, applied to the circuit arrangement. The delay element 324 ensures that the critical elements in Fig. 7 assume the correct initial condition after voltage is applied. This delay allows all occurring switch-on processes to be ended or closed by means of suitable circuits or the like dampen. In addition, the delay ensures that all of the logic combination circuits contained in the overall circuit are energized and ready to receive the reset signal. The reverse part generated by the delay circuit 324 or POR signal causes any flip-flop receiving this signal to be set or to an initial condition is postponed. Perhaps the most important initiating function produced by signal POR is flip-flop 323 to cause to assume the state in which the output signal "delete" is generated. The clear signal is the in Fig. 8 is supplied (which will be described below), whereby the driver circuits for the injectors and thus also the system's fuel injection devices remain switched off until the first identification pulse is produced.

In the meantime, the distribution signals are from the signal— source 340 has been fed to flip-flops 320 and 325, respectively. That the DIST signal continuously supplied to the flip-flop 325 in detail each one generated by the distributor during operation

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In the case of an eight-cylinder engine, eight pulses would be fed to the flip-flop 325 for each revolution of the engine. In a six cylinder engine, only six pulses would be fed to flip-flop 325 for each engine revolution. Naturally Other pulse rates can be used and the pulses supplied by means of a crankshaft sensor or the like. In addition, an identification or identification signal is fed to the flip-flop 320 by means of a suitable device (e.g. distributor, crankshaft sensor or the like). Just one The identification signal is normally generated for each engine revolution and is used to synchronize the distributor operating status and motor revolution. The special ignition sequence of the engine's injection devices is thus determined by recording the characteristic and DIST signals are determined. In addition, the momentary Relationship of the distributor pulses and thus the operating state of the engine with respect to the number of revolutions is determined.

The reset signal POR sets each of the flip-flops 320, 321, 323, 325, 326 and 334 to an initial state, respectively return each of these flip-flops to an initial state. That Set signal causes flip-flop 323 to generate a high or true output signal. Correspondingly effected the cancellation signal supplied to the injection driver circuits and / or injection devices means that the injection system is shut down facilities.

In addition, the reset signal POR causes the flip-flop 320, a low level signal or a false signal at the Q output terminal to create. Conversely, a high level or true output signal will appear at the "Q output terminal of the flip-flop 321 generated. As a result, AND gate 322 only receives

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a high or correct signal and a low or incorrect signal. (The terms high level, positive, binary one, or correct are used interchangeably here. Similarly, the expressions become low level, negative, false or binary zero optionally used. There is a definition of positive or negative voltage levels not intended.)

As long as the AND gate 322 receives two different signals, the output signal RP remains false. The flip-flops 320, 321, 323, 325, 326 and 334 remain in their original state as long as the POR signal remains correct. That is, the den Set and reset input signals fed to flip-flops override the clock input signals. After the POR signal is wrong, the flip-flops respond to the clock input signals at.

If the identification signal is generated by the source 340, a A high level or correct signal is supplied to the flip-flop 320. The next clock signal applied to the clock input of flip-flop 320 (C) causes the positive signal at the data input to go to the Q output when the Y leading edge of the clock signal is applied is transmitted. Accordingly, a binary one or a correct signal from the Q output of flip-flop 320 becomes the data input of the flip-flop 321 and an input terminal of the AND gate 322 is supplied. As mentioned earlier, the ^ output produces of the flip-flop 321 a high level signal at the same time. As the input signals supplied to all input terminals are high level or signals representing a binary one, the AND gate 322 generates a high level output signal RP.

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This signal is applied to the reset terminal of reference counter 328 and supplied to the K input terminal of flip-flop 323. Accordingly the reference counter 328 is reset to zero and on the next clock signal the Q output of the flip-flop drops 323 generated output signal at a low level ah. This means that the various injection units are in one State that enables them to receive control or ignition signals, as already mentioned.

As already mentioned, in the meantime the signal source 3 ^ 0 has continuously the data input terminal of the flip-flop 325 is supplied with the DIST signal. When the clock signal is applied (C) the high DIST signal is in turn transferred from the input terminal to the Q output terminal of flip-flop 325 been. In addition, this signal is an input terminal of the AND gate 32? has been fed. In the meantime remains the flip-flop 326 in the set by the reset signal POR wrong state. During this one cycle time, the output signal DP from AND gate 327 is correct, since both inputs of AND gate 327 are correct. However, the next clock pulse (C) causes flip-flop 326 to set the Q output of the flip-flop 325, which is a correct signal to copy. The "Q" output of flip-flop 326 goes false which causes the signal DP from AND gate 327 becomes false. The flip flops 325 and 326, in conjunction with the AND element 327, form an edge detector for the DIST signal for a cycle time. That is, anytime the DIST signal transitions from false to right, the DP signal will generate a correct signal during a cycle time.

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The digital pulse signal DT is applied to the increment input terminal of the reference counter 328. The reference counter 328 is used to count the DP signals. This is done by applying clock pulses (C) to the clock input terminal of the counter 328 causes. Since the DP signal is only correct for each DIST signal during one cycle, the counter increments

328 only once for each DIST signal. In the preferred embodiment, the counter 328 counts modules n, where η is the number of DIST signals during one engine revolution. The reference counter 328 generates an output signal EEF which is fed to the circuit arrangement shown in FIG. 8, as will be explained later. The output signal REF is a Function of the number of DP pulses counted by counter 328.

Signal DP is also applied to the reset terminal of a timer 329. In this way the timer 329 , which is essentially a counter, is reset to zero by each distribution pulse DP. Essentially, the timer 329 counts at the clock frequency until the next DP signal, which resets the timer 329 to zero. If, on the other hand, a DP signal is not delivered in time, the timer 329 reaches a certain high count which, in this embodiment, is characterized by an output signal DT which consists entirely of binary ones. If this count is reached, the increment or increase input signal will be incorrect. That is, the output signal DT from the timer 329 is fed via the AND gate 331 to the inverter 330, which is again connected to the increment terminal of the timer

329 is connected. If each signal in the multi-bit output DT is a binary one, that generates

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AND gate 331 a positive or correct output signal. This Signal is sent to the data input port of the copy flip-flop 334 and the input terminal of the inverter 330. The inverter 330 processes this correct signal and generates an incorrect signal which is sent to the increment terminal of the Counter 329 is supplied. The supply of the wrong signal or signal consisting of a binary zero to the increment connection of the timer 329 has the effect that further counting of the clock signal C from the timer 329 is prevented. Hence will the state during which the signal DT consists entirely of binary ones is maintained until the next DP signal resets the timer 329.

When the AND gate 331 produces a proper output signal simultaneously with a DP pulse, the starting flip-flop 334 becomes "correct" is set and remains in this correct state until the signal from AND gate 331 simultaneously with a DP pulse wrong is. The starter flip-flop 334 is then also set incorrectly.

The starter flip-flop is set "correctly" when the time period between the DP pulses is sufficiently large that the timer 329 can reach the particular state in which the AND gate 331 is enabled. This indicates that the number of revolutions of the motor is below a certain threshold value. The particular timer state is selected so that the predetermined revolution threshold is just above the maximum Starting speed is. The starting flip-flop therefore indicates that the engine is either starting or stopping.

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The Q output of the starting flip-flop becomes false if the starting flip-flop is correct and prevents the AND gate 335 from generating a correct signal, which in turn prevents the Increment input to counter 337 becomes correct. Since that Starting flip-flop is clocked by the same signal that resets counter 337, the starting flip-flop becomes correct and prevents the counter 337 from continuing to count after the jog state.

The state detector 332 decodes a certain state of the Timer 329, which after a certain number of clock pulses and thus occurs after a specified period of time after each DP pulse. When discovered that particular condition is, the detector 332 generates an output signal DFT of the duration of one clock time, which is shown in FIG Circuitry is processed as described below.

The mode of operation of the circuit arrangement described is based on the assumption that different speed ranges or motor - speeds can be set. These speed ranges are the engine operating parameters and engine characteristics assigned. This information is used to determine the ignition time of an injection device in relation to the opening time of the intake valve of a particular cylinder. If the engine is running at a relatively low speed, the inlet valve is opened for a relatively long period of time, and the fuel to be injected can be in the correct time Way to be injected. On the other hand, if the engine is running at a relatively high speed, the inlet valve is only for one

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opened for a relatively short period of time, and the fuel must be injected into the system earlier to ensure that the fuel reaches the inlet valve at the right time for complete combustion. In the following table typical speed ranges are listed with the corresponding delay:

Deceleration speed range in rev / kin.

0 4500

1 3OOO to 45OO

2 2000 to 3OOO

3 1200 to 2000

4 700 to 1200

5 0 to 700

Of course, other speed ranges or limits can be set up if desired.

The speed ranges are labeled numerically so that a numerical (i.e. binary) designation is applied to them can. The appropriate name or number is assigned to each speed range. By taking advantage of the time the speed range can be recorded between the distribution pulses DP and suitable modifications of the various switching operations can be done.

The speed range parameters are determined, among other things, by comparing the pulse duration signal PW from the computer 12 with a pulse duration threshold value signal PWmvj from a suitable signal source

obtain. The signal source 342 can be any suitable Be a signal source, such as a read-only memory for generating a specified signal that lasts for a specified period of time, e.g. 20 milliseconds. This signal indicates the duration of the pulse width and sets its limits.

The signals PW and PW ₁₃ , - are fed to the digital comparator 338. The digital comparator 338 generates the output signal PWOK at its output connection. This signal is applied as an input to AND gate 335, which will be described below. If the signal PW ^ t- is greater than the signal PW, the signal PWOK is correct or represents a binary one. Conversely, the signal PWOK is incorrect if the signal PW is greater than the signal PW _{TJ ±} .

The threshold counter 337 receives the signal DP and is reset to zero by each DP signal. In the absence of an incrementing signal from the AND element 335, the (delay) signal emitted by the threshold value counter 337 is equal to zero and indicates a delay of zero. The delay signal is applied to the circuit arrangement shown in FIG. 8, as will be described below. In addition, the delay signal is fed to the threshold value memory 336. The delay signal emitted by the counter 337 is used to address a memory location in the threshold value memory 336. This memory contains thresholds or threshold values which increase as the delay address increases and generates an output signal DT _T "which designates a certain range of engine speeds, as already mentioned. When the counter 329 counts, the signal DT can go beyond the signal DT _TH ,

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which causes the counter 337 to increase. The next signal DT _T "(which is higher than the previous one) is then addressed until the signal DT again exceeds _{the signal DT TH.} At the time of the next DT pulse, but before the counter 337 is reset, the delay output of the counter 337 indicates the speed range in which the engine is running.

As already mentioned, the output signal is from the AND gate 331 is supplied to the data input terminal of the flip-flop 334. The flip-flop 334 is clocked by each signal DP. That The Q output of flip-flop 334 remains positive for this time or a binary one, such as signal DP, an all binary ones output generated by timer 329 is. This means that this signal has previously been correctly normalized in this circuit arrangement, so that the The condition "all bit positions equal to one" is only achieved if the engine speed is a sufficient amount below the Idle speed is so that the engine is either at a standstill is or is left on. Receives the AND element 335 signals, which consist entirely of binary ones, from the flip-flop 33 ^ »the comparator 338 and the comparator 333, a positive signal is applied to the increment input terminal of counter 337. The counter 337 is thus when there is an issue of a clock signal (C) is incremented (i.e. its count is increased).

FIG. 8 shows a block diagram and the logic combination of the ignition and injection control circuit. The distributor impulses DP will each have an input port of each

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AND gate 350, 354 and 358 supplied. The other input terminal of the AND gate 350 has an output terminal a digital comparator 352 connected. The other input terminal of AND gate 358 is with the other output terminal of the digital comparator 352 connected. The output terminal of AND gate 350 is with the incrementing one Input terminal of an up-Z-down counter 351 connected. The reset terminal of counter 351 receives the signal POR, while the clock input terminal of counter 351 is the Receives clock signal (C). The down-counting input terminal of the counter 351 is connected to the output terminal of an AND gate 356 as described below.

The output terminal of the counter 351 is connected to an input terminal of a subtraction circuit 360 as well as to the A input terminal of the digital comparator 352 is connected. The B input port of digital comparator 352 receives the delay signal from counter 337 in Figure 7. The digital comparator 352 compares "servo" and delay signals and generates output signals that are the result of that comparison represent. If the delay signal is greater than the servo signal, then a signal consisting of a binary one becomes the AND gate 350 and an input terminal of an inverter 353 are supplied. Conversely, if the servo signal is greater than that Delay signal, the AND gate 358 becomes a positive Signal supplied.

The output terminal of the inverter 353 is connected to an input terminal of the AND gate 354. The other input— Connection of AND gate 354 receives the distributor pulse signal DP. The output terminal of the AND gate 354 is with

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one input terminal of an OR gate 355 is connected.

The output terminal of AND gate 358 is connected to the J input terminal of a J-K-Plip-Plop 357 connected. The clock connection of the flip-flop 357 receives the clock signal (C). The Q output terminal of the flip-flop 357 is one with an input terminal AND gate 356 connected. The signal DFT from the state detector 332 in Fig. 7 becomes another input terminal of the AND gate 356 supplied. The output terminal of AND gate 356 is to the K input terminal of flip-flop 357, with a second input terminal of the OR gate 355 and to the down-counting input terminal of the up-Z-down counter 351 connected. The output terminal of the OR gate 355 outputs the ignition signal to an AND gate 366 via an AND gate 367 as described below.

According to the circuit arrangement according to FIG. 9, the subtracter takes or subtracter 36O counteracts signal REF from counter 328 shown in FIG. In addition, the subtracter receives 36O the signal SERVO from up / down counter 351. The output terminals of the subtracter 36O are connected to the input terminals of a decoder 36I. The decoder 361 is a "one of N" decoder, where N is the number of injectors and injector driver circuits used designated. For example, N = 8. One input terminal of each logic gate 366 and 367 (representing two of N AND gates) are each connected to a separate N output terminal of decoder 361. the other input terminals of the gates 366 and 367

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are commonly connected to the output terminal of the OR gate 355 to receive the ignition signal. The output connectors of gates 366 and 367 are connected to the J input terminals of J-K flip-flops 368 and 369, respectively (the two of N flip-flops).

The pulse duration signal PW of the computer 12 becomes the B input terminals from digital comparators 362 and 364 (representing two of N digital comparators). The A input terminals the digital comparators 362 and 364 are with connected to the output terminals of counters 363 and 365, respectively. The incrementing input terminal of counter 363 is with connected to the Q output terminal of a flip-flop 368. The ^ output terminal of flip-flop 368 is connected to the reset input terminal of the counter 363 connected. The clock connection of the counter 363 receives the clock signal (C ^. The links between flip-flop 369 and counter 365 are similar to the links between the flip-flop 368 and the counter 363. In addition, the output from the flip-flop 323 shown in Fig. 7 is output The clear signal is supplied to the clear or quiescent terminals of the flip-flops 368 and 369, respectively.

Basically, the logic circuit shown in FIG. 8 generates Ignition pulses, which the corresponding injectors due to at the right time during engine rotation a pulse duration PW and the engine speed. In other words, when the vehicle is running, cause sudden Changes in the speed Changes in the pulse duration signal PW. As already mentioned, the threshold counter 337 generates a specific signal that addresses the threshold memory 336

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and generates a signal that indicates a specific speed range. A sudden change in speed or speed the speed could cause the threshold value memory 336, Generate an additional (or insufficient) speed range signal. The signal could then be used during recirculation generate a delay signal pulse with incorrect information through the circuit. For example, suppose that the Vehicle was operated in a certain speed range, e.g. in speed range 1. This speed range would cause the generation of a delay signal that causes the ignition pulses to be triggered by a distributor pulse, which e.g. can be the distributor impulse for cylinder 2. If the engine speed changes in such a way that it is in a speed range which requires that the pulse be triggered by the distributor pulse for cylinder 1, it can be seen that the distributor pulse for cylinder 1 has already passed, and it would be impossible to fire the injector to ensure that the fuel is in the correct cylinder injected at the right time.

Conversely, it is conceivable that the injection system would attempt to use the same injector during one Ignite twice the engine cycle, which would add twice the amount of fuel to a given cylinder than required is.

In the following description, the cylinders are in their firing order numbered. If the operating state of the engine requires an injection delay of zero (delay signal = O at the end of a DP interval), the ignition logic generates

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circuit ignition and SERVO signals, so that the injection process for cylinder 1 is initiated by the distributor pulse for cylinder 1 the injection process for cylinder 2 from the distributor pulse for cylinder 2, the injection process for cylinder 3 from the distributor impulse for cylinder 3 etc.

If the operating state of the engine requires a delay of a distributor pulse before the injection (ie, delay signal = i at the end of a DP interval), ignition and SERVO signals are generated so that the injection process for cylinder 1 is carried out by the distributor pulse for cylinder 2 is initiated, the injection process for cylinder 2 by the distributor pulse for cylinder 3, the injection process for cylinder 3 by the distributor pulse for cylinder k, etc. The relationships in the case of larger delays arise accordingly.

The linking elements 350, 351, 352, 353, 354, 355, 356, 357 and 358 ensure that one and only one injection occurs during one engine revolution per cylinder, in particular when the delay changes due to changes in the operating condition of the engine.

One of the main tasks of electronic fuel injection directions is to achieve the most complete possible combustion of the fuel in the engine, and thus pollution largely to reduce. It is therefore for the most complete possible combustion and low emissions It is very important that the fuel is injected into each cylinder once and only once during an engine revolution. the actual to be used to ignite the injection device

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Therefore, the delay is regulated with a calculated delay such that changes in the delay are controlled can. However, the rate of change of the delay is limited to one by the distributor pulse. As can be seen, it takes place with uniform operation, one fuel injection per distributor pulse DP. However, if the delay falls by one Distributor pulse from the ignition angle, are during a distributor pulse interval two injectors ignited. This has the effect of reducing the delay by one distributor pulse will be changed. Conversely, if the delay is greater by one distribution pulse of the timing angle, then the result is a Manifold Pulse Interval when no injectors are fired.

In addition, it is stipulated that the driver circuits for the injectors have a recovery time which is observed must become. This means that every time an injection device is activated by applying a signal to the injection device Driver circuit is switched on, must have a certain recovery time be provided before another injection device can be switched on. This limitation is has been taken into account in the operation of the logic circuits shown in FIG.

In operation, the signal POR is applied to the counter 351 to reset the counter to zero. Accordingly, the output signal SERVO is equal to zero. Then the distributor pulse signal DP fed to AND gates 350 and 358. As long as the delay signal and the SERVO signal are the same, i.e.

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are identical, a condition B greater than A or A greater than B does not occur in the digital comparator 352. For this Reason, neither the AND gate 350 nor the AND gate 358 are released. The SERVO signal therefore remains in the zero state. This condition is the same as the zero delay generated by the threshold counter 337 and the speed range Indicates zero.

Thus, when the delay signal is the same as the SERVO signal, the SERVO signal remains unchanged. This creates an ignition signal or command generated by a distributor pulse signal DP. That is, the inverter 353 receives an incorrect input signal from the digital comparator 352. This signal is inverted, and a correct signal is fed to the AND gate 35 ^ which is thereby released. Thus, when the signals DP to the AND gate 35 ^ and substantially identical signals to the OR gate 355 are supplied, the ignition signal is generated by the OR gate 355 as a result.

If as a result of a change in the engine operating condition the delay signal is greater than the SERVO signal, "B is greater than A" of the digital comparator at the output terminal 352 generates a binary one. This signal is fed to the AND gate 350 and enables the AND gate 350, whereby the next signal DP to the incrementing connection of the forward / Down counter 351 is supplied. Accordingly, the SERVO signal is incremented or raised by one, a Ztind command however, it is not generated. That is, the "B greater than A" signal, a binary one, is inverted by inverter 353, whereby the AND gate 35 ^ is blocked and the signal DP is not transmitted

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will wear. During this period of time in question, i.e., during this part of the engine revolution, therefore, no injector is activated ignited.

On the other hand, if the delay signal is smaller than the SERVO signal, an ignition command or signal is generated by the OR gate 355, and the delay ignition flip-flop 357 is set to the "one state". Thus, if condition A is greater than B, a signal consisting of a binary one is fed to AND gate 358 in order to enable AND gate 358. The next signal DP therefore runs through the AND gate 358 and is fed to the J input of the flip-flop 357. At the next clock signal, the signal present at the J input connection of the flip-flop 357 and consisting of a binary one is transmitted and fed to an input connection of the AND element 356. In this way, the AND gate 356 is enabled by the signal from the flip-flop 357. If the state detector 332 (see FIG. 7) determines that the output of the timer 329 has a corresponding count, the detector 332 generates the detection signal DFT, which becomes correct, and the AND gate 356 is enabled, whereby the OR gate 355 a second Ztind command is generated and the counter 351 is counted down. This enables two injections in two different cylinders using the same distributor pulse and reduces the delay for the second injection by one distributor pulse. These injections are also separated from one another by a time interval which is determined by the state detector 332 and which allows the injection driver circuit a recovery time between the first and second injections.

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The ignition command or the ignition signal is assigned to the AND gates 366 and 367 supplied as described. The other signals applied to AND gates 366 and 367 are provided by the decoder 361 delivered. The decoder 361 processes the difference of the signal REF and the servo signal in order to determine in which cylinder by applying the next ignition pulse an injection is to be carried out. This means that the reference signal REF shows the distributor pulse position relative to the motor rotation run while the SERVO signal is determined by the status of the motor operating state is set and determines whether the injection timing should be accelerated or not, and in case of acceleration by what amount.

Are the ignition signal and the signal for the injection device on, whereby the AND gates 366 and 367 set the associated flip-flops 368 and 369, respectively, then becomes a drive signal the injection driver circuits 370 or 371 (the two of N represent injection driver circuits) supplied. These signals emitted by the flip-flops remain in the "on" state, whereby the injection driver circuit remains in the "on" state until the counter associated with the flip-flops counts up to a signal that is equal to or greater than the pulse duration signal PW. If the counter (preferably a Timer) a signal that is larger or higher than the signal PW, the digital comparator generates a binary An existing signal that is connected to the I input terminal of the associated Flip flops is fed. Therefore, the flip-flop is triggered with the next clock signal, so that the zero output signal is generated and the corresponding counters 363 to 365 resets as well as the signal to the corresponding injection

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Driver circuits 370 to 37i terminated.

Of course, while the injector driver circuits are in operation, the injector is operative to provide fuel inject into the engine. As mentioned earlier, the fuel gets into the engine at the right time and during a appropriate length of time, so that the correct amount of fuel is injected according to the operating condition of the inlet valve is injected into the engine. Furthermore, mostly only one injection from an injection device during one Engine revolution made. The control of the emission is thus greatly improved and a better working one or «, cleaner burning engine is obtained.

According to the invention, there is thus an electronic fuel injection device created which in a much improved manner the injection of fuel into the engine and causes the correct mixture formation. The inventive Circuitry controls the mixing of fuel with air as a direct function of the injection pulse based on the motor revolution. The circuit arrangement can be made by using standard logic circuits and integrated Realize circuit technology.

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Claims (1)

- 76 claims ί i. ^ Electronic fuel injection device, characterized ^ - ' by a plurality of signal sources, by a control device, by logic elements which are connected in such a way that they receive signals from the signal sources and the control device, by a data storage device which is connected in such a way that it receives signals from the logic elements and outputs information from memory locations, which are addressed by the signals of the logic elements, through an accumulator device that receives information from the memory locations and processes the information to generate sum signals, through an output memory device that is associated with the Accumulator means is connected to receive and process a first part of the sum signals and to provide an output storage signal as a function of the part of the sum signals fed to the output storage means, and by an output register means which is connected in such a way that si e receives the output memory signal and a second part of the sum signals from the accumulator device in order to selectively change the output memory signal previously stored in the output register device. 2. Electronic fuel injection device according to claim 1, characterized in that a memory device with the Accumulator device is connected to current information from the accumulator device during input new information to be sent to the accumulator device 409847/0274 store and the current information subsequently the accumulator device for the purpose of combination with the in the Accumulator device to supply stored new information again. 3. Electronic fuel injection device according to claim 1, characterized in that a function memory device is connected to the accumulator device and the control device, whereby the in the accumulator device Information located as an address signal for the function memory device acts, and that the function memory device is connected in such a way that the on of the Address signal addressed memory location located information of the accumulator device is supplied. k. An electronic fuel injection device according to claim 1, characterized in that the control means comprises program storage means and program address counter means, the program address counter means comprising a non-synchronized counter which selects the program storage means by that in it stored command program switches to control the functions of the entire system. 5. Electronic fuel injection device according to claim 1, characterized in that each memory device has a Having a plurality of storage locations, and that each storage device is a read-only memory in which at each Storage location a certain information is stored. 09 847/0274 6. Electronic fuel injection device according to claim 1, characterized in that a standardizing device is connected to the data storage device and the accumulator device to store the information from process and modify the memory locations, before they are fed to the accumulator device, and that a logic combination circuit with the logic elements and the accumulator means is connected to the signals from the logic gates process and the memory locations addressed by the signals of the logic combination circuit in the Change data storage device. 7. Electronic fuel injection device according to claim 1, characterized in that the signals and the information are supplied in digital form. 8. Electronic fuel injection device according to claim 1, characterized in that the accumulator device of the data storage device receives address signals feeds. 9. Electronic fuel injection device according to claim i, characterized in that the output storage device supplies information signals to the accumulator device. 10. Electronic fuel injection device according to claims 1 to 9, characterized by a signal voltage device, by a feedback voltage device, by one with the signal voltage device 409847/0274 and comparator means connected to the feedback voltage means by one of the comparator means connected counting device for generating a control signal, through a signal transmission device, which is connected to the counter in order to change its mode of operation as a function of the control signal an accumulator for receiving the signals from the signal transmission device, by an adder which is connected in such a way that the content of the adder becomes the content of the accumulator is added at a first periodic rate and that the content of the counter is added to the content of the accumulator is added at a second periodic rate, and by switching means connected to the adder, which is thereby excited to selectively control the operation of the feedback voltage device steer. 11. Electronic fuel injection device according to claim 10, characterized in that the feedback voltage device has a low-pass filter device. 12. Electronic fuel injection device according to claim 10, characterized in that the counting device is an up / down counter. 13. Electronic fuel injection device according to claim 10, characterized in that the signal voltage device has a voltage divider device connected to a voltage source, and that the voltage 4098A7 / 0274 divider device has at least one variable component which emits the signal voltage. lh. An electronic fuel injector as claimed in claim 10, characterized in that the switching means selectively connects a reference voltage source to the feedback voltage means to change the value of the feedback voltage. 15. Electronic fuel injection device according to claims 1 to 9, characterized by a circuit, which generates a sawtooth signal, through a voltage divider network, through at least one comparator circuit, connected to the sawtooth signal generating circuit and the voltage divider network to generate a signal that is the relationship between those generated by the sawtooth generator and those generated by the voltage divider network signals generated by a logic circuit that is connected to the comparator circuit to generate an output signal which is a function of the signal generated by the comparator circuit, and by recirculating register means for generating an output signal indicative of the digital signal, wherein the recirculating register device is connected to the logic combination circuit, so that their Operation is controlled by the signals generated by the logic circuit. 16. Electronic fuel injection device according to claim 15j, characterized in that the voltage divider device has several impedances, of which at least 409847/0274 At least one is variable that the voltage divider device several different voltages generated by the return voltage device has an RC circuit, and that a separate comparator means the Feedback voltage with each of the various voltages compares. 17. Electronic fuel injection device according to claim 15, characterized by an output register which Supplies output signals to a user device a first register means which selectively supplies part of its contents to the output register by a first adder for receiving the part of the content of the first register device, by a second register device, which is connected in such a way that it selectively receives the content of the first adder, the Content of the first adder is the sum of the content of the second register device and that part of the content of the first register means, and by a second adder for adding the contents of the first register means to the content of the second register device and for the selective storage of the same in the first Register facility. 18. Electronic fuel injection device according to claim 17, characterized in that the first register device has a part for bits of highest significance and has a part for least significant bits, the part of the content of the first register being the bit part represents the highest value as well as an overflow condition. 40984 7/0274 19. Electronic fuel injection device according to claim 18, characterized in that a logic combination circuit is connected to the comparator means and the register means to their operation control, whereby the register means at different times as a function of that of the comparator means generated output signal acts. 20. Electronic fuel injection device according to claim 17, characterized in that a detector device is connected to the first register to the To receive part of its content, and that the detector means a control signal according to a predetermined State of the part of the content of the first register device generated, the control signal serving to activate the output register. 21. Electronic fuel injection device according to claims 1 to 20, characterized by a device for the supply of pulses of different periodicity, through a device for generating control signals corresponding to the pulses, by means for counting the control signals and generating corresponding ones Function signals, and by a device for receiving the control signals and the function signals for generation an output signal. 22. Electronic fuel injection device according to claim 21, characterized in that the device for Generation of control signals having first and second logic combination circuits, which the different 4098A7 / 0274 Receive pulses that the first logic combination circuit generates at least two control signals that the trains led impulses correspond and that the second logic combination circuit generates a third control signal, which corresponds to the supplied pulses. 23. Electronic fuel injection device according to claim 22, characterized in that the counting device has a first counter which receives the third control signal from the second logic combination circuit and one of the two control signals from the first logic combination circuit receives that the counting means has a second counter for counting at a controlled rate, until the third control signal is periodically reset to a predetermined state, and that the counting means comprises a third counter for counting at a controlled rate, corresponding to one Condition that is generated in response to at least one of the function signals until a reset to a predetermined one State is carried out by the third control signal. 2h, electronic fuel injection device according to claim 23, characterized in that a comparator device is connected to the second and third counting device in order to generate a signal which controls the predetermined state. 25. Electronic fuel injection device according to claim 24, characterized in that the receiving device another counting device for the selective counting of the third control signals as well as another counting device 409847/0274 has the same device, which with the further counting device and the third counter is connected to generate a control signal indicative of the relationship between indicates the signals generated by the third and further counting means in order to generate an output signal to control. 26. Electronic fuel injection device according to claim 25, characterized in that a subtracter- device is connected to the first counting device and the further counting device by the counting devices to subtract generated signals from each other, and that a decoder with the subtracter is connected to generate enable signals on selected user devices, with multiple user devices. services are available. 409847/0274