GB1569866A - Semiconductor devices and methods of fabricating them - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THEM (71) We, THE GENERAL ELECTRIC COMPANY LIMITED, of 1 Stanhope Gate, London W1A lEH., a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performd, to be particularly described in and by the following statement: This invention relates to methods of fabricating semiconductor devices and to devices fabricated by these methods.

The invention is particularly concerned with the fabrication of silicon gate semiconductor devices of the kind having in a semiconductor substrate a channel region with source and drain regions at opposite ends thereof and a doped polycrystalline silicon gate electrode structure overlying the channel region and insulated from the substrate by dielectric material, so that the storage and/or transfer of charge within the channel region may be controlled by potentials applied to the electrode structure. Devices of this kind will hereinafter simply be referred to as silicon gate semiconductor devices of the kind specified.

One method of fabricating a silicon gate charge coupled semiconductor device of the kind specified is described in IEEE Transactions on Electron Devices, Vol.

ED-21, No. 12, December 1974 on pages 758 to 767 by Bertram et al. This method comprises first forming a layer of silicon dioxide on one surface of a semiconductor silicon substrate and then forming over this layer a three-level, polycrystalline silicon electrode structure. Each level is formed by depositing a layer of doped polycrystalline silicon (hereinafter referred to simply as polysilicon) on the surface of the device, thermally growing a masking oxide layer thereon, etching it, and then the polysilicon, into a desired pattern, removing the oxide mask and thermally growing an oxide layer on the resulting electrode pattern.

When all the polysilicon electrode levels are formed, contact windows are opened to each of the polysilicon levels and to the source and drain regions, after which a metal conductor is deposited over the contact windows and etched into a desired pattern to provide large features such as bonding pads and high conductivity bus lines.

Although this method of fabrication achieves good results, it also has a number of disadvantages.

As is well known in the fabrication of silicon gate semiconductor devices of the kind specified, due to unavoidable impurities or defects, pin holes appear in the polysilicon structure which, during the various oxide etches used to form the electrode structure and contact windows therefor, permit oxide etchant to penetrate through to, and form a hole in, the underlying oxide insulation which it is intended to mask. Upon subsequent deposition of the metal conductor pattern, if such a pin hole exists in an area of polysilicon exposed by a contact window, the deposited metal will penetrate through the pin hole in the polysilicon and the hole in the underlying oxide insulation, causing either a short circuit to the substrate, or if such an area of polysilicon overlies a lower level of polysilicon, an interlevel short circuit.

The regions of the polysilicon electrodes exposed by the contact windows normally comprise polysilicon bus lines interconnecting a plurality of gate electrodes in the same polysilicon level extending over the channel region. In devices having a large number of electrodes e.g. charge coupled devices, the polysilicon bus lines need to be fairly long, and due to the limited conductivity of doped polysilicon impair the high frequency performance of such devices.

In order to reduce this problem, metal bus lines, usually formed in the metal conductor layer are provided which make contact with the polysilicon bus lines through elongate slit contact windows extending along the length thereof as described in the above-mentioned article by Bertram et al. These provide high conductivity paths in parallel with the polysilicon bus lines and thus improve the high frequency performance of the device.

In some cases it is necessary or desirable for design reasons, for the polysilicon and associated metal bus lines of an upper level of polysilicon to overlap one or more regions of a lower level of polysilicon thus rendering the device susceptible to interlevel short circuits which may be formed under the contact windows in the manner described earlier.

According to the present invention a method of fabricating a silicon gate semiconductor device of the kind specified includes forming said electrode structure including at least two overlapping levels of polysilicon each comprising a plurality of electrode elements interconnected by a bus line; forming a metal conductor pattern in contact with the electrode structure through contact windows to provide a respective high conductivity path in parallel with and extending along each said polysilicon bus line; and arranging each said contact window over an area of polysilicon which does not overlap a lower level of polysilicon.

Preferably the or each bus line except the lowest level bus line overlies the electrode elements of the or each lower level.

A silicon gate charge coupled semiconductor device, and a method of fabricating it in accordance with the present invention will now be described by way of example only, with reference to the accompanying drawings of which Figure 1 shows diagrammatically a longitudinal section through the charge coupled device; Figure 2 shows diagrammatically a plan view of part of the device shown in Figure 1; and Figure 3 illustrates schematically various stages in a method of fabricating the device shown in Figure 1 and 2.

Referring to Figures 1 and 2 of the drawings, the device comprises a p-type silicon semiconductor substrate 1 on the surface of which is a first insulating layer 2 of silicon dioxide partilaly covered by a second layer 3 of silicon nitride. The insulating layers 2, 3 comprise a central gate insulation region 4 which overlies a charge transfer channel 5 (shown in dotted lines in Figure 2) at the surface of the substrate 1, surrounded by a field insulation region 6 in which the silicon dioxide layer 2 is thicker than in the gate insulation region.

At opposite ends of the channel region 5 are a charge source and a charge drain in the form of an input diode 8 and output diode 9, each diode comprising an n-type diffusion 10 in the substrate 1 contacted through a window 11 in the overlying insulation oxide layer 2 by a respective metal conductor 12, 13.

Overlying the insulation layers 2, 3 is a gate electrode structure comprising three mutually insulated levels of polysilicon.

This electrode structure provides gate electrodes 15, 16 for controlling charge flowing from and to the input and output diodes 8, 9, respectively and a three-phase transfer gate electrode pattern. Each phase of the pattern comprises a bus line 24, 25, 26 running parallel with the transfer channel 5 but overlying the field insulation region 6, and connecting in common a respective plurality of spaced parallel transfer gate electrodes 20, 21, 22 extending transversely across the channel region 5 above the gate insulation 4. The bus lines 24, 25, 26 are positioned so as each to overlie a different area of the field insulation region 6.

Each level of polysilicon is covered by its own layer of silicon dioxide 27 to provide mutual insulation between the phases and for protection. Associated with each polysilicon bus line 24, 25, 26 is a respective high conductivity metal bus lines 24a, 25a, 26a, running in parallel with its associated polysilicon bus line and in contact therewith through respective contact windows 24b, 25b, 26b in the insulating layers 27 of silicon dioxide. As shown in Figure 2, the metal bus line 26a for the lowest level polysilicon bus line 26 makes contact through a single slit contact window 26b extending substantially along the whole length thereof, while in the case of each of the other metal bus lines 24a and 25a and their associated polysilicon level bus lines 24 and 25, contact is made through a respective plurality of contact windows 24b, 25b spaced along the length thereof so as, in accordance with the invention.

not to overlie any areas of polysilicon of the lower polysilicon levels.

This spacing of the contact windows 24b, 25b for the higher level polysilicon bus lines 24, 25 in accordance with the invention reduces the possibility of interlevel short circuits due to pinholes as described earlier. The metal bus lines 24a, 25a 26a provide a high conductivity electrical path in parallel with the polysilicon bus lines, which due to their limited conductivity would otherwise impair the performance of the device, particularly at high frequencies.

A method of fabricating the 3-phase charge coupled device described above with reference to Figures 1 and 2 will now be described, with reference also to Figure 5 which illustrates various stages in the method. The vertical scale of Figure 3 is distorted for clarity.

Referring first to Figure 3(a), the n-type diffusion regions 10 (only one of which is shown) for the input and output diodes 8, 9 are formed in the p-type silicon substrate 1 using a thermally grown oxide mask produced in known manner by a well known photolithographic process. This oxide mask is then removed and the first insulation layer 2 of silicon dioxide is thermally grown over the surface of the substrate 1, to a thickness of 1000 over the central channel region 5 (Figure 2), i.e. the gate insulation region 4, and elsewhere, i.e. the field insulation region 6, to a thickness of 2000 .

The second insulating layer 3 of silicon nitride is then deposited to a thickness of 500A over the oxide insulating layer 2, followed by a 5000-7000 thick layer of polysilicon which is then doped with phosphorous to render it conductive. The nitride layer 3 acts as a barrier to the phosphorous dopant to prevent it from penetrating through the underlying oxide layer 2 to the substrate 1.

An oxide masking layer is then grown over the polysilicon and etched using standard photolithographic techniques into a mask pattern corresponding to the desired pattern of the phase two electrodes 21, the bus line 26 and the input and output gates 15, 16 for the diodes 8, 9, and the device is then treated first with a polysilicon etchant to remove all exposed areas of polysilicon, and then with an oxide etchant to remove the masking oxide layer to leave only the required polysilicon electrode pattern on the surface of the nitride layer 3.

A layer 27 of insulating silicon-dioxide 1 000A thick is then grown on the electrode pattern as illustrated in Figure 3(b).

This polysilicon deposition, etching and oxidation process is then repeated twice to produce the second and third levels of the electrode structure which provide the phase one and phase three transfer electrodes 20, 22 and their bus lines 24, 25.

As described above, the nitride layer 3 protects the underlying oxide insulation layer 2, which is particularly important in the region underlying the gate electrodes 20, 21, 22, from the oxide and polysilicon etchants used to form the polysilicon electrode structure, and to prevent additional growth of oxide on the layer 2 during the thermal growth of the oxide insulation coatings 27 on the polysilicon electrodes.

This serves to maintain an even thickness of gate insulation between the gate electrodes 20, 21, 22 of each phase, or poly silicon level.

Having formed the oxide insulation coating 27 on the last polysilicon electrode pattern, the entire device is dipped in a nitride etchant, e.g. orthophosphoric acid, to remove all exposed areas of the nitride layer 3 as shown in Figure 3(c) using the existing electrode structure as a mask.

A photoresist contact window mask is then formed on the upper surface of the device having apertures therein corresponding to the diode contact window 11, contact windows 19 to the input and output gates 15, 16, and the contact windows 24b, 25b, 26b to the polysilicon bus lines 24, 25, 26 respectively. The device is then treated in an oxide etchant bath for a period sufficient only to etch through the 1000fez thickness of the respective gate oxide layer 2 and coatings 27, to form the said contact windows, and the photoresist mask is removed.

A layer of aluminium is then deposited over the upper surface of the device and photolithographically etched to form a conductor pattern providing lead-in conductors 18 and 12 to the input and output gates 15, 16 and the input and output diodes 8, 9, respectively, and the bus lines 24a, 25a, 26a for the three phases of the polysilicon electrode structure.

The metal conductor pattern may then be sintered, after which the device is subjected to an annealing process to remove harmful surface states at the boundary between the gate insulation oxide 2 and the substrate 1 in the channel region 5.

The annealing process comprises subjecting the device to forming gas, a mixture of hydrogen and nitrogen, at a temperature of 435"C for a time sufficient for the hydrogen to penetrate through the whole of the channel region. In this respect the width of the nitride layer overlying the channel region is important as, if it is too wide i.e.

greater than 200 microns, it inhibits the penertation of the forming gas to the whole of the channel region 5.

In a modification of the above method, instead of relying on the presence of the electrode structure to act as a mask for the nitride etchant a separate mask of vapour deposited silicon dioxide may be formed before the formation of the oxide coating 27 on the third polysilicon electrode pattern. This mask may be formed with windows exposing the nitride layer 3 over the source and drain regions 10 only, or it may simply cover the existing electrode structure so as to expose all areas of the nitride layer 3 surrounding the electrode structure.

The areas of the nitride layer 3 exposed by the vapour deposited silicon dioxide mask are then etched away, the mask re moved, and the oxide coating 27 then formed on the third polysilicon electrode pattern. The fabrication method is then completed as before with the formation of all the contact windows and the deposition of the metal conductor pattern.

The use of a vapour deposited mask is not necessary, but is preferred since it reduces the possibility of short circuits forming through "pinholes" in the polysilicon electrode structure covered by the mask.

Certain features of the method of fabrication described above are claimed in our co-pending patent application No. 47273/ 75 (Serial No. 1569865).

WHAT WE CLAIM IS: - 1. A method of fabricating a silicon gate semiconductor device of the kind specified including forming said electrode structure including at least two overlapping levels of polycrystalline silicon each comprising a plurality of electrode elements interconnected by a bus line, forming a metal conductor pattern in contact with the electrode structure through contact windows to provide a respective high conductivity path in parallel with and extending along each said polycrystalline silicon bus line; and arranging each said contact window over an area of polycrystalline silicon which does not overlap a lower level of polycrystalline silicon.

2. A method according to claim 1 wherein the or each bus line except the lowest level bus line overlies the electrode elements of the or each lower level.

3. A method of fabricating a silicon gate semiconductor device of the kind specified substantially as hereinbefore described and shown in Figures 1 and 2 of the accompanying drawings.

4. A silicon gate semiconductor device of the kind specified fabricated by a method according to any preceding claim.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. formed on the third polysilicon electrode pattern. The fabrication method is then completed as before with the formation of all the contact windows and the deposition of the metal conductor pattern. The use of a vapour deposited mask is not necessary, but is preferred since it reduces the possibility of short circuits forming through "pinholes" in the polysilicon electrode structure covered by the mask. Certain features of the method of fabrication described above are claimed in our co-pending patent application No. 47273/ 75 (Serial No. 1569865). WHAT WE CLAIM IS: -

1. A method of fabricating a silicon gate semiconductor device of the kind specified including forming said electrode structure including at least two overlapping levels of polycrystalline silicon each comprising a plurality of electrode elements interconnected by a bus line, forming a metal conductor pattern in contact with the electrode structure through contact windows to provide a respective high conductivity path in parallel with and extending along each said polycrystalline silicon bus line; and arranging each said contact window over an area of polycrystalline silicon which does not overlap a lower level of polycrystalline silicon.

2. A method according to claim 1 wherein the or each bus line except the lowest level bus line overlies the electrode elements of the or each lower level.

3. A method of fabricating a silicon gate semiconductor device of the kind specified substantially as hereinbefore described and shown in Figures 1 and 2 of the accompanying drawings.

4. A silicon gate semiconductor device of the kind specified fabricated by a method according to any preceding claim.