GB1565717A - Line signalling transmission in a pcm exchange - Google Patents

Description

(54) LINE SIGNALLING TRANSMISSION IN A PCM EXCHANGE (71) We, INTERNATIONAL STANDARD ELECTRIC CORPORATION, a Corporation organised and existing under the Laws of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to the transfer of line signalling in a PCM (Pulse Code Modulation) exchange.

It is common practice to transmit line signalling data over a definite time channel of each PCM junction. Thus, for example, for junctions having thirty-two time channels, this fixed channel could be channel 16. In order to be transferred from the central control unit to channel 16 of the junctions, and vice-versa, the line signals pass through the space-time switch of the central exchange, within which a path is temporarily assigned to them. Passing line signalling data through the switch has the disadvantage of requiring a reconfiguration of paths in case of failure of a part of the switch or of a line signalling unit having access to an input of the switch.

An object of this invention is a line signalling transfer device avoiding this drawback.

According to the invention there is provided an automatic telecommunication exchange in which connections are set up in TDM manner using PCM, in which the exchange includes group equipments each of which serves q multiplex junctions, in which each of the multiplex junctions conveys r time channels outside the exchange while on the inside of the exchange each group equipment has a multiplex super-junction conveyingqr time channels of duration t on the space-time switch side, in which a line signalling unit is provided for responding to signals from the channels on the junctions and for sending signals to those channels, in which p serial transmission buses are provided to connect the line signalling unit respectively to each said group equipment, which serial transmission buses do not pass through the space-time switch, and in which each bus transmits over two separate lines, one per direction, the line signal bits of the q multiplex junctions of its one of the group equipments.

An embodiment of the invention will now be described with reference to the attached drawings in which: Figure 1 shows the general lay-out for the transfer of line signalling data in a PCM exchange embodying the invention; figure 2 is a more detailed drawing showing the line signalling transfer chain between a computer and the group equipments; figure 3 shows an interface circuit between a multicontroller and the serial transmission buses; figure 4a to 4c present time diagrams; figure 5 shows an interface circuit between a group equipment and the serial transmission buses; figures 6a to 6h present time diagrams.

In figure 1 a space-time switch C, of the time-space-time (TST) type, is connected to p group equipments GE(O) to FE(p-1) through p multiplex super-junctions SJ(0) to SJ(p - 1).

In addition, each group equipment is connected to q multiplex junctions J(0) to J (q - 1) allowing communication with the outside. Each multiplex junction contains r time channels and transmits r successive coded words within a repetition period of frame T. Each word occupies a particular time channel within the frame T and contains b bits. Serial transmission is used over the multiplex junctions and parallel transmission over the multiplex superjunctions. Group equipments GE(0) to GE (p - 1) have the function of carrying out the serial-to-parallel conversion of words and the multiplexing of the q multiplex junctions in the junction switch direction, and the reverse operations in the switch junction direction.Each multiplex super-junction transmits s words (s = q.r) during s equal time slots t(o) to t (s - 1) of duration t within one frame T. The following numerical values are given as an example: b = eight bits r = thirty-two time channels T = 125,us q = eight multiplex junctions s = two hundred fifty-six time slots t = 488 ns.

The multiplex junctions are connected to the voice-frequency network by conversion units MUX performing the digital-to-analog conversion of speech codes and the demultiplexing of the time channels in the PCM network voice-frequency network direction, and vice-versa in the other direction. Taking into account that two fixed time channels are reserved for synchronization and for line signalling (e.g. channels 0 and 16 as defined by the CEPT, i.e. the "Comite European des Postes et Telecommunications"), there remain (r - 2) channels for conversation. Each unit MUX is connected to (r - 2) voice-frequency lines L by means of (r 2) line circuits JCT. These line circuits are controlled by a scanner-driver JSD connected to the unit MUX through which it receives the line signalling.

Two load-sharing computers, CUA and CUB, control the exchange. In particular, they deliver orders to the scanner-drivers and receive results from them. This interchange of data constitutes the line signalling. Two identical line signalling units SILA and SILB are connected respectively to the computers CUA and CUB through input-output units IOSIA and IOSIB.

The function of units SILA and SILB is to adapt the data coming asynchronously from units IOSIA and IOSIB for PCM transmission on the multiplex network, and vice-versa in the other direction. Thus, a complete signalling message assigned to a scanner-driver appears at the output of the units SILA and SILB as a set of several words of b bits to be transmitted during several successive frames (multi-frame signalling) on the signalling channel of the corres ponding junction. The line signals coming from units SILA and SILB are sent directly to the p group equipments GE(0) to GE (p - 1), and vice-versa, without passing through switch C.

Units SILA and SILB, paired for security, are connected to the same group equipments and operate alternatively by time division. Register signalling passes through switch C, and is exchanged between the switch and the input-output units IOSIA and IOSIB through a register signalling unit SIR.

Figure 2 is a more detailed diagram showing the line signalling transfer chain between a computer, e.g. computer CUA, and the group equipments. The signalling unit SILA contains v identical multicontrollers MC(0) to MC(v - 1). Each multicontroller is equipped, in the conventional way, to handle the line signalling of n multiplex junctions, and is connected to m group equipments by m transmission buses such as B(0) to B(m - 1) for the multicontroller MC(0). The number v of multicontrollers must be equal to at least p/m, to be able to handle the line signalling of all of the multiplex junctions. Thus, for m = 32 and p = 128, we will have v = 4.

The interchange of data between each multicontroller and the input-output unit IOSIA is carried out in parallel form. The transmission of multicontroller output data, on the PCM network side, is carried out in parallel form by means of b conductors per direction of transmission. Serial transmission is used on buses B(O) to B(p - 1). Each bus contains two lines, one per direction of transmission. Thus, bus B(O) contains line A(O) for the multicontroller group equipment direction, and line R(O) for the group equipment multicontroller direction. The v multicontrollers are associated respectively with v interface circuits IMC(0) to IMC(v - 1). These interface circuits route the signalling words to the proper buses and perform parallel-to-serial conversion in the direction of the group equipments, and perform serial-to-parallel conversion and the grouping of signalling words in the direction of the multicontrollers. The p group equipments GE(0) to GE(p - 1) are associated respectively with p interface circuits IGE(0) to IGE(p - 1). which as will be explained later, perform serial-to-parallel conversion and a transmission time conversion in the direction of the group equipments, and vice-versa in the direction of the multicontrollers.

The multicontrollers are paired, so the interface circuits IGE(0) to IGE(p - 1) are each connected to two serial buses (of which only one is shown in figure 2).

Figure 3 shows an interface circuit between a multicontroller and its m serial transmission buses, e.g. circuit IMC(0) providing the interface between multi-controller MC(0) and the m buses B(0) to B(m - 1). The multicontroller MC(0) delivers, in parallel form, n successive codes of b bits per frame T, i.e. one code per period t' = T/n. Each of these codes is assigned to a given scanner-driver and thus should be transmitted over the signalling time channel (channel 16, for example) of the multiplex junction serving that scanner-driver.The table below gives the relation between the order of appearance of the n codes at the output of the multicontroller and the group equipment, as well as the multiplex junction concerned: Order Group Multiplex of codes equipment junction 0 GE (0) J(0) 1 GE (1) J ( ) ml GE(m- 1) J(0) m GE (O) J(1) m+l GE (1) J(1) 2m-l GE(m-l) J(1) 2m GE (0) J(2) 2m + 1 GE(1) J(2) n-I GE (m -1) J(q- 1) The codes supplied by the multicontroller MC(0) are transmitted in parallel form simultaneously to m buffer registers ORB(0) to ORB(m - 1) controlled by clock pulses H(0) to H(M - 1) of period m.t', separated from each other by a time interval t' as shown in figure 4a.

The b parallel outputs from the buffer registers are connected respectively to the b parallel inputs of m shift registers OSR(0) to OSR(m - 1). The codes are entered simultaneously in these m registers under the control of clock pulses I, having a period of m.t.', as shown in figure 4b. The shift registers perform the parallel-to-serial conversion of the codes under the control of clock pulses K of period m.t'/b. Serial transmission is then carried out on lines A(0) to A(m - 1) of buses B(0) to B(m - 1), each line having a line transmitter and a twisted pair.

The codes are transmitted synchronously over lines (0) to A(m - 1).

In the opposite direction, the signalling codes arrive simultaneously in serial form over lines R(0) to R(m - 1) of buses B(0) to B(m - 1), each line having a twisted pair and a line receiver. A set of m shift registers ISR(0) to ISR(m - 1), controller by clock pulses K of period m.t'/b, carry out the serial-to-parallel conversion of the received codes. These codes are entered in m buffer registers IRB(0) to IRB(m - 1) under the control of clock pulses I having a period of m.t.' (figure 4b). A multiplexer S(0), addressed periodically by codes AD at a rate t', as shown in figure 4c, successively transmits in parallel form the various received codes to the multi-controller MC(0). These AD codes can come from a counter, identical for the v interface circuits IMC(0) to IMC(v - 1), incremented under the control of clock pulses of period t'.

Figure 5 represents an interface circuit between a group equipment and its two serial transmission buses, e.g. the circuit IGE(0) providing the interface between group equipment GE(0) and the two buses B(0) associated with the two line signalling units SILA and SILB respectively. Since these two units operate alternately by time division, for example 4 ms each, the transmission of the codes over the two lines A(0) will not be simultaneous, but shifted by 4 ms. These lines are terminated by line receivers whose outputs are connected by an OR gate. A shift register ISG(0) carries out the serial-to-parallel conversion of the b-bit codes under the control of clock pulses M of period m.t/b synchronized with the clock pulses K. The b parallel outputs of the shift register ISG(0) are connected to the b parallel inputs of a read-write memory IME(0) containing q lines of b bits.This memory is designed to produce a time conversion, so as to deliver the line signalling codes to the multiplex superjunction SJ(0) of the associated group equipment GE(0) at the appropriate time slots t. We shall assume, as an example, that the q time slots t transmitting the signalling codes are consecutive within a frame T, as shown in figure 6a. These codes are respectivelv routed to the signalling time channel (for example, channel 16) of junctions J(0) to J(q - 1) by the logic unit UL(0) of the group equipment GE(0).

Memory IME(0) is addressed cyclically at two different frequencies for reading and writing, by a multiplexer SE identical for the p interface circuits IGE(0) to IGE(p - 1). This multiplexer receives on the one hand codes CY (write) of period m.t', as shown in figure 6b and, on the other hand, codes DY (read) of period t, as shown in figure 6c. The q codes DY are identical with the q codes CY, but they change more frequently. Each time slot t is divided into two equal parts A and B, as shown in figure 6d. By means of a clock pulse P of period t, the multiplexer SE delivers a code CY durin the first part A of each time slot t and a code DY during the second part B.Memory IRE(0 is written cyclically, every period m.t' on the address CY, under the control of write pulses E of period m.t' present during part A of a time slot t, as shown in figure 6e. It is read the rest of the time, as shown in figure 6f. The codes read are sent to a buffer register IRT(0) controlled by clock pulses Q of period t present during part B of the time slots. This buffer register is connected to the multiplex super-junction SJ(0) of group equipment GE(0) through a multiplexer V(0). This multiplexer, controlled by pulses W shown in figure 6g, allows the codes read from memory IME(0) to pass only during the q successive time slots reserved within a frame for transmission of the line signalling.

During the other time slots, multiplexer V(0) blocks the signalling codes and allows the conversation codes coming from the space-time switch to pass.

The operations are opposite in the group equipment multicontroller direction. The codes coming from group equipment GE(0) are directed in parallel form to the b inputs of a buffer register ORT(0) controlled by pulses Q of period t. This buffer register is connected to the inputs of a memory OME(0) having q lines of b bits designed to carry out a time conversion.

This memory is addressed in the same way as memory IME(0). It is written at the address DY, under the control of pulses X of period t present during the second half B of the q time slots t reserved for line signalling, as shown in figure 6h. It is read the rest of the time. A shift register OSG(0) enters in parallel form the read codes under the control of clock pulses E of period m.t' (figure 6e). These codes are converted into serial form by shift pulses M of period m.t'/b.

The output of shift register OSG(0) is connected, through line transmitters, to the two lines R(0) of the two buses B(0) associated with the two signalling units SILA and SILB respectively.

Although this invention has been described with a particular embodiment, it is clearly not limited thereto and is capable of variants or modifications still lying within its scope. In particular, it can be used, for multiplex junctions having more than one time channel reserved for signalling. It can also be used to send or receive line data transmitted channel by channel in accordance with the CEPT format, with addressing by position of frames within a group of frames (multi-frame), or to exchange control information with a distant exchange.

WHAT WE CLAIM IS: 1. An automatic telecommunication exchange in which connections are set up in TDM manner using PCM, in which the exchange includes group equipments each of which serves q multiplex junctions, in which each of the multiplex junctions conveys r time channels outside the exchange while on the inside of the exchange each group equipment has a multiplex super-junction conveying qr time channels of duration t one the space-time switch side, in which a line signalling unit is provided for responding to signals from the channels on the junctions and for sending signals to those channels, in which p serial transmission buses are provided to connect the line signalling unit respectively to each said group equipment, which serial transmission buses to not pass through the space-time switch, and in which each bus transmits over two separate lines, one per direction, the line signal bits of the q multiplex junctions of its one of the group equipments.

2. An exchange according to claim 1, in which the line signalling unit contains v multicontrollers each handling the line signalling data of q.m multiplex junctions (v2p/m), in which each multicontroller is connected to m serial transmission buses by an interface circuit routing the signalling codes in parallel form, in the multicontroller group equipment direction, to the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

**WARNING** start of CLMS field may overlap end of DESC **. GE(0) and the two buses B(0) associated with the two line signalling units SILA and SILB respectively. Since these two units operate alternately by time division, for example 4 ms each, the transmission of the codes over the two lines A(0) will not be simultaneous, but shifted by 4 ms. These lines are terminated by line receivers whose outputs are connected by an OR gate. A shift register ISG(0) carries out the serial-to-parallel conversion of the b-bit codes under the control of clock pulses M of period m.t/b synchronized with the clock pulses K. The b parallel outputs of the shift register ISG(0) are connected to the b parallel inputs of a read-write memory IME(0) containing q lines of b bits.This memory is designed to produce a time conversion, so as to deliver the line signalling codes to the multiplex superjunction SJ(0) of the associated group equipment GE(0) at the appropriate time slots t. We shall assume, as an example, that the q time slots t transmitting the signalling codes are consecutive within a frame T, as shown in figure 6a. These codes are respectivelv routed to the signalling time channel (for example, channel 16) of junctions J(0) to J(q - 1) by the logic unit UL(0) of the group equipment GE(0). Memory IME(0) is addressed cyclically at two different frequencies for reading and writing, by a multiplexer SE identical for the p interface circuits IGE(0) to IGE(p - 1). This multiplexer receives on the one hand codes CY (write) of period m.t', as shown in figure 6b and, on the other hand, codes DY (read) of period t, as shown in figure 6c. The q codes DY are identical with the q codes CY, but they change more frequently. Each time slot t is divided into two equal parts A and B, as shown in figure 6d. By means of a clock pulse P of period t, the multiplexer SE delivers a code CY durin the first part A of each time slot t and a code DY during the second part B.Memory IRE(0 is written cyclically, every period m.t' on the address CY, under the control of write pulses E of period m.t' present during part A of a time slot t, as shown in figure 6e. It is read the rest of the time, as shown in figure 6f. The codes read are sent to a buffer register IRT(0) controlled by clock pulses Q of period t present during part B of the time slots. This buffer register is connected to the multiplex super-junction SJ(0) of group equipment GE(0) through a multiplexer V(0). This multiplexer, controlled by pulses W shown in figure 6g, allows the codes read from memory IME(0) to pass only during the q successive time slots reserved within a frame for transmission of the line signalling. During the other time slots, multiplexer V(0) blocks the signalling codes and allows the conversation codes coming from the space-time switch to pass. The operations are opposite in the group equipment multicontroller direction. The codes coming from group equipment GE(0) are directed in parallel form to the b inputs of a buffer register ORT(0) controlled by pulses Q of period t. This buffer register is connected to the inputs of a memory OME(0) having q lines of b bits designed to carry out a time conversion. This memory is addressed in the same way as memory IME(0). It is written at the address DY, under the control of pulses X of period t present during the second half B of the q time slots t reserved for line signalling, as shown in figure 6h. It is read the rest of the time. A shift register OSG(0) enters in parallel form the read codes under the control of clock pulses E of period m.t' (figure 6e). These codes are converted into serial form by shift pulses M of period m.t'/b. The output of shift register OSG(0) is connected, through line transmitters, to the two lines R(0) of the two buses B(0) associated with the two signalling units SILA and SILB respectively. Although this invention has been described with a particular embodiment, it is clearly not limited thereto and is capable of variants or modifications still lying within its scope. In particular, it can be used, for multiplex junctions having more than one time channel reserved for signalling. It can also be used to send or receive line data transmitted channel by channel in accordance with the CEPT format, with addressing by position of frames within a group of frames (multi-frame), or to exchange control information with a distant exchange. WHAT WE CLAIM IS:

1. An automatic telecommunication exchange in which connections are set up in TDM manner using PCM, in which the exchange includes group equipments each of which serves q multiplex junctions, in which each of the multiplex junctions conveys r time channels outside the exchange while on the inside of the exchange each group equipment has a multiplex super-junction conveying qr time channels of duration t one the space-time switch side, in which a line signalling unit is provided for responding to signals from the channels on the junctions and for sending signals to those channels, in which p serial transmission buses are provided to connect the line signalling unit respectively to each said group equipment, which serial transmission buses to not pass through the space-time switch, and in which each bus transmits over two separate lines, one per direction, the line signal bits of the q multiplex junctions of its one of the group equipments.

2. An exchange according to claim 1, in which the line signalling unit contains v multicontrollers each handling the line signalling data of q.m multiplex junctions (v2p/m), in which each multicontroller is connected to m serial transmission buses by an interface circuit routing the signalling codes in parallel form, in the multicontroller group equipment direction, to the

appropriate bus, and in the group equipment multicontroller direction performing the serial-to-parallel conversion of the codes as well as the grouping of the codes coming from the m transmission buses.

3. An exchange according to claim 1 or 2, in which each group equipment is connected to its serial transmission bus by an interface circuit providing, in the multicontroller group equipment direction, serial-to-parallel conversion of the signalling codes as well as a time conversion permitting the said codes to be injected at the proper instant in the group equipment, so that they are transmitted on the line signalling time channel of the appropriate junctions, and in the group equipment multicontroller direction, the reverse time conversion as well as the parallel-to-serial conversion of the extracted codes.

4. An exchange according to claim 3 and in which the time conversion, in the multicontroller group equipment direction, is performed in a read-write memory having q lines of b bits each, addressed cyclically in a period m.T/n for write and a period t for read, with means being provided to inject the read words at the required time in the group equipment.

5. An exchange according to claim 4, and in which the time conversion, in the group equipment multicontroller direction, is performed in a read-write memory identical with the preceding memory, addressed cyclically in the period t for write and in the period m.T/n for read, the write operation however being possible only during a definite time corresponding to the transmission time channels of the line signalling codes.

6. An automatic telecommunication exchange substantially as described with reference to the accompanying drawings.