GB1561643A

GB1561643A - Phaseshift-keying modulators

Info

Publication number: GB1561643A
Application number: GB3261275A
Authority: GB
Original assignee: Marconi Co Ltd
Current assignee: BAE Systems Electronics Ltd
Priority date: 1975-08-05
Filing date: 1975-08-05
Publication date: 1980-02-27
Also published as: IT1070638B; DE2548241B2; FR2320666A1; FR2320666B1; DE2548241A1

Description

(54) IMPROVEMENTS IN OR RELATING TO PHASE-SHIFT-KEYING MODULATORS (71) We, THE MARCONI COMPANY LIMITED, a British Company, of Marconi House, New Street, Chelmsford, Essex, CM 1 1 PL do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to phase-shift-keying (P.S.K.) modulators, and seeks to provide improved modulators of this kind having particularly stable phase-shift levels.

According to this invention in its broadest aspect, a phase-shift-keying modulator is provided with means for receiving one or more pairs of input binary data signals which are used to polarity-modulate respective streams of clock pulses derived from a common clock source, and in which phase modulated high frequency signals which are derived by phase modulation of locally produced high frequency signals by the polarity modulated pulses, obtained from a given pair of input data signals are combined to produce a high frequency signal having an instantaneous phase angle selected from four predetermined equally spaced phase angles.

According to a further aspect of this invention a phase-shift keying modulator includes a pair of inverters for inverting, in dependence on input binary data signals, selected ones of a stream of clock pulses passed to each inverter from a common clock source, said clock pulses having a duty ratio of substantially less than one to one; a pair of phase modulators each of which respectively receives one of said streams of clock pulses passed by a respective inverter and which phase modulate high frequency signals received from a local oscillator, said high frequency signals which are received at the two phase modulators having a relative phase difference of w/2; and means for combining said phase modulated signals to produce a high frequency signal having an instantaneous phase angle selected from four predetermined equally spaced phase angles.

Although in the simplest embodiments of this invention only one pair of input binary data signals are provided which result in an output signal having an instantaneous phase angle selected from four equally spaced phase angles, where, say, two pairs of input binary data signal are provided each pair results in an output signal having one of a set of four equally spaced phase angles, but with one set offset from the other by sir/4, so that both sets together represent eight equally spaced phase angles.

In theory more than two pairs of input binary sata signal can be provided, so that the output signal takes one of a correspondingly larger number of possible phase angles but since the spacing between the phase angles is becoming small, the error rate of a transmission system incorporating such a modulator may rise to unacceptable levels Accordingly it is expected that in practice one or two pairs of input binery data signals will be provided.

By adopting a duty ratio for the clock pulses which is substantially less than one to one, the associated spectrum departs only slightly from a uniform response in the frequency band of interest. This enables relatively simple filters to be used subsequently to achieve the desired spectrum control.

Preferably the duty ratio of each clock pulse is 25%.

The invention is further described, by way of example, with reference to the drawings accompanying the Provisional specification in which, Figure 1 is a schematic circuit diagram of a four level phase-shift-keying modulator in accordance with the present invention, Figure 2 illustrates waveforms present at various points in the circuit diagram, Figure 3 is an explanatory phase diagram, Figure 4 shows a modification and extension of the present invention to an eight level phase-shift-keying modulator, and Figure 5 is an explanatory diagram relating thereto, and with reference to the accompanying drawings in which Figures 6 and 7 show modifications to the invention illustrated in Figures 1 and 4.

Figure 1 shows a phase-shift-keying modulator having a single pair of input binary data terminals 1, 2 and which produces a fourlevel phase angle output at terminals 3. A clock signal is applied via terminal 4 and AND gate 5 to a pulse generator 6 which produces clock pulses having a pulse repetition frequency equal to the pulse repetition frequency of the input binary data. Whilst, however, the input binary data is of the nonreturn to zero (NRZ) type, the clock pulses produced by the pulse generator 6 are arranged to have duty ratio of only 25%.

Typical input binary data streams present at terminals 1 and 2 are shown in Figure 2 at lines a and b respectively, and the clock signals applied to terminal 4 and the clock pulses produced by pulse generator 6 are shown at lines c and d respectively.

The stream of clock pulses are routed to two polarity inverting circuits 7 and 8 where individual clock pulses are polarity modulated by inversion in dependence on the logic level of the input binary data which is applied to a respective one of inverter circuits 7 and 8. The output signals provided by the polarity inverting circuits 7 and 8 are shown in lines e andfrespectively of Figure 2. Thus when the input binary data is a logic 1 the clock pulse is passed with unaltered polarity, but for a logic 0 the clock pulse is inverted.

Each of the polarity inverting circuits 7 and 8 is of the balanced modulator type reversing switch, and its configuration is illustrated in diagrammatic form in Figure 1. The two streams of clock pulses, containing inverted and erect pulses, are fed via respective low pass filters 9 and 10 to balanced modulators 11 and 12, where they are mixed with a relatively high frequency signal obtained from a local oscillator 13. The high frequency signal is passed from the oscillator 13 via a gate 14 and is then fed directly to balanced modulator 12, and is also fed via a phase shifter 15, which introduces a w/2 phase change to balanced modulator 11.

Referring to Figure 3, the phase of the signal applied by oscillator 13 to balanced modulator 12 is taken to be the reference phase and is represented by vector 31. The phase of the signal applied to balanced modulator 11 is shown by vector 32, which represents a phase shift of 42 introduced by the phase shifter 15. The balanced modulators produce suppressed carrier bandpass signals centred at the frequency of the oscillator 13.

Erect clock pulses result in signals which are in phase with the high frequency signals applied to the balanced modulators, i.e.

corresponding to vectors 31 and 32, whereas inverted clock pulses result in a 7 phase change. Thus an inverted clock pulse applied to balanced modulator 12 results in a signal having the phase of vector 33, and an inverted clock pulse applied to balanced modulator 11 results in a signal having the phase of vector 34.

The outputs of the two balanced modulators 11 and 12 are combined by combiner 16, which could be merely a resistive adding network, the result of the combination being one of the solid-line vectors 35, 36, 37 or 38, depending on whether vector 31 or 33 is combined with vector 32 or 34.

As so far described, it has been assumed that the phase-shift-keying modulator circuit shown in Figure 1 operates continuously.

However, in practice a carrier-burst on/off control may be needed. This would be required, for example, in a phase-shift-keying modulator utilised in a satelite time-division multiple-access digital communication system.

To this end, a carrier-burst control signal is applied to terminal 17 and which via buffer 18 controls the gate 5 and the gate 14. The provision of gate 14 greatly improves signal suppression in the inter-burst period. In the absence of gate 14, signal suppression would be dictated by the degree of balance obtainable in balanced modulators 11 and 12. By using gate 14 this figure can be improved substantially.

By ensuring at the start of a burst (when the carrier transition is from OFF to ON), that gate 14 is enabled before gate 5 is enabled and by ensuring at the end of a burst, that gate 5 is inhibited before gate 14 is inhibited, the transient in the modulated output signal may be constrained so as not to cause interference frequency components lying outside the bandwidth defined by the low-pass filters 9 and 10. The required switching delays are provided by buffer 18.

The phase-shift-keying modulator shown in Figure 1 possesses the advantage that since a common pulse generator 6 is used to drive both balanced modulators 11 and 12, problems due to differential drift of the input binary data are obviated. Furthermore, drift of the clock pulses produced by the pulse generator 6 will not cause phase errors, but will merely cause a change in the general level of the combined output signal and this point is considered to be of considerable importance in practice.

The use of clock pulses having a duty ratio of substantially less than one to one (a 25% duty ratio is mentioned in connection with Figure 1) means that particularly simple low pass filters can be used, as compared with some known phase-shift-keying modulators which produce undesirable spectral components of the (sinx) /x form. The circuit shown in Figure 1 avoids the need to provide d.c. coupled amplifiers in the signal path, and this feature greatly enhances the potential stability (with time and temperature etc.) of the modulator. However, an a.c. coupled amplifier is preferably provided between filters 9 and 10 and modulators 11 and 12 respectively to provide impedance matching and to boost signal levels.

Since the input binary data is merely required to control the operation of the invertor circuits 7 and 8, the circuit operation is largely immune to changes in input signal amplitudes. The use of the inverter circuits 7 and 8 serves also to remove the effect of any timingjitter present on the input binary data.

This is because the inverter circuits are biased into the required state by the input binary data before the clock pulse is presented to them.

The invention is not limited to a four phase level modulator, but is applicable to higher levels. Figure 4 illustrates the case in which the invention is applied to an eight phase level modulator. Referring to Figure 4, it will be seen that two pairs of input terminals 31, 32 and 41, 42 are provided. Each pair of input terminals is connected to a circuit which corresponds largely to the circuit shown in Figure 1, and where appropriate like reference numerals are used but with those of the circuitry relating to the first pair of terminals being prefixed by 3 and those of the circuitry relating to the second pair of terminals being prefixed by 4. The clock pulses provided by pulse generator 6 are applied at terminal 51, ans the burst-control ciruitry is omitted for the sake of clarity.The clock pulses are routed via resistors 52 and 53 as shown, and they can be earthed at the inputs to the inverter swirches by electronic on/off switches 54 or 55.

The high frequency signal produced by oscillator 313 is routed to an additional 44 piase shifter 56 and thence to modulator 411 and phase shifter 42.

By analogy with the operation of Figure 1, it will be uderstood that combiners 316 and 416 are each capable of providing a double side-band suppressed carrier signal having at any one time one of four phases. By virtue of the additional phase shifter 56, the combiner 416 produces a set of our phases which is offset by 44 from the set produced by combiner 316. These phases are shown in Figures 5, in which the four vectors 35 to 38 are obtained from combiner 316, and so correspond to the like referenced vectors in Figure 3, and in which vectors 61 to 64 are obtained from combiner 416. The outputs of combiners 316 and 416 are fed to a combiner 57 and thence to output terminal 58, so that any one of the phase vectors shown in Figure 5 can be used as the output phase of the eight-level phaseshift-keying modulator.

Which particular phase-vector is adopted at any particular instant will depend on the instantaneous value of the binery data to be transmitted. Since eight levels are available, a three digit binary code can be accommodated, and by way of example each vector in Figure 5 is associated with a particular code value, the values increasing anti-clockwise in accordance with the following table Vector Code 61 000 35 001 62 010 36 011 63 100 37 101 64 110 38 111 In practice the three-digit codes will be applied to some form of processor which will close one or other of on/off switches 54 or 55 and apply the appropriate logic signal to one of the pairs of input data terminals 41 and 42 or 31 and 32 respectively. Thus for example when switch 54 is closed, combiner 316 provides no output signal and the output vector is provided by combiner 416.

In practice, it will be understood that differential codes will be transmitted to avoid the need to transmit a phase reference signal, and in the present description it is assumed that the phase-shift-keying modulator receives the data in the appropriate differential code converted form.

An alternative mode of connecting the inverter circuits is shown in Figure 6. This is applicable to the inverters 7 and 8 in Figure 1 and also to the inverters 37, 38, 47 and 48 in Figure 4 although the reference numerals adopted correspond to those used in Figure 1.

The modified connection provides improved stability of the base level when long sequences of adjacent 'l's or '0's are received.

The frequency response can be further improved by including frequency compensating circuits in each inverter circuit, and suitable forms are shown in Figure 7. A high frequency compensating network 61 consists of a capacitor 62 in shunt with a resistor 63, as shown, and a low frequency compensating network 64 consists of a resistor 65 and a capacitor 66 connected in series across the output coil of the inverter circuit. The output 67 of the inverter is connected to a respective low pass filter 9 or 10 (in Figure 1) and 39, 310, 49 or 410 (in Figure 4) as previously.

WHAT WE CLAIM IS: 1. A phase-shift-keying modulator includes means for receiving one or more pairs of input binary data signals which are used to polarity-modulate respective streams of clock pulses derived from a common clock source, and in which phase modulated high frequency signals which are derived by phase modulations of locally produced high frequency signals by the polarity modulated pulses obtained from a given pair of input data

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

amplifier is preferably provided between filters 9 and 10 and modulators 11 and 12 respectively to provide impedance matching and to boost signal levels.

Since the input binary data is merely required to control the operation of the invertor circuits 7 and 8, the circuit operation is largely immune to changes in input signal amplitudes. The use of the inverter circuits 7 and 8 serves also to remove the effect of any timingjitter present on the input binary data.

This is because the inverter circuits are biased into the required state by the input binary data before the clock pulse is presented to them.

The invention is not limited to a four phase level modulator, but is applicable to higher levels. Figure 4 illustrates the case in which the invention is applied to an eight phase level modulator. Referring to Figure 4, it will be seen that two pairs of input terminals 31, 32 and 41, 42 are provided. Each pair of input terminals is connected to a circuit which corresponds largely to the circuit shown in Figure 1, and where appropriate like reference numerals are used but with those of the circuitry relating to the first pair of terminals being prefixed by 3 and those of the circuitry relating to the second pair of terminals being prefixed by 4. The clock pulses provided by pulse generator 6 are applied at terminal 51, ans the burst-control ciruitry is omitted for the sake of clarity.The clock pulses are routed via resistors 52 and 53 as shown, and they can be earthed at the inputs to the inverter swirches by electronic on/off switches 54 or 55.

The high frequency signal produced by oscillator 313 is routed to an additional 44 piase shifter 56 and thence to modulator 411 and phase shifter 42.

By analogy with the operation of Figure 1, it will be uderstood that combiners 316 and 416 are each capable of providing a double side-band suppressed carrier signal having at any one time one of four phases. By virtue of the additional phase shifter 56, the combiner 416 produces a set of our phases which is offset by 44 from the set produced by combiner 316. These phases are shown in Figures 5, in which the four vectors 35 to 38 are obtained from combiner 316, and so correspond to the like referenced vectors in Figure 3, and in which vectors 61 to 64 are obtained from combiner 416. The outputs of combiners 316 and 416 are fed to a combiner 57 and thence to output terminal 58, so that any one of the phase vectors shown in Figure 5 can be used as the output phase of the eight-level phaseshift-keying modulator.

Which particular phase-vector is adopted at any particular instant will depend on the instantaneous value of the binery data to be transmitted. Since eight levels are available, a three digit binary code can be accommodated, and by way of example each vector in Figure 5 is associated with a particular code value, the values increasing anti-clockwise in accordance with the following table Vector Code

61 000

35 001

62 010

36 011

63 100

37 101

64 110

38 111 In practice the three-digit codes will be applied to some form of processor which will close one or other of on/off switches 54 or 55 and apply the appropriate logic signal to one of the pairs of input data terminals 41 and 42 or 31 and 32 respectively. Thus for example when switch 54 is closed, combiner 316 provides no output signal and the output vector is provided by combiner 416.

In practice, it will be understood that differential codes will be transmitted to avoid the need to transmit a phase reference signal, and in the present description it is assumed that the phase-shift-keying modulator receives the data in the appropriate differential code converted form.

An alternative mode of connecting the inverter circuits is shown in Figure 6. This is applicable to the inverters 7 and 8 in Figure 1 and also to the inverters 37, 38, 47 and 48 in Figure 4 although the reference numerals adopted correspond to those used in Figure 1.

The modified connection provides improved stability of the base level when long sequences of adjacent 'l's or '0's are received.

The frequency response can be further improved by including frequency compensating circuits in each inverter circuit, and suitable forms are shown in Figure 7. A high frequency compensating network 61 consists of a capacitor 62 in shunt with a resistor 63, as shown, and a low frequency compensating network 64 consists of a resistor 65 and a capacitor 66 connected in series across the output coil of the inverter circuit. The output 67 of the inverter is connected to a respective low pass filter 9 or 10 (in Figure 1) and 39, 310, 49 or 410 (in Figure 4) as previously.

WHAT WE CLAIM IS: 1. A phase-shift-keying modulator includes means for receiving one or more pairs of input binary data signals which are used to polarity-modulate respective streams of clock pulses derived from a common clock source, and in which phase modulated high frequency signals which are derived by phase modulations of locally produced high frequency signals by the polarity modulated pulses obtained from a given pair of input data

signals are combined to produce a high frequency signal having an instantaneous phase angle selected from four predetermined equally spaced phase angles.
2. A phase-shift-keying modulator includes a pair of inverters for inverting, in dependence on input binary data signals, selected ones of a stream of clock pulses passed to each inverter from a common clock source, said clock pulses having a duty ratio of substantially less than one to one; a pair of phase modulators each of which respectively receives one of said streams of clock pulses passed by a respective inverter and which phase modulate high frequency signals received from a local oscillator, said high frequency signals which are received at the two phase modulators having a relative phase difference of 42; and means for combining said phase modulated signals to produce a high frequency signal having an instantaneous phase angle selected from four predetermined equally spaced phase angles.
3. A phase-shift-keying modulator as claimed in claim 2 and wherein the duty ratio of each clock pulse is 25%.
4. A phase-shift-keying modulator as claimed in claim 2 or 3 and wherein a lowpass filter is provided beteeen each inverter and the corresponding phase modulator.
5. A phase-shift-keying modulator as claimed in claim 4 wherein an a.c. coupled amplifier is provided between each low-pass filter and the corresponding phase modulator.
6. A phase-shift-keying modulator substantially as illustrated in and described with reference to Figures 1 or 4 of the drawings accompanying the Provisional specification.
7. A phase-shift-keying modulator substantially as illustrated in and described with reference to Figures 1 or 4 as modified by Figure 6 or 7 of the accompanying drawings.