DE2548241A1 - PHASE SHIFT KEY MODULATOR - Google Patents

Description

MANITZ, FINSTERWALD & GRÄMKO ¥

PATENT LAWYERS

Munich, 2-3. OCT. ίΞ / a P / Sv - M 3083

The Marconi Company Limited

Marconi House, New Street Chelmsford, Essex CM1 1PL / United Kingdom

Phase shift key modulator

The invention relates to phase shift key (P.S.K.) Modulators (phase-shift-keying modulators).

One of the objects of the invention is to establish to create such modulators with particularly stable phase shift levels or values.

In accordance with the broadest aspect of the present invention there is provided a phase shift key modulator having an arrangement for receiving one or more pairs of

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009886/070 1

DIFl.-IMO. TV. GRAMKOW ZENTRALKASSE BAYER. FOLK BANKS

7 STUTTGART SO (BAD CANNSTATT) MONKS. ACCOUNT NUMBER 7270

SEELBERGSTR. 23/25. TEL. (0711) 56 72 61 POSTSCHECK: MÖNCHEN 77O62-SO5

input, binary data representing signals suggested, which are used to the respective Polgen of T air timpul s s from a common clock pulse source are issued to modulate polarity; the phase-modulated HoGhfuaq.uensignale that are sent by the polarity-modulated pulses of a certain pair of input data signals are derived, combined so that a high frequency signal with an instantaneous The phase angle arises from four previously determined, equally spaced phase angles is selected.

According to another aspect of the present invention, a phase shift key modulator includes a pair of inverters, to select pulses from a sequence of clock pulses as a function of the binary data signals entered, which are fed to each inverter from a common clock pulse source, to invert the Clock pulses have a duty cycle much less than one to one; also is a pair of phase modulators provided, one of which is one of the sequences of clock pulses which are passed through the respective inverter, and which that of a local oscillator received high-frequency signals phase-modulated, the recorded at the two phase modulators High frequency signals have a relative phase difference of Have / 7/2; Finally, the modulator also has an arrangement for combining the phase-modulated signals, so that a high frequency signal arises with an instantaneous phase angle which is made up of four previously determined im phase angles arranged at the same angle is selected.

In the simplest embodiments of the present invention is just a pair of binary data representing

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Input signals provided so that an output signal is produced with an instantaneous phase angle selected from four equally spaced phase angles; however, if two pairs of input signals representing binary data are provided, each pair results in an output signal which has a phase angle of a set of four equally spaced phase angles, but with one set offset by 77 / k from the other set, see above that the two sets together represent eight equally spaced phase angles.

Theoretically, more than two pairs of input signals with binary data can be provided, so that the The output signal has a phase angle which corresponds to one of a correspondingly larger number of possible phase angles; however, in this case, since the distance between the phase angles becomes smaller and smaller, the error rate may be one Transmission system that uses such a modulator can rise to a value that cannot be accepted can «Therefore, in practice, only one or two pairs of input signals with binary data should be used ·

If the pulse duty factor for the clock pulses is significantly less than one to one, it produces selective inversion depending on the input signals with binary Data unwanted frequency components that can be suppressed by relatively simple filters.

According to a preferred embodiment, the duty cycle is of each clock pulse 25%.

The invention will be described in the following on the basis of exemplary embodiments with reference to the accompanying schematic Drawings explained in more detail:

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Show it:

1 is a schematic diagram of a phase shift key modulator with four levels according to the present invention;

Figure 2 shows waveforms appearing at various points on the circuit diagram;

3 shows an explanatory phase diagram;

Fig. Bf shows a modification and enlargement of the modulator according to the present invention to a phase shift key modulator with eight values; and

5 shows a diagram used to explain FIG.

Fig. 1 shows a phase shift key modulator with a single pair of terminals 1,2 for inputted binary data; this modulator generates at the terminal or the output terminal 3 an output signal with a phase angle, that can assume four different values _o A clock signal is applied via a terminal Zf and an AND gate 5 to a pulse generator 6, the clock pulses with a pulse frequency and Generates a pulse repetition rate that is equal to the pulse rate of the binary data entered. However, although the binary data entered are represented in the NBZ method (non-return to zero method), that is, in alternating letters, the clock pulses generated by the pulse generator 6 are arranged in such a way that they have a duty cycle of only 25 % . Typical sequences of input binary data occurring at connections 1 and 2 are shown in FIG. 2 in lines a) and / or »b), while

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the clock pulses supplied to the terminal Zf and those from the Pulse generator 6 generated clock pulses are shown in lines c) and d).

The sequence of clock pulses is fed to two polarity reversing or inverting circuits 7 and 8, where the individual clock pulses dmeh inversion as a function are polarity-modulated by the logic level of the input binary data, each on one of the inverter circuits 7 and 8 are given. The output signals generated by the circuits 7 and 8 for reversing the polarity are shown in lines e) and f) of FIG. If a logical resp. binary 1 is supplied, the clock pulse is passed with unchanged polarity, while the clock pulse for a logical or binary O is inverted or reversed.

Each of the polarity reversal circuits 7 and 8 is a push-pull modulator reversing switch, the structure of which is shown schematically in FIG. The two episodes of clock pulses, which contain inverted and upright or unchanged pulses, are each passed through a low-pass filter 9 and 10 led to balanced or »push-pull modulators Π and 12, where they are supplied with a relatively high high-frequency signal obtained from a local oscillator 13. The high frequency signal will passed by the oscillator 13 via a logic element lif and then fed directly to the push-pull modulator 12; in addition, it is also via a phase shifter 15, which introduces a phase change of 77/2, given to the push-pull modulator 11.

In the following, the mode of operation of the modulator will be explained with reference to FIG. 3; the phase of the

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The signal applied to the oscillator 13 to the push-pull modulator 12 is used as a reference phase and is represented by the vector 31. The phase of the signal fed to push-pull modulator 11 is shown by vector 32 which represents a phase shift of / ^ 2 introduced by phase shifter 15. The push-pull modulators generate suppressed carrier bandpass signals which are centered at the frequency of the oscillator 13. Upright or unchanged clock pulses result in signals that are in phase with the high-frequency signals that are fed to the push-pull modulators, that is, correspond to vectors 31 and 32, while inverted clock pulses result in a phase change of 77. An inverted clock pulse applied to the push-pull modulator 12 thus leads to a signal with the phase of the vector 33 »while an inverted clock pulse applied to the push-pull modulator 11 results in a signal with the phase of the vector 3k.

The output signals of the two push-pull modulators 11 and 12 are combined by a combiner 16 which is simply a resistor-adder network could; the result of the combination is one of the vectors 35 »36, 37 or 38, which is shown in Fig. 3 with solid lines are shown; it depends on whether the vector is 31 or 33 is combined with the vector 32 or 34.

In the description so far, it has been assumed that the phase shift frequency modulator shown in FIG works continuously. In practice, however, an ON / OFF control for the carrier information chain (carrier burst) or the intermittent carrier information may be required. This is for example the case with a phase shift key modulator,

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used in a digital satellite communication system employing multiple access and time division multiplexing. For this purpose, a control signal for the closed carrier information is applied to a connection 17 which controls the logic element 5 and the logic element 1Ij- via a buffer 18. By using the logic element 1 k , the signal suppression in the time intervals between the closed information chains is greatly improved. Without the logic element 11+ , the signal suppression would be determined by the size of the compensation or balance that can be achieved in the balanced or push-pull modulators 11 and 12. Using the logic element lif this value can be significantly improved.

At the beginning of a closed information chain (if the Carrier transition from OFF to ON) ensures that the logic element 1 if is activated before the logic element 5 is controlled; at the end of the closed information chain it is ensured that the Link 5 is blocked before the link 1 if is blockedj then the equalization or settling process can take place in the modulated output signal are limited in such a way that no interference or interference frequency components which lie outside the bandwidth defined by the low-pass filters 9 and 10. The required switching delays are supplied by the buffer 18.

The phase shift key modulator shown in KLg, 1 has the following advantage: Since a common pulse generator 6 is used to control the two push-pull modulators 11 and 12, the problems due to the difference or differential shift of the binary input

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data avoided. In addition, a shift or a drifting of the clock pulses generated by the pulse generator 6 does not cause any phase errors, but only causes one Change in the general level of the combined output signal; however, this point is when used in particularly important in practice.

The use of clock pulses with a duty cycle much less than one to one (a duty cycle of 25% was mentioned in connection with FIG. 1) means that particularly simple low pass filters can be used, which is what some conventional phase shift key modulators do nxht is the case, so that they produce undesirable spectral components of the form (sinaf) / 36. In the circuit shown in FIG. 1, no DC-coupled amplifiers have to be provided in the signal path; this increases the potential stability (with time, temperature, etc.) of the modulator significantly »

Since the binary data entered only have to control the operation of the inverter settings 7 and 8, the circuit, i.e. the operation of the individual components, is relatively insensitive to changes in the amplitudes of the input signal Remove the effect of any temporal instabilities that may be present in the binary data entered. This is because the inverter circuits are biased to the required state by the inputted binary data before the clock pulse is applied to them. ^x '

The invention is not limited to a modulator with four phase values, but can also be used with higher values. In Fig. K the case is shown in which the

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Invention is used in a modulator with eight phase values o Two pairs of input connections 31, 32 and 2 + 1, Zf2 are provided · Each pair of input connections is connected to a circuit which essentially corresponds to the circuit shown in FIG. 1; Where appropriate, similar reference numerals are used, but the parts of the circuit which relate to the first pair of connections are given the prefix 3, while the parts of the circuit which relate to the second pair of connections, are provided with the prefix k »The clock pulses supplied by the pulse generator 6 are applied to the connection 5I; the control circuit for closed, intermittent information chains is not shown in order to increase the clarity of the representation. As can be seen from the figure, the clock pulses are passed through resistors 52 and 53; they can be earthed at the inputs to the inverter switches by electronic ON / OFF switches 5k or 55 _e

The high frequency signal generated by an oscillator 313 is passed to an additional f ~ 7 / k phase shifter 56 and then to a modulator ZfH and a 77/2 phase shifter.

From the analogy with the mode of operation of the circuit shown in FIG. 1, it follows that the combining arrangements 316 and ifl 6 each have a double sideband suppressed Can generate a carrier signal that has one of four phases at any one time. With the additional phase shifter 56 the combining array / + 16 produces a set of four Phases by 77A- from that by the combiner The sentence generated is offset. These phases are shown in Fig. 5; the four vectors 35 to 38 of of the combining assembly 316 and thus correspond to the

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Vectors in Fig. 3 which have been given similar reference numerals; vectors 61 through 64 are used by the combining device 416 received. The output signals of the combiner assemblies 316 and if 16 go to a combining arrangement

der / 52 and then to output 58 so that each in Fig.

5 phase vectors shown as the output phase of the phase shift key modulator can be used with eight phase values.

Which particular phase vector is assumed at any particular point in time depends on the instant Value of the binary data to be transmitted. Since eight values are available, a binary code with three digits be included; for example, assume that each vector in FIG. 5 is assigned a particular code value where the values increase counter-clockwise according to the following table:

Vector code

61,000

35 001

62 010

36 011

63 100

37 101

64 110

38 111

In practice, the three-digit codes are applied to some form of processor or processing device, which closes one or the other of the on / off switches 54 or 55 and the appropriate logical or binary Signal to one of the pair of inputs 41 or 42 or 31 or 32 for the data leads. For example, if the

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Switch 5k is closed, the combining arrangement 315 does not provide an output signal and the output vector is generated by the combining arrangement IfT 6 «

In practice, differential codes are used transmitted so that no phase reference signal has to be sent; in the present description it is assumed that the phase shift key modulator receives the data in the appropriate differential code converted form.

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Claims (1)

Claims Phase shift key modulator, thereby characterized in that an arrangement (7 »8) for receiving one or more pairs of binary Data representing input signals is provided, each for polarity modulation of clock pulse trains are used, which are taken from a common clock pulse source (6), and that the phase-modulated High frequency signals are combined, by the polarity modulated, by a given pair derived from input data signals pulses to form a high frequency signal with an instantaneous To generate phase angle from four previously determined, equally spaced phase angles is selected. Phase shift key modulator, characterized by a pair of inverters (7j 8) to convert depending on the input, binary data representing signals selected from a sequence of clock pulses to invert the each inverter (7 »8) are fed from a common clock pulse source (6), the clock pulses being a Have a duty cycle of substantially less than one to one, through a pair of phase modulators (11, 12), of each of which receives one of the sequences of clock pulses passed through the respective inverter (7 »8) and which phase modulate the high-frequency signals received by a local oscillator (13), wherein the high-frequency signals received at the two phase modulators (11, 12) have a relative 609886/0701 Have phase difference of / 7/2, and by an arrangement (16) for combining the phase-modulated signals / around a high frequency signal with an instantaneous To generate phase angle from four previously determined, equally spaced phase angles is selected. 3. phase shift key modulator according to claim 2, characterized in that each clock pulse has the duty cycle 25 % . if. Phase shift probe modulator according to one of the claims 2 or 3 »characterized in that a device is provided to the local oscillator (13) during the time periods between the carrier information chains to lock. 5 «phase shift key modulator according to claim if, characterized in that an additional device is provided to the common clock pulse source to block during the periods of time between the carrier information chains. 6. phase shift probe modulator according to claim 5, characterized characterized in that the local oscillator is activated at the beginning of a carrier information period is before the common clock pulse source is driven, and that at the beginning of the period between the carrier information chains the common clock pulse source is blocked before the local oscillator is blocked «. 609886/0701 Blank page