GB1533773A - Frame synchronisation arrangements for use in data transmission systems - Google Patents

Frame synchronisation arrangements for use in data transmission systems

Info

Publication number
GB1533773A
GB1533773A GB670876A GB670876A GB1533773A GB 1533773 A GB1533773 A GB 1533773A GB 670876 A GB670876 A GB 670876A GB 670876 A GB670876 A GB 670876A GB 1533773 A GB1533773 A GB 1533773A
Authority
GB
United Kingdom
Prior art keywords
frame
bit
synchronization
counter
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB670876A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB670876A priority Critical patent/GB1533773A/en
Publication of GB1533773A publication Critical patent/GB1533773A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase

Abstract

1533773 Multiplexing; frame synchronization PLESSEY CO Ltd 7 Feb 1977 [20 Feb 1976] 6708/76 Heading H4M In a T.D.M. data transmission system of the type having one synchronization bit per frame which is arranged to be the inverse of the immediately preceding data bit, there is provided a frame synchronization circuit which operates by accumulating for each bit in the frame a value indicative of the logarithm of the probability that that bit is the synchronization bit. As shown, the incoming 4 phase D.P.S.K. data stream I/P is used to condition the read-only memory ROM pre-programmed so as to generate incremented logarithm probability values which are applied, as ones or zeros, to control a probability accumulation counter PAC. The counter PAR cooperates with a random access memory RAM which has one location for each bit in a received frame and which is cyclically addressed by a frame counter FC, whereby the addressed RAM location contents are read out into the counter PAC and these contents are incremented by one or zero in accordance with the output of ROM before being loaded back into RAM. The RAM locations therefore accumulate over successive frames the aggregate probability of each bit of each symbol of the frame being the synchronization bit. The cyclic addressing and incrementing continues repetitively for each frame until PAC overflows and generates a frame synchronization pulse FSP to indicate that synchronization has been established.
GB670876A 1977-02-07 1977-02-07 Frame synchronisation arrangements for use in data transmission systems Expired GB1533773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB670876A GB1533773A (en) 1977-02-07 1977-02-07 Frame synchronisation arrangements for use in data transmission systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB670876A GB1533773A (en) 1977-02-07 1977-02-07 Frame synchronisation arrangements for use in data transmission systems

Publications (1)

Publication Number Publication Date
GB1533773A true GB1533773A (en) 1978-11-29

Family

ID=9819334

Family Applications (1)

Application Number Title Priority Date Filing Date
GB670876A Expired GB1533773A (en) 1977-02-07 1977-02-07 Frame synchronisation arrangements for use in data transmission systems

Country Status (1)

Country Link
GB (1) GB1533773A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794341A (en) * 1985-11-05 1988-12-27 Signal Processors Limited Digital filters and demodulators

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794341A (en) * 1985-11-05 1988-12-27 Signal Processors Limited Digital filters and demodulators

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930207