GB1427084A - Asynchronous digital multiplexer - Google Patents

Asynchronous digital multiplexer

Info

Publication number
GB1427084A
GB1427084A GB3560673A GB3560673A GB1427084A GB 1427084 A GB1427084 A GB 1427084A GB 3560673 A GB3560673 A GB 3560673A GB 3560673 A GB3560673 A GB 3560673A GB 1427084 A GB1427084 A GB 1427084A
Authority
GB
United Kingdom
Prior art keywords
pulse
read out
bit
stuffing
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3560673A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB3560673A priority Critical patent/GB1427084A/en
Priority to DE19742434869 priority patent/DE2434869A1/en
Priority to FR7425990A priority patent/FR2246129B1/fr
Priority to ES428643A priority patent/ES428643A1/en
Publication of GB1427084A publication Critical patent/GB1427084A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

1427084 Multiplex pulse code signalling STANDARD TELEPHONES & CABLES Ltd 26 July 1973 35606/73 Heading H4L In a multiplex digital data transmission system, incoming data received at interface 2 is written into an 8-bit store 3 under the control of clock pulses W derived from the data stream and is read out at a higher rate under the control of basic clock signals R modified for stuffing purposes by an inhibit gate 4 to provide read out pulses SR. Pulses SR and W are compared in phase at 5 and when they tend to coincide a trigger pulse is generated and supplied to a stuff store 6 which holes an instruction to stuff until it is enabled by a pulse SS, whereby the gate 4 is caused to block one pulse R. By this means the read out is delayed by one bit period and the duration of the previous bit is extended to cover two successive bit periods, a signal at 7 indicating that stuffing has taken place. Each frame is divided into four subframes, Fig. 2 (not shown) and certain time slots in subframes 2, 3 and 4 are used to transmit stuffing information and others in subframe are used for frame synchronization.
GB3560673A 1973-07-26 1973-07-26 Asynchronous digital multiplexer Expired GB1427084A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB3560673A GB1427084A (en) 1973-07-26 1973-07-26 Asynchronous digital multiplexer
DE19742434869 DE2434869A1 (en) 1973-07-26 1974-07-19 DIGITAL DATA MULTIPLEXER IN PLUG TECHNOLOGY
FR7425990A FR2246129B1 (en) 1973-07-26 1974-07-26
ES428643A ES428643A1 (en) 1973-07-26 1974-07-26 Asynchronous digital multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3560673A GB1427084A (en) 1973-07-26 1973-07-26 Asynchronous digital multiplexer

Publications (1)

Publication Number Publication Date
GB1427084A true GB1427084A (en) 1976-03-03

Family

ID=10379591

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3560673A Expired GB1427084A (en) 1973-07-26 1973-07-26 Asynchronous digital multiplexer

Country Status (4)

Country Link
DE (1) DE2434869A1 (en)
ES (1) ES428643A1 (en)
FR (1) FR2246129B1 (en)
GB (1) GB1427084A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923660B2 (en) * 1979-02-19 1984-06-04 株式会社日立製作所 Digital signal transmission method
DE2922338C2 (en) * 1979-06-01 1982-10-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Line termination device for broadband transmission links
FR2594277B1 (en) * 1986-02-13 1993-04-23 Houdoin Thierry DOUBLE LOOP PACKET SYNCHRONIZATION WITH PHASE LOCK
CN114489233B (en) * 2022-01-24 2024-06-11 上海华力集成电路制造有限公司 Phase-adjustable arbitrary waveform generator

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE349716B (en) * 1971-02-05 1972-10-02 Ericsson Telefon Ab L M

Also Published As

Publication number Publication date
FR2246129A1 (en) 1975-04-25
DE2434869A1 (en) 1975-07-03
FR2246129B1 (en) 1978-01-20
ES428643A1 (en) 1977-01-01

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee