GB1523123A - Cascaded converter - Google Patents

Cascaded converter

Info

Publication number
GB1523123A
GB1523123A GB44113/75A GB4411375A GB1523123A GB 1523123 A GB1523123 A GB 1523123A GB 44113/75 A GB44113/75 A GB 44113/75A GB 4411375 A GB4411375 A GB 4411375A GB 1523123 A GB1523123 A GB 1523123A
Authority
GB
United Kingdom
Prior art keywords
converter
outputs
output
word
transfer unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB44113/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecommunications Radioelectriques et Telephoniques SA TRT
Original Assignee
Telecommunications Radioelectriques et Telephoniques SA TRT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecommunications Radioelectriques et Telephoniques SA TRT filed Critical Telecommunications Radioelectriques et Telephoniques SA TRT
Priority to GB44113/75A priority Critical patent/GB1523123A/en
Publication of GB1523123A publication Critical patent/GB1523123A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

1523123 Analogue to digital converter TELECOMMUNICATIONS RADIOELECTRIQUES ET TELEPHONIQUES 27 Oct 1975 44113/75 Heading H3H In a cascaded a-to-d converter, for producing a Gray code, at least the first stage comprises a comparison unit K 1 having two comparators using references respectively above and below the average input value, and a transfer unit U 1 having a piece-wire straight line characteristic with discontinuities substantially at the reference values. For an input V 2 (Fig. 8) an output 24 passes to the next stage from the transfer unit while the comparator outputs, inverted, are passed to a word comparator 70 where words are compared as in Fig. 7. For word equality e9 = 1 and sign digit C forms output on d 1 , for b 1 a 2 b 3 a 4 greater, M = 1 and these form outputs on d 2 -d 5 and d, and vice versa when M = 0. The transfer characteristic slopes may have a companding effect and the digital output may be clocked (Fig. 14, not shown). The converter is said to be sensitive to small fluctuations around its zero point with amplifier drift, only affecting higher significance outputs.
GB44113/75A 1975-10-27 1975-10-27 Cascaded converter Expired GB1523123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB44113/75A GB1523123A (en) 1975-10-27 1975-10-27 Cascaded converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB44113/75A GB1523123A (en) 1975-10-27 1975-10-27 Cascaded converter

Publications (1)

Publication Number Publication Date
GB1523123A true GB1523123A (en) 1978-08-31

Family

ID=10431847

Family Applications (1)

Application Number Title Priority Date Filing Date
GB44113/75A Expired GB1523123A (en) 1975-10-27 1975-10-27 Cascaded converter

Country Status (1)

Country Link
GB (1) GB1523123A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084841A (en) * 1989-08-14 1992-01-28 Texas Instruments Incorporated Programmable status flag generator FIFO using gray code
WO1996015593A1 (en) * 1994-11-10 1996-05-23 National Semiconductor Corporation Radix 2 architecture and calibration technique for pipelined analog to digital converters
US6124820A (en) * 1997-11-20 2000-09-26 National Semiconductor Corporation Error correction architecture for pipeline analog to digital converters

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084841A (en) * 1989-08-14 1992-01-28 Texas Instruments Incorporated Programmable status flag generator FIFO using gray code
WO1996015593A1 (en) * 1994-11-10 1996-05-23 National Semiconductor Corporation Radix 2 architecture and calibration technique for pipelined analog to digital converters
US5668549A (en) * 1994-11-10 1997-09-16 National Semiconductor Corporation Radix 2 architecture and calibration technique for pipelined analog to digital converters
US6124820A (en) * 1997-11-20 2000-09-26 National Semiconductor Corporation Error correction architecture for pipeline analog to digital converters
US6304204B1 (en) 1997-11-20 2001-10-16 National Semiconductor Corporation Error correction architecture for pipeline analog to digital converters

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee