GB1518829A - Interference prevention in computer - Google Patents

Abstract

1518829 Interference prevention HONEYWELL INFORMATION SYSTEMS Inc 23 Dec 1975 [30 Dec 1974] 52579/75 Heading G4A A computing system includes a protection system for preventing interferences between processes based on a continuously updated record of the history of utilization of resources. There may be a set of utilization tables, Fig. 4, one for each resource and indicating the processes (A-D) which have previously accessed that resource and whether each access was a read (R) or write (W), and a matrix, Fig. 5, of the relationship between processes resulting from the sequential accessing of the resources by the processes; when a new access is requested the utilization tables are accessed to determine new relationships between processes implied by the request and it is then determined from the matrix whether the new access would violate rules of interference and thus should be denied. If a new relationship already exists in the matrix the access is allowed whereas if its inverse exists explicitly or implicitly in the matrix the access is denied; if neither exists the access is allowed, the utilization tables and matrix being updated after each access. In the matrix of Fig. 5 0 indicates no direct relationship between the processes, 1 indicates "follows but does not depend upon" (write follows read) and 2 indicates "follows and depends upon" (read or write follows write). Thus the accesses shown in dotted lines for resource R 4 in Fig. 4 would be denied. If a read access is denied the access is routed to an earlier generation of the resource if such is available and reading of it would not produce interferences. If this is not possible, or for a denied write access, the process which interferes with the requested access is aborted, as are any processes depending thereon and the system is restored to its state prior to execution of the aborted processes. The aborted processes are subsequently re-run. The computing system operates under the control of microinstructions partially stored at the time of system initialization, some of the microinstructions being stored in a hardware area of the main memory (11, Fig. 1, not shown), some in programmable read-only and random access memory in the processing unit and some in read-write and read-only storage sections of control stores (42, 52, 62, Fig. 1, not shown) in peripheral subsystems. Details of the form of the microinstructions and nested branches are given.