GB1517926A - Electronic stores - Google Patents

Electronic stores

Info

Publication number
GB1517926A
GB1517926A GB36980/75A GB3698075A GB1517926A GB 1517926 A GB1517926 A GB 1517926A GB 36980/75 A GB36980/75 A GB 36980/75A GB 3698075 A GB3698075 A GB 3698075A GB 1517926 A GB1517926 A GB 1517926A
Authority
GB
United Kingdom
Prior art keywords
cells
gate
floating
control
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB36980/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19742445078 external-priority patent/DE2445078C3/en
Priority claimed from DE19752505821 external-priority patent/DE2505821C3/en
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1517926A publication Critical patent/GB1517926A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor

Abstract

1517926 FET storage matrix SIEMENS AG 9 Sept 1975 [20 Sept 1974 12 Feb 1975] 36980/75 Heading H1K [Also in Division G4] In an electronic store consisting of a matrix of storage cells, each consisting solely of an N- channel storage FET with a floating gate and a superposed control gate both of which control the main current path of the FET and so constructed as to permit programming by negative charging the floating gate by channel injection, at least some of the corresponding terminals, e.g. sources, drains or channel of at least some of the cells are connected together. In the embodiment, Fig. 2, the control gates of all cells in a row are connected to the respective X-conductor, the drains of all cells in a column to the respective Y-conductor, and the sources of all cells in the matrix to a common point S o , which may be earthed by connection to S U , placed at voltage U by connection to R U , or left floating. The cells may be formed on a common semiconductor substrate which may be earthed or left floating and may also include the control circuitry S t though the store and control circuitry may alternatively be in separate epitaxial semiconductor layers on a common substrate of spinel or sapphire. The construction enables voltages to be applied to programme the cell individually by storing electrons on their floating gates and to read the state of individual cells. Stored information may be erased from individual cells, or from all cells in a row or the matrix simultaneously. Such simultaneous erasure can be achieved with minimal heat generation if the FETs are of the enhancement type, by using the Fowler- Nordheim tunnelling or, if the floating gates are of P-doped polycrystalline silicon more than 1000 Š thick, by the gate surface effect mechanism. The tunnelling mechanism requires application of a direct voltage or series of pulses between control gate and source, drain or channel region with the others of these regions floating, while the gate surface effect requires a train of pulses with steep leading flanks, e.g. with a frequency of 100 KHz to 1 MHz and a keying ratio of 1 : 1. In either case voltage pulses are applied with the control gate held at a fixed potential, such as earth. The thickness of insulation between the floating gate and substrate is so chosen e.g. at 600 Š to avoid partial discharge of a cell by drain avalanching when its drain is connected in common with that of another cell being programmed, and to prevent avalanche effect at a reverse-biased PN junction in the main current path of the FET making a major contribution to erasure of the cell. Lower operating voltages can be used if the capacity between the control and floating gates greatly exceeds that between the floating gate and substrate, and contamination of the gate insulation of the gate insulation, reduced by so operating that the programming and erasure currents pass through spaced portions of it.
GB36980/75A 1974-09-20 1975-09-09 Electronic stores Expired GB1517926A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19742445078 DE2445078C3 (en) 1974-09-20 Electronic memory produced using integrated technology
DE19752505821 DE2505821C3 (en) 1975-02-12 1975-02-12 Method for operating an electronic memory produced using integrated technology

Publications (1)

Publication Number Publication Date
GB1517926A true GB1517926A (en) 1978-07-19

Family

ID=25767729

Family Applications (1)

Application Number Title Priority Date Filing Date
GB36980/75A Expired GB1517926A (en) 1974-09-20 1975-09-09 Electronic stores

Country Status (9)

Country Link
JP (1) JPS5158078A (en)
BE (1) BE833630A (en)
CH (1) CH607234A5 (en)
DK (1) DK423175A (en)
FR (1) FR2285678A1 (en)
GB (1) GB1517926A (en)
IT (1) IT1042649B (en)
NL (1) NL7510941A (en)
SE (1) SE7510482L (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2143698A (en) * 1981-01-14 1985-02-13 Toshiba Kk Semiconductor integrated memory circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654693A (en) * 1979-10-05 1981-05-14 Hitachi Ltd Programable rom
JPS6284496A (en) * 1986-08-25 1987-04-17 Hitachi Ltd Programmable rom

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS526148B2 (en) * 1972-05-18 1977-02-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2143698A (en) * 1981-01-14 1985-02-13 Toshiba Kk Semiconductor integrated memory circuit

Also Published As

Publication number Publication date
NL7510941A (en) 1976-03-23
JPS5158078A (en) 1976-05-21
BE833630A (en) 1976-03-19
FR2285678B1 (en) 1979-03-23
IT1042649B (en) 1980-01-30
CH607234A5 (en) 1978-11-30
FR2285678A1 (en) 1976-04-16
DK423175A (en) 1976-03-21
SE7510482L (en) 1976-03-22

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee