GB1491592A - Electrical integrated circuit chips - Google Patents

Abstract

1491592 Distributers PLESSEY CO Ltd 23 Dec 1975 [8 Jan 1975] 735/75 Heading H4M To provide on one i.e. chip circuits performing analogue functions and circuits performing logic functions, a chip accommodates a series of bipolar transistor amplifiers, each amplifier having an input potential terminal, a reference potential terminal, a control terminal to which a constant current enabling pulse may be applied, and two output terminals across which an analogue output potential difference is delivered on the coincident application of an input signal potential and of a constant current enabling pulse, the magnitude of the analogue output being proportional to the difference between the input signal potential and the reference potential; the chip also accommodating sequence switching means, whereby an enabling pulse of constant current value is applied to the control terminals of each amplifier of the series in turn. In Fig. 1 each of the bipolar transistor amplifiers consist of first and second transistors, e.g. T10, T11 the first transistor having its base connected to the input terminal il, and the second having its base connected to the common reference terminal r, the emitters of the transistors being commoned and connected to the control terminals, e.g. C1 and the collectors of the transistors are connected to output terminals 010, 011. With loads (not shown) which may or may not be accommodated on the chip across the output terminals, an enabling pulse on c1 causes T11 to conduct and input il causes T10 to conduct hence load potential is proportional to difference in base potential of T10, T11 &c. Weighting may be introduced by inserting serial collector resistors. In addition to amplification, if continuous signals are applied to terminals i1-in combined sampling and multiplexing are performed. With terminals i1-in derived from a static store the arrangement acts as a parallel/series converter. In an alternative arrangement Fig. 2 (not shown) output terminals (018,019) &c. may have individual loads connected thereacross but input (i) and reference terminal r are respectively commoned to alternate bases. A sequential potential applied to (cl) &c. will cause potentials across pairs of terminals to be proportional to difference in signal values applied to (i, r). A continuous signal on (i) enables the circuit to act as a combined sampler and distributer. A constant amplitude input signal creates a pulse generator. The circuit of Fig.2 may be presented as a load for Fig. 1 by connecting terminal 010 to terminal (r). If in this connection both devices S are run in synchronism the joint arrangement serves as a demultiplexer or series/parallel converter, also enables signals to be passed from one chip to another using a minimum number of leads between chips. The sequencing device may comprise a shift register or counter.