GB1491357A - Charge transfer devices - Google Patents

Abstract

1491357 Electronic counters WESTERN ELECTRIC CO Inc 14 May 1975 [16 May 1974] 20339/75 Heading G4A [Also in Division H1] A charge-coupled binary counter for counting up to 2n-1 signal pulses includes, in a semiconductor substrate 10, a charge-coupled "quantizer" 12 for providing a predetermined quantity of charge in response to each signal pulse, a sequence of n charge-coupled "threshold cells" 14À1, 16À1, 18À1 the first of which receives charge from the quantizer, each threshold cell 14.1 &c. having at its input a first potential barrier (e.g. 12.5) such that substantially all charge will transfer into that threshold cell from a preceding cell on suitable energization of the electrodes and having at its output a second potential barrier (e.g. 14.3) of greater height than the first barrier such that charge is transferable across the second barrier only when two of said predetermined quantities of charge are in that cell and, for at least the first n-1 of the n threshold cells, feedback means responsive to charge transferred across the second barrier for removing residual charge remaining in that cell. In the illustrated counter n = 3, there being three charge-coupled threshold cells 14.1, 16.1, 18.1 at least the first two of which are followed in the counter sequence by charge-coupled transfer cells 14.2, 16.2. The quantizer 12 comprises two charge-coupled cells 12.1, 12.2, the cell 12.1 being supplied with charge by an input diode 11. The first (dot-dashed) and second (double dotdashed) potential barriers, as well as charstop barriers such as 12.7, 8 defining the lateral edges of the devices, may be formed as diffused or implanted elongate strips. The feedback means associated with each of the first two thresholds cells of the counter include, in addition to the associated transfer cell (e.g. 14.2), a grounded source IGFET 17 which is open-circuited by the presence of charge in the transfer cell 14.2. As a result a charge-coupled "dump gate" 15 connected to the threshold cell 14.1 is opened to drain residual charge from the cell 14.1, resetting the cell to the "0" state while the next cell 16.1 switches to the "1" state as a result of the transfer of charge thereto from the preceding transfer cell 14.2. All the dump gates 15 can be simultaneously opened by a "read control" signal from IGFET 111, so as to dump the storage charges across loads (e.g. 20) via charge-sensing IGFETs 19, 21, 23 to permit read-out.