DE2521467A1 - CHARGE TRANSFER BINARY COUNTER - Google Patents

Description

BLUMBACH · WESER · BERGEN KRAMER ZWIRNER · HIRSCH

PATENT LAWYERS IN MÖNCHEN AND WIESBADEN 2521467

Postal address Munich: Patentconsulr 8 Munich 60 Radedtestraf) 43 Telephone (089) 883603/883604 Telex 05-212313 Postal address Wiesbaden: Patentconsult 62 Wiesbaden Somenberger Stra # e 43 Telephone (0 * 121) 562943/561998 Telex 04-186237

Western Electric VJLLDiW, B.H. 8

Company, Incorporated

222, Broadway

New York, N.Y. 10038
US5 "

Charge transfer binary counter

The invention relates to a charge transfer binary counter for counting aaximal 2 ^ -I in a special time interval occurring signal pulses) »with a charge storage medium and a plurality of electrodes for transferring charge in the medium.

The charge coupling technology that has emerged recently has led to the occurrence of the now known shift register

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directions (in the following also under the known name CCB ₁ an abbreviation of the term Charge · Coupled Devices used in the English-language tree), the production of the system is advantageously simplified. For example, a shift register and AND gate could be fabricated on a single die using well known integrated circuit technology. In addition, interface problems, such as impedance matching and exposure to stray capacitances, would be reduced.

These problems are solved according to the invention by a charge transfer biological counter of the type mentioned at the beginning, which is characterized in that a quantizer with a first electrode arrangement is provided. to form at least one IJadungsspeicher-Q cell _s ervermag in the medium, the "upon the occurrence of jades signal pulse a predetermined charge packet su, d B, a second electrode assembly is provided to form a Mehrsahl νοΏ η Ladunggspeicher-Schwellenin desi _Mtdiin>:. ven which at least one © so arranged

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has a second potential barrier at its output, wherein the area of "each threshold value cell and the height of the second barrier are matched to one another in such a way that Charge transfers across the second barrier only occur when two of the charge packets are transferring into the threshold cell and that a feedback device responsive to charge passing through at least the first of the second barriers is provided to remove residual charge in at least the first of the Threshold cells

The invention provides a charge transfer binary counter which can count the number (from 0 to ^ -I) of charge packets in a particular time interval. The charge packets can, for example, have been generated by signal pulses in a PCM (pulse code modulation) system, and the time interval can form a "word" or a frame in PCM terminology. In one embodiment, the binary counter comprises a charge storage medium in which at least one charge storage "Q cell" is formed which is capable of quantizing each signal pulse into a packet of charge Q i · In. Row with the Q cells are η one-bit shift registers, each - with the possible exception of the last - have first and second charge storage cells that are connected in series. Adjacent cells of the same shift register are from each other

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separated by a threshold potential barrier of size Ym, which only allows partial transfer of the charge across them. On the other hand are neighboring cells successive shift registers separated from each other by smaller potential barriers of size V ^, the one allow practically complete charge transfer across them. In a preferred embodiment, V, j is about equal to 1.5 Vn »if the Q cells have an area A and at least the first cells of each shift register each have an area 2A. Adjacent cells of the device are connected to opposite phases of a two-phase clock. Between neighboring cells of the same Shift register is formed to provide a feedback path Remove residual charge from the first cell whenever charge has been transferred above its threshold barrier. At the end of the special time interval (e.g. of a word or a frame), however, there is a quasi-permanent one State reached, i.e. the charge transfer stops until a read operation is performed or the next word arrives. In the quasi-steady state, the charge packets in the first cells correspond to the shift register the binary equivalent of the number of signal pulses in the word.

In the drawing show:

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Figure 1 is a top plan view of a binary counter accordingly an embodiment of the invention;

FIG. 2 is a schematic plan view of the binary counter of FIG Figure 1, in which the electrodes for simplicity is omitted and a barrier grid configuration is shown in solid lines;

3 schematically shows the quantizer and the first shift register of Figure 2; and

Fig. 4 ″ to 8 show the surface potential of the various cells of Figure 3 at different times during the clock cycle. For the sake of simplicity, it has been assumed that the Voltage drop across the insulating layer (oxide) of the storage medium is negligible, so that the / the Surface potential (s) approximately equal to that applied Tension is / are.

Fig. 1 shows a plan view of a binary counter according to an embodiment of the invention. The counter 10 includes a storage medium 10.1, which is, for example, a p "* -conducting semiconductor substrate such as silicon which an insulating layer (shown) is formed, typically of thermally grown silicon dioxide

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consists. There are several rectangular charge storage cells in the substrate, their boundaries by dashed and dot-dash lines Marked are. These boundaries, called barrier grids, are established in the substrate, for example, by ion implantation or diffusion of streaks of immobile charge (i.e., impurity centers) in that disclosed in U.S. Patent No. 3,789,267 Kind generated.

The barrier grid is made up of charge strips with three different ones Potential heights together:

1) Channel stop barriers (dashed lines) designed to prevent charge transfer across them. As described in U.S. Patent No. 3,728,161, the purpose of the channel stopper barriers is to prevent unintentional Inversion of the surface of the IC (integrated circuit) semiconductor chip to be switched off due to capacitive coupling between metallization and / or field oxide in the semiconductor substrate. If such a coupling were strong enough to invert the semiconductor surface, current could flow between neighboring devices flow in the form of leakage current or even short-circuit elements of a single device.

2) Barriers to transmission (dot-dash lines), with one for typical height of an n-channel device, i.e. the application of the

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usually positive clock voltage should be applied to the barrier zone allow full charge transfer. Any transmission barrier is arranged asymmetrically with respect to the center of the overlying electrode, about a flow of charge to effect in a predictable direction. and

3) threshold barriers (double dot-dash lines) that have such a height that charge is only transferred across them if two charge packets are in the preceding one Cell have been transferred.

In addition, the boundaries of diffusion zones for diodes, IGIGs and the like are shown by dotted lines.

The three types of potential barriers in the grid define a quantizer 12 and three (n = 3) one-bit shift registers 14 ·, 16 and 18, which are able to count the number of charge packets in a special time interval up to a maximum of 2 ^ -I = 7. In binary notation, the outputs correspond to

Shift registers 14, 16 and 1§ have the powers of two as follows: 2 °, 2 ^Λ and 2 ^2, respectively.

The quantizer 12 has at least one charge storage cell (hereinafter referred to as a "Q cell") of the area A with a charge-carrying capacity Q on. Thus everyone generates to be counted

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Signal pulse an amount of charge Q in the Q-cell. For reasons to be explained later, the quantizer of FIG. 1 comprises a first and a second Q-cell 12, 1 and 12.2, which each have an area A and are arranged in series with one another. Transmission "barriers are arranged at 12.4 between the first and second Q-cells 12.1 or 12.2 and at 12.5 between the second Q-cell 12.2 and the first shift register 14-. A transmission barrier can also be arranged at 12.3 if the input device 11 is a charge storage cell of a preceding CCD device. However, if the input device 11 is a diode as shown, then the interface at 12.3 indicates an edge of an n ⁺ diffusion zone. On the other hand, channel stop barriers are located at 12.7 and 12.8 In addition, a pair of electrodes 12.9 and 12.10 overlies the first and second Q-cells 12.1 and 12.2, respectively, and these electrodes are connected to opposite phases of a two-phase clock 100.

In the same way, the first shift register 14 has first and second charge storage cells 14.1 and 14.2, which are arranged in series with one another. The aforementioned transfer barrier 12.5 is between the first cell 14.1 of the shift register 14 and the second Q-cell 12.2 of the quantizer. A threshold barrier is at 14.3 between

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the first and second cells 14.1 and 14.2 arranged. A pair of electrodes 14.7 "and 14.7" are located above cells 14.1 and 14.2. 14.8 connected to opposite phases of clock 100.

As will be described in more detail below, in order to remove residual charge from the first cell 14.1 after charge has been transferred across the threshold barrier 14.J, a feedback path is established between the first and second cells 14.1 and 14.2. For example, this path comprises an IGEET 17 »which is usually grounded with its source and whose gate electrode 17.1 is in contact with an n ⁺ diffusion gate zone 14.6 which is partially overlapped by the electrode 14.8. The drain electrode 17 * 2 actuates a clearing gate 15 coupled to the first cell 14.1.

The evacuation gate 15 has an adjacent to the first cell 14.1 Charge storage cell 15-1 and includes a transfer barrier 14.5 at the interface between the two. An electrode 15-3 overlies cell 15-1 and is connected to the drain 17.2 of the IGlET 17. Charge transferred into the second cell 14.2 of the first shift register 14 causes over the IGiET 17 applies a voltage to the clearing gate electrode 15-3 is placed, and thus has the effect that residual charge is emptied from the first cell 14.1 in the Ausräumgatterzelle 15.1. To the rest

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To remove charge from the Ausräumgat.ter becomes an IGFET-Dipde 25 is used as will be described below.

In addition, a gate electrode of a 19.1 ^L adungsfühler- XGFET is connected to the diffusion region 1fj η "2 extending below the electrode 15.3. The drain of IGEET 19 is connected to a load, indicated schematically by resistor 20. The voltage at the output terminal 20.1 corresponds, if it is read at a prescribed point in time such as the end of a word, to the first digit of a three-digit binary number. In other words, the presence of a voltage at connection 20.1 corresponds to a binary number 2.

For brevity, no detailed description of the second and third shift registers 16 and 18 and their respective feedback paths will be given. It will be understood that the construction of these components as well as the circuit connections are identical to that described with regard to the first shift register 14 with one exception. The exception is that the third shift register, and generally the nth shift register, need not include a second cell, since no charge can be transferred across the last threshold value barrier if the maximum number of signal pulses in any given word is 2 ⁿ - 1 is. Accordingly, the nth shift register does not need a feedback path as described

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kind.

As "already mentioned, in the quasi" steady state, as at the end of a word, the charge in the first cell of each shift register "represents the binary equivalent of the number of pulses in the word. A read control is used to obtain the desired count The read controller 110 is shown for simplicity as a single IGIET device 111 connected by a manifold to each of the purge gates. The manifold represents separate lines from the read controller 110 to each of the purge gates, and in practice More than one IGi ¹ EO? 111 can be used, for example an IGEET for each clearing gate, with an individual connection to this point. A clock cycle counter 120 dst connected to the clock generator 100 and activates the read control 100 after a predetermined number of clock cycles gives a suitable voltage to the discharge gate electrodes, which causes that possibly existing charge from the first cells of the shift register is transferred into the evacuation gate cells. As a result, voltages appear at the drain connections of the IGEETs 19 , 21 and 23 (ie. At the output connections 20.1, 30.1 and 40.1), depending on which of the first cell charges contained. with the

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Connected to diffusion zones which adjoin the evacuation gate cells of the first, second and third shift register, to create a path through which the charge in the evacuation gate cells can flow to the substrate (earth). In Usually the gate and drain of every IGEET diode are shorted together and connected to a bias voltage source 130. Thus, reading clears the presence of In the first cell of each shift register, load these cells too and make them ready for the next counting operation (e.g. the arrival of the next word). The read and erase operations are described in more detail below.

Assume that the duration of a clock cycle is equal to the time Distance between adjacent pulse positions occurs under the control of counter 120 and read control 110 read operation performed after an integer number of clock cycles when an even number of Q cells in the quantizer 12 is used, but occurs after an integer number of half cycles when using an odd number of Q cells will. The exact number of clock cycles after which a read operation is performed depends on design considerations, like the maximum number of pulses in a word, which in turn determines the number η of shift registers required in the counter will. However, the outputs 20.1 correspond to each pail,

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30.1 and 40.1 in "binary representation powers of two like

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follows: 2.2 "or 2. If output voltages at the connections 20.1 and 30.1, but not present at the connection 40.1, this consequently corresponds to the binary number 110, which is a decimal 3 is the same, i.e. the detected word had three impulses.

The operation of the device according to the invention will now be described with reference to the schematic representation in the figures 2 and 3 ". For clarity of illustration, the electrodes have been omitted and the barrier grid is by means of shown in solid lines. Corresponding components have been given identical reference numbers in FIGS. 1 and 2. Although the clock device is not shown, it should be understood that "adjacent cells of each shift register are connected to opposite clock phases as in Fig. 1. Note that the last shift register 18 ' has only a first cell 18.1. As already explained, a second cell or a feedback path is not required. In addition, the understanding of the method of operation according to the invention is facilitated if one assumes a preferred embodiment in which the Q cells of the quantizer each have one Area A and the cells of the shift registers have an area 2A, the threshold value barriers Vg-, approximately 1.5 Vg and the voltage swing of the clock voltage, about Vg (Fig. 3)

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It is assumed that the input signal is a PCM word with a maximum of seven pulse time slots, three of which contain signal pulses. During phase 1 of the clock cycle, the first signal pulse is applied to the quantizer 12, which generates a charge packet Q in the first Q cell. The packet.Q is transmitted via the transmission barrier 12.4 into the second Q cell and then via the transmission barrier 12.5 into the first cell 14.1 of the first shift register 14 by means of two-phase clocking. This first packet is temporarily prevented from further transmission by the threshold value barrier 14.3; that is, because of the larger area (2A) of cell 14.1, the charge Q only half fills the cell. More specifically, an amount of charge Q in a cell with an area A reduces its surface potential by an amount equal to Vg, while the the same amount of charge Q in a cell with outer area 2A only reduces the surface potential by 0.5 Vg. Consequently, during phase 2, when the threshold value _{barrier is reduced from 1.5 V β} to 0.5 ^V -n, which is equal to the surface potential of cell 14.1, no charge is transferred into cell 14.2 (FIG. 5).

Then the second signal pulse is given to the quantizer 12, which another packet with the charge Q in the first Q-cell generated. This is achieved by means of two-phase clocks

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The second charge packet Q is similarly transferred via the second Q cell to the first cell 14.1, where, as you may remember, the first packet with the charge Q is waiting, there is now a charge of the Henge ZQ in the first Cell 14.1, This charge reduces the surface potential of the first cell 14-, 1 by about Yg (! "Fig. 6}. If during phase 2 of the clock cycle the surface potential tauter of the second cell 14.2 of the first shift register by the amount Tig If the clock voltage excursion or the change caused by the clock voltage) is increased, the effective threshold value barrier is consequently reduced from 1.5 Tg to 0.5 Vg, since the surface potential in the first cell 14.1 is 0.4 Yd less than the reduced threshold value barrier half of the! charge 2 £ J (d, h, Q) is transferred to the second cell 14.2 (Fig. 7) and then into cell 16.1 (I ¹ Ig. 8) .Therefore, the second cell 14.2 receives charge only after the Transfer of two charge packets to the first cell 1 4.1,

When this process is complete, the first cell 14.1 of the first shift register 14 is still half full, i.e. it contains an amount of charge Q (Pig. 8) · This excess charge becomes derived before the next pulse arrives at the first cell 14.1, by means of a Hitskkopplungsweges, the Ausräumgatter 15 "and the IGHED inverter 17 (Pig-2} includes. In short, the ISISI inverter 17 is through the

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Presence of charge in the second cell 14.2 in an open circuit. The resulting increase in its drain voltage opens the discharge gate 15 · Excess Ladurig in the first Cells of the other shift registers, with the exception of the last shift register 18 ', are cleared out in the same way or turned off.

During the next half clock cycle, the charge packet will Q in the second cell 14.2 is transferred to the first cell 16.1 of the second shift register, where it responds to the arrival of a another charge package is waiting. This counting process is continued as long as subsequent charge packets are generated by the quantizer as a function of the applied signal pulses of the PCM word. This creates a third charge package transported along the device in the same way as the first and second charge packets until it reaches the first Reached cell 14.1, where it waits for the arrival of the next charge packet due to the threshold value barrier 14.3, if there is one. Since it has been assumed that the word contains only three signal pulses, there is a quasi-permanent state reached (i.e. no further charge transport occurs). At the end of the word, that by counting the clock cycles can be determined (namely by counter 120, Pig. 1), the read control activates all clearing gates, so that at the output connections 20.1 and 30.1

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Voltages appear, but not at connection 40.1. So is the binary output signal 110, which is equal to the decimal three, the number of pulses in the PCM word. After the read operation is performed, the first cell of each shift register is cleared or cleared, so that the counter is used to count the number of pulses in the next word.

In the same way, any number of charge packets from 0 to 7 in a given word can be created using the arrangement of the Pig. 2 are counted. In general, a larger number of charge packets up to a maximum of 2 ⁿ -1 can be counted by using a large number of η shift registers of the type described.

The read and erase operations are described in more detail below. The read controller 110 includes an IGPET 111, the drain of which is connected to a source 130 of a voltage Vg, the source of which is connected separately to each evacuation gate electrode and the gate of which is connected to the clock cycle counter 120. In practice, the IGPET 111 can be fabricated on the same die as the binary counter and, as indicated earlier, can comprise multiple IGPETS. Depending on whether an erase or a read function is to be performed, the clock cycle counter 120 outputs one of two voltages Vg = V or V ^ = Vg> V to the gate of the IGPET 111. For erasing, V _R = V _& , so that the conductance of the

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IGFET 111 has a Vert g ^ = .g ^ X gj, where g ^ - is the conductance of the IGPET 17, for example, when there is no charge in the cell 14.2. As a result, the potential at the evacuation gate 15 is approximately zero and no erasure occurs. If, however, an amount of charge Q has been transferred into cell 14.2 via threshold value barrier 14.3, IGPET 17 is switched off and the potential at clearing gate 15 is approximately Vg, so that cell 14 »1 is erased. When reading, on the other hand, there is no charge in cell 14.1 in the quasi-steady state, so that IGFET 17 conducts and has a conductance gj. For reading, the clock cycle ^{counter 120 V a} * ^{s0 that the line value of the IGFE} T 111 is now one

Has value gg = g ^ yy gj. As a result, the potential at evacuation gate 15 is approximately Vg, and charge in cell 14.1 flows through the channel under the evacuation gate to the gate of IGFET 19, which generates a signal at output terminal 20.1. The first cells of the other shift registers are erased and read out in the same way.

Even if it was pointed out that the last shift register need not have a "second cell" or feedback path, it should be noted that in some Cases where the pulse count is high enough, a charge 2Q reaches the last cell and Q over the last threshold barrier is transmitted. So it can be desirable

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to dissipate this transferred charge in that, for example, a diode is coupled to the last cell of the last shift register will.

In order to create a path from the read control 110 via the electrode of the last clearing gate (for example 45 in FIG. 2) to ground, an IGJB ¹ ET 112 is additionally provided, its drain connected to this electrode, its source grounded and its gate connected to the Bias source (ie Vg) is performed. Thus, IGFET 112 is always conductive, but functions in essentially the same way as inverters 17 and 37 in creating a connection to ground.

If you look at the subject matter from a slightly different point of view Considered from FIG. 1, it can be viewed as having a quantizer 12 and a plurality of η threshold cells (14.1, 16.1 and 18.1), each of which has a transmission barrier (12.5, 14.4 and 16.4) at their entrance and one Includes threshold value barrier (14.3 »16.3 and 18.3) at its output. A coupling device in memory cells 14.2 and 16.2, IGFET inverters 17 and 37 and clearing gates 15, 35 and 45) speak for charge transferred across each threshold barrier to remove residual charge in the threshold cells.

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Claims (4)

BLUMBACH · WESER · BERGEN · KRAMER ZWIRNER - HIRSCH PATENT LAWYERS IN MUNICH AND WIESBADEN Postal address Munich: Patentconsult 8 Munich 60 Radeckestrasse 43 Telephone (089) 883603/883604 Telex 05-212313 Postal address Wiesbaden: Patentconsult 62 Wiesbaden Sonnenberger Straße 43 Telephone (06121) 562943/561998 Telex 04-186237 Claims Ci.Jfl ^ formation transfer binary counter for counting a maximum I signal pulses occurring in a specific time interval, having a charge storage medium and a plurality of electrodes for transferring charge in the Medium, characterized in that a quantizer (12) having a first electrode arrangement (12.9 »12.10) is provided for the formation of at least one charge storage Q-cell (12.1, 12.2) in the medium, which in the Occurrence of each signal pulse a predetermined charge packet able to generate that a second electrode arrangement (14.7) is provided to form a plurality of η charge storage threshold cells (14 *. 1, 16.1, 18.1) in the medium, at least one of which is arranged to be transmitted from the quantizer Can receive cargo, that each threshold cell has a first potential barrier at its input (12.5, 14.4-, i € .4), over which at Applying a suitable voltage to the second electrode arrangement practically all of it in a preceding cell S09848 / 0828 The charge present is transferred into this threshold cell, and that it has a second potential barrier at its output (14.3, 16.3 »18.3), where the area is a each threshold cell and the height of the second barrier are coordinated in such a way that charge transfers only occur across the second barrier if two of the charge packets have been transferred into the threshold cell, and that a feedback device (17j 15-3) »the on Charge that has been transferred across at least the first (n-1) of the second barriers is intended for Removal of residual charge in at least the first (n-1) of the threshold cells. 2. Charge transfer binary counter according to claim 1, characterized by a third electrode arrangement (14.8) for generating a plurality of charge storage transfer cells (14.2, 16.2) in the medium, with a transmission cell between each pair of threshold cells (14.1, 16.1) is arranged so that charge that is transferred across the threshold barrier of the preceding cell is collected by the transmission cells, and a control device (14.6, 17.1, 17, 17.2, 15.3 »15-1» 14.5) »responds to the charge transferred into the transfer cell, to remove those in the threshold cells Remaining charge. · ' 609848/0828 252U67 3. Charge transfer binary counter according to claim 2, characterized in that the control device a clearing gate electrode assembly (15 x 3) has for the formation of η charge storage evacuation cells (15 x 1) in the medium, which is sent to separate one of the η threshold cells adjoin, and a plurality of IGFETS (17) whose gates (17-1) with the corresponding transmission cells, but at least with the first (n-1), are connected, and with one of them Control electrodes (17.2) are connected to corresponding clearing cells, but at least to the first (n-1) of the clearing cells are, furthermore a device (25) for discharging charge in the evacuation cells. 4. Charge transfer binary counter according to claim 3 »characterized by a clock cycle counter (120) and a responsive reading device (110) for activating the evacuation cells in such a way that Charge in the threshold cells at the end of a time interval va valls is transferred to the evacuation cells, with the presence or absence of charge "in the k-th Clearing cell of the kth binary digit with a decimal equi- k-1
corresponds to valentine 2. 5- charge transfer binary counter according to claim 4, characterized by a two-phase clock generator (100) and a coupling device for coupling 509848/0828 alternating cells of the Q cells, threshold cells and transmit cells on opposite phases of the clock. 509848/0828 Blank page