GB1484331A - Computer system - Google Patents

Abstract

1484331 Synchronizing computers TELEFONAKTIEBOLAGET L M ERICSSON 24 Oct 1974 [30 Oct 1973] 46126/74 Heading G4A A computer system comprises substantially identical executive and reserve computers E, R respectively, each computer comprising a number of functional units FU connected to one another via timing buses tb, order buses ob and data buses db, the reserve computer being able to work synchronously and in parallel with the executive computer by means of clock pulses from a clock pulse generator CG applied to the computers via start devices SDe, SDr respectively, data being transferred unidirectionally from the executive computer to update the reserve computer via a data transferring channel DCH which incorporates a time delay, the reserve computer being started subsequent to the start of the executive computer after a time delay substantially equal to the time delay of the data transferring channel. The data transferring channel is opened if necessary, to prevent transfer of faulty data within the reserve computer, by means of a signal ts, representing the "transfer state" of the system and stored in a control memory CM, operating AND gates G1, G2 connected to the data bus dbr of the reserve computer. In order to start the parallel synchronous working of the computers, an interrupt unit IU sends a signal to the executive computer, interrupting processing and selecting an instruction register which sends a "ready signal" to the interrupt unit, the ready signal producing via a decoder DEC a secondary start pulse ss which is applied to the start device SDe. Each start device SD comprises a first phase generator (shift register) PG1 stepped by clock pulses, and a second phase generator (cyclic counter) PG2 being four steps corresponding to the four phases of an instruction processing cycle. The secondary start pulse ss causes read-out of a start instruction from a register SIRe, the start instruction addressing a beginning instruction register BIR in the executive computer. The secondary start pulse ss passes to the start device SDr of the reserve computer via a delay device DE, and is further delayed a certain number of phases by a first phase generator PG1r having more stages than generator PG1e. In another embodiment (not shown) all the delay is obtained from the delay device DE, the generators PG1e, PGlr being identical. The second phase generator PG2r remains at zero until activated by a start pulse s from generator PG1r, and then reads out a start instruction from a register SIRr to select a beginning instruction register in the reserve computer. In Fig. 2 (not shown) each functional unit FU has a control memory CM recording its transfer state, allowing diagnosis of which functional unit in the reserve computer is faulty. In this embodiment the delay device DE is omitted, delay being obtained partly via a single first phase generator (shift register) (PG1) feeding the start devices SDe, SDr via different outputs, and partly by the start device SDr addressing so called "blind instruction registers" (BLR) in the reserve computer. Each blind instruction register contains an instruction to address another register, so that a delay of one processing cycle is obtained. A drift comparison device comprising an EXOR gate (EXORd) compares data on the data transferring channel DCH and on the data bus dbr of the reserve computer during those timing phases intended for reception of data by the reserve computer, and generates an alarm signal if these are unequal. This alarm signal is used in the above diagnosis. In Fig. 3 (not shown) the delay of the delay device is achieved via the data transferring channel DCH, in that a signal is sent from generator PG1e to the control memory CM of the channel DCH, which closes the channel and enables data and a start instruction to be transferred from the executive to the reserve computer. When the incoming start instruction from channel DCH is recognized to be the same as that stored in register SIRr, a comparison device (EXORs) sends a start signal to the first phase generator PGlr. The second phase generator PG2r is then started a certain number of phases (optimally adjustable) following this.