GB1478953A - Analogue to digital converter - Google Patents

Abstract

1478953 Analogue-to-digital conversion INTERNATIONAL BUSINESS MACHINES CORP 15 May 1975 [16 July 1974] 20492/75 Heading H3H In analogue-to-digital conversion a voltage V IN to be converted is initially stored on a capacitor 18 and the number of discrete charge subtractions required to reduce the voltage across the capacitor 18 to a predetermined threshold, 22, is counted, 42. In Fig. 2 a calibration routine alternates with conversion cycles. During calibration, a known reference voltage V REF is stored on capacitor 18 and repeatedly reduced, the difference in time between output from threshold detector 22 and counter 42 attaining a predetermined state N is detected at 28 and used to control the current sink 20 producing the charge subtractions. Control pulses for gates 10a, 10b, 30 and 44 are derived from the counter 42, which is continuously recycled. In a modification (not shown) a calibration routine does not precede energy A-to-D conversion cycle. Integrated circuit details of the threshold detector, current sink and filter are given, Fig. 4 (not shown). Switches 10a 10b are n channel enhancement MOS switches. Capacitor 18 may comprise 0À1 and 0À9 pF capacitors with switching for range changing. A F.E.T. may be provided for shorting the capacitor 18 during chip testing. A modified input circuit. Figs. 5 and 6 (not shown) includes a bipolar transistor (110) and a high gain negative feedback loop for providing a tare compensation for its forward base-emitter voltage drop.