GB1477881A - Data storage systems - Google Patents

Data storage systems

Info

Publication number
GB1477881A
GB1477881A GB3972474A GB3972474A GB1477881A GB 1477881 A GB1477881 A GB 1477881A GB 3972474 A GB3972474 A GB 3972474A GB 3972474 A GB3972474 A GB 3972474A GB 1477881 A GB1477881 A GB 1477881A
Authority
GB
United Kingdom
Prior art keywords
write
select
read
inputs
byte
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3972474A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1477881A publication Critical patent/GB1477881A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/04Addressing variable-length words or parts of words
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

1477881 Data store SIEMENS AG 12 Sept 1974 [25 Sept 1973] 39724/74 Heading G4C A data storage system includes a matrix array of byte storage assemblies SB11-SBki, each row including a number i of assemblies equal to the number of bytes in a word, and each assembly including a number of bit storage modules equal to the number of bits in a byte, an assembly select input CS, a write/read input S/L through which write and read operations are selected, and a number of address inputs (not shown) corresponding to the number of bits stored in each bit storage module, the address inputs to each assembly being connected to all the modules in that assembly and to a common address source; a word select AND gate VG1 for each row receiving a respective word select signal WI-Wk and feeding all the select inputs CS in the respective row; and a byte select AND gate VG2 for each column receiving a respective byte select signal BI-Bi and a common write/read select signal S/L* and feeding all the write/read inputs S/L in the respective column. The arrangement allows write and read operations to be performed in a selected byte or bytes of a selected word while requiring fewer AND gates than prior art arrangements (Fig. 1, not shown) in which each assembly receives a common write/read signal via column gates and in which the assembly select signals CS are produced by feeding each of the k word select signal to i AND gates each of which receives a respective one of the i byte select signals so as to produce an individual select signal CS for each assembly. A write operation into selected bytes of a selected word and a simultaneous read operation from the remaining bytes of the word are possible by arranging that, say, binary 1 signals at write/read inputs S/L produced by binary 1 signals on the appropriate byte select inputs B produce a write operation while binary O signals at write/read inputs S/L produced by binary O signals at the remaining byte select inputs B produce a read operation.
GB3972474A 1973-09-25 1974-09-12 Data storage systems Expired GB1477881A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732348196 DE2348196B2 (en) 1973-09-25 1973-09-25 CIRCUIT ARRANGEMENT AND PROCEDURE FOR BYTE SELECTION IN A SEMICONDUCTOR MEMORY

Publications (1)

Publication Number Publication Date
GB1477881A true GB1477881A (en) 1977-06-29

Family

ID=5893597

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3972474A Expired GB1477881A (en) 1973-09-25 1974-09-12 Data storage systems

Country Status (6)

Country Link
BE (1) BE820318A (en)
DE (1) DE2348196B2 (en)
FR (1) FR2245049B1 (en)
GB (1) GB1477881A (en)
IT (1) IT1022204B (en)
NL (1) NL7412597A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2146146A (en) * 1980-05-30 1985-04-11 Fairchild Camera Instr Co Microprocessor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2852985C2 (en) * 1978-12-07 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Method for controlling a memory, particularly in telephone switching systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2146146A (en) * 1980-05-30 1985-04-11 Fairchild Camera Instr Co Microprocessor

Also Published As

Publication number Publication date
DE2348196A1 (en) 1975-03-27
FR2245049A1 (en) 1975-04-18
FR2245049B1 (en) 1978-06-09
NL7412597A (en) 1975-03-27
BE820318A (en) 1975-03-25
IT1022204B (en) 1978-03-20
DE2348196B2 (en) 1977-08-04

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee