GB1476709A - Integrated master slave flipflop circuit - Google Patents

Integrated master slave flipflop circuit

Info

Publication number
GB1476709A
GB1476709A GB3608275A GB3608275A GB1476709A GB 1476709 A GB1476709 A GB 1476709A GB 3608275 A GB3608275 A GB 3608275A GB 3608275 A GB3608275 A GB 3608275A GB 1476709 A GB1476709 A GB 1476709A
Authority
GB
United Kingdom
Prior art keywords
clock
clock signals
master slave
sept
train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3608275A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1476709A publication Critical patent/GB1476709A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the master-slave type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Shift Register Type Memory (AREA)

Abstract

1476709 Transistor bi-stable circuits ITT INDUSTRIES Inc 2 Sept 1975 [5 Sept 1974] 36082/75 Heading H3T An integrated injection logic (I<SP>2</SP>L) masterslave flip-flop controlled by clock signals comprises a master cell M and a slave cell S each comprising I<SP>2</SP>L elements to the injectors of which are applied clock signals T 1 , T 2 . The clock pulses of the two clock signals are non- overlapping and the sum of the decay time of one clock pulse of one train, the rise time of the next clock pulse of the other train, and the spacing between these two pulses is smaller than the storage time of the transistors. A plurality of such stages may be used to form a shift register.
GB3608275A 1974-09-06 1975-09-02 Integrated master slave flipflop circuit Expired GB1476709A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2442773A DE2442773C3 (en) 1974-09-06 1974-09-06 Integrated master-slave flip-flop circuit

Publications (1)

Publication Number Publication Date
GB1476709A true GB1476709A (en) 1977-06-16

Family

ID=5925076

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3608275A Expired GB1476709A (en) 1974-09-06 1975-09-02 Integrated master slave flipflop circuit

Country Status (5)

Country Link
DE (1) DE2442773C3 (en)
FR (1) FR2284223A1 (en)
GB (1) GB1476709A (en)
IT (1) IT1042295B (en)
ZA (1) ZA755645B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2833594A1 (en) * 1977-08-02 1979-02-15 Texas Instruments Inc STORAGE CELL

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847092B2 (en) * 1976-12-14 1983-10-20 株式会社東芝 logic circuit
US4160173A (en) * 1976-12-14 1979-07-03 Tokyo Shibaura Electric Co., Ltd. Logic circuit with two pairs of cross-coupled nand/nor gates
WO1981000332A1 (en) * 1979-07-19 1981-02-05 Motorola Inc Bistable circuit and shift register using integrated injection logic
DE3637158A1 (en) * 1986-10-31 1988-08-11 Telefunken Electronic Gmbh Chained logic circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3655999A (en) * 1971-04-05 1972-04-11 Ibm Shift register
NL7107040A (en) * 1971-05-22 1972-11-24
GB1494481A (en) * 1973-12-21 1977-12-07 Mullard Ltd Electrical circuits comprising master/slave bistable arrangements

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2833594A1 (en) * 1977-08-02 1979-02-15 Texas Instruments Inc STORAGE CELL

Also Published As

Publication number Publication date
IT1042295B (en) 1980-01-30
FR2284223A1 (en) 1976-04-02
DE2442773B2 (en) 1978-04-27
DE2442773A1 (en) 1976-03-18
ZA755645B (en) 1976-08-25
DE2442773C3 (en) 1978-12-14
FR2284223B1 (en) 1982-07-23

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee