GB1472210A - Data transfer apparatus - Google Patents

Abstract

1472210 Skew correction; buffering INTERNATIONAL BUSINESS MACHINES CORP 27 Nov 1974 51355/74 Headings G4C and G4A Data transfer apparatus includes a plurality of data buffer units in each of which the stage of a shift register 26 from which read-out takes place is controlled by an up-down counter 28, which is stepped up by one every time a bit is written into shift register 26 and is stepped down by one every time a bit is read out of the shift register; the count in counter 28 thus represents the position in register 26 of the first which has been written into the register 26 but has not yet been read out by a circuit 17 which detects when all the shift registers 26 contain data. Each counter 28 has one more count state than there are shift register stages, all but a reference count state causing, via a decode circuit 29, a respective one of AND gates A1- A6 of circuit 27 to be enabled to pass the content of the respective shift register stage SR1- SR6 to utilization and control means 15. This apparatus may be used for buffering or in deskewing apparatus, the signals from each track of a magnetic tape 10 being fed to a respective shift register, controlled by a respective up-down counter to ensure synchronized readout of the signals from the different shift registers. The apparatus may be used in either of two modes; in the first mode signals are received as presented and output signals are supplied as available, whereas in the second mode output signals are supplied as requested by utilization and control means 15, and signals are received only when the shift registers 26 have room for them. Overrun or underrun is indicated by monitoring selected counts of the up-down counters 28.