GB1458834A - Electronic time keeping apparatus - Google Patents

Abstract

1458834 Electronic watches FAIRCHILD CAMERA & INSTRUMENT CORP 28 Dec 1973 [2 Jan 1973] 60023/73 Heading G3T [Also in Division H2] An electronic watch comprises means 12...18 for providing low voltage time signals, means 27 responsive to said low voltage time signals for converting the D.C. voltage from a battery 26 to a higher D.C. voltage and level converters 20, responsive to the higher D.C. voltage for increasing the magnitude of the low voltage time signals for application to a liquid crystal display D. As described, an oscillator 10, controlled by a crystal 12 operates at a frequency of 32, 768 Hz and feeds a divider 14 which produces pulses at 1 Hz, 32 Hz and 64 Hz for feeding a time keeping unit 16, Figs. 3 and 4 (not shown) from which a de-coder 18 provides appropriate low voltage minutes and hours signals which are increased in voltage by means of level converters 20 so as to be suitable for gating to the respective segments of a 7-segment liquid crystal display D. Gates 22 are operated by the 32 Hz time signal which is also fed to the common electrode 30, individual segments 24o ... 24i being displayed or not depending whether they are driven antiphase or in phase with the signal on the common electrode 30. (Figs. 3 and 4) relate to block diagrams to show how counters in the time keeping unit 16 can be manually reset to adjust the hours and minutes. Fig. 7 (not shown) relates to an integrated circuit using complementary metal oxide semiconductors (CMOS) for the level converters 20. D.C.-D.C. converters. Fig. 6 shows details of block 27 for converting the battery voltage VD (1.5V) to V D ' (15V). When a clockpulse is received by gate 80, CMOS transistor 50 is turned off and 51 turned on, turning on transistor 52 which passes current via inductor 53. At the end of the clockpulse, transistors 50...52 change state, so that the resulting high voltage across inductor 53 is rectified at 54 and charges capacitor 55. Automatic voltage control. A constant current source 41 is driven by the output of a JK flip-flop 87 so as to provide 1ms constant current pulses in resistor 42 at 4 Hz. The lower end of resistor 42 is connected to the output of the D.C.-D.C. converter at 57 so that the voltage at 45 will be indicative of the converter output. Terminal 45 is coupled to a sensing transistor 76 via a source follower 75 having a further CMOS transistor 72 as its source load. When the voltage at 57 reaches a predetermined value, transistor 76 is turned off and flip-flop 77 set by the next clockpulse from 87, so as to block NOR gate 80 and inhibit the D.C.-D.C. converter 44 until its output 57 has fallen to a further predetermined value. The output voltage at 57 is thus regulated by comparing it with the voltage pulses across resistor 42 applied by constant current sampling pulses. CMOS transistors 60..62 provide a bias voltage at terminal 63, slightly lower than the output voltage 57.