GB1447476A - Semiconductor circuit arrangements - Google Patents
Semiconductor circuit arrangementsInfo
- Publication number
- GB1447476A GB1447476A GB5488772A GB5488772A GB1447476A GB 1447476 A GB1447476 A GB 1447476A GB 5488772 A GB5488772 A GB 5488772A GB 5488772 A GB5488772 A GB 5488772A GB 1447476 A GB1447476 A GB 1447476A
- Authority
- GB
- United Kingdom
- Prior art keywords
- inverting
- semi
- control signal
- load
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
1447476 Semi-conductor logic inverter circuits PLESSEY CO Ltd 15 Nov 1973 [28 Nov 1972] 54887/72 Heading H3T In a circuit arrangement comprising a plurality of inverting stages (not shown) and a further inverting stage M 1 , M 2 , each including an inverting semi-conductor device M 1 and a load semi-conductor device M 2 , the further inverting stage includes an arrangement, e.g. e 1 , e 2 for degrading a logical level signal derived therefrom and a regulator arrangement A for applying a control signal to the load M 2 for varying its conductance in a sense to counteract said degradation and the control signal is also applied to load devices of other inverting stages for logic level correction. As shown, the voltages e 1 , e 2 or an alternative resistor circuit simulates the degradation in the high level which would be encountered in the above plurality of inverting stages. The regulator A is a differential amplifier which compares the degraded logic level output with the high voltage level for providing the control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5488772A GB1447476A (en) | 1972-11-28 | 1972-11-28 | Semiconductor circuit arrangements |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5488772A GB1447476A (en) | 1972-11-28 | 1972-11-28 | Semiconductor circuit arrangements |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1447476A true GB1447476A (en) | 1976-08-25 |
Family
ID=10472363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5488772A Expired GB1447476A (en) | 1972-11-28 | 1972-11-28 | Semiconductor circuit arrangements |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1447476A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0110701A2 (en) * | 1982-11-27 | 1984-06-13 | Hitachi, Ltd. | Input buffer circuit |
WO1987004027A1 (en) * | 1985-12-20 | 1987-07-02 | Fujitsu Limited | A slice amplifier using fet's |
-
1972
- 1972-11-28 GB GB5488772A patent/GB1447476A/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0110701A2 (en) * | 1982-11-27 | 1984-06-13 | Hitachi, Ltd. | Input buffer circuit |
EP0110701A3 (en) * | 1982-11-27 | 1985-01-09 | Hitachi, Ltd. | Input buffer circuit |
WO1987004027A1 (en) * | 1985-12-20 | 1987-07-02 | Fujitsu Limited | A slice amplifier using fet's |
AU576979B2 (en) * | 1985-12-20 | 1988-09-08 | Fujitsu Limited | A slice amplifier using fet's |
WO1989000359A1 (en) * | 1985-12-20 | 1989-01-12 | Fujitsu Limited | A slice amplifier using fet's |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PE20 | Patent expired after termination of 20 years |
Effective date: 19931114 |