GB1444791A - - Google Patents

Abstract

1444791 Processing control data BABCOCK & WILCOX CO 20 July 1973 [24 July 1972] 34769/73 Heading G3N In programme processing apparatus suitable for use with a machine tool { e.g. lathe } , or the like, each data group of the programme comprises a left hand or "Boolean" word with an address identifying it as "Boolean" and directing it via units 21, 23, 25 to interrogate, sequentially, term-by-term the status of specific machine functions {e.g. lathe motor "on", or "off" } defined by bits of the word to provide a cumulative machine status evaluation, the left hand word being followed by a programming instruction instruction cypher {e.g. "=" or "halt", or "jumps" } passing via unit 20 to unit 36 controlling the processing of a right hand word of the data group delivering execution instructions to specific machine functions, via units 21, 23, 25. Deserializer 32, see also Fig. 2, (not shown), receiving signals representing the status on line 31 updates the actual status of the machine functions by combining the received status signals with the previous according to the rules of Boolean algebra, Boolean symbols "(",")" being incorporated into data words, the detection of a "(" symbol causing storage of the thus far accumulated result, termby-term evaluation continuing until a ")" is detected, whence the result of the continuing evaluation, and the stored value are combined. The deserializer operates, in response to an evaluation to decide whether, or not, any actuation of machine members is required in response. The processing logic may be converted from positive to negative by preceding a data word with a sign "-", passed via line 18 to the deserializer. Unit 23 comprises a group of logic gates (not shown), one gate being unique to a machine function, unit 25 inverting the voltage level of signals to and from machine 10 to and from higher voltage for immunity against interference. The next word in a program is called up under control of counter 34, from a specific location in memory 12, to buffer memory 16, the Boolean combination in unit 32 taking place under control of four timed pulses from generator 13. Each data word includes a parity bit.