GB1441661A - Data processing system - Google Patents

Data processing system

Info

Publication number
GB1441661A
GB1441661A GB4077573A GB4077573A GB1441661A GB 1441661 A GB1441661 A GB 1441661A GB 4077573 A GB4077573 A GB 4077573A GB 4077573 A GB4077573 A GB 4077573A GB 1441661 A GB1441661 A GB 1441661A
Authority
GB
United Kingdom
Prior art keywords
address
interrupt signals
control word
field
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4077573A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19722247735 external-priority patent/DE2247735C3/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1441661A publication Critical patent/GB1441661A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825Interrupt from clock, e.g. time of day

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Multi Processors (AREA)
  • Digital Computer Display Output (AREA)
  • Programmable Controllers (AREA)

Abstract

1441661 Data processing system INTERNATIONAL BUSINESS MACHINES CORP 30 Aug 1973 [29 Sept 1972] 40775/73 Heading G4A A data processing system includes a store containing a number of sequence control words each including two address fields, the first of which accesses a corresponding stored program routine and the second of which accesses a further sequence control word, and means, responsive to interrupt signals, to access a further sequence control word in response to the second address field unchanged when no interrupt signals are active and in reponse to a predetermined logical combination of the second address field and the interrupt signals when one or more of the interrupt signals are active. Each sequence control word contains a field (the left hand field in Fig. 1) by means of which a corrresponding microprogram routine is accessed. The right hand field contains an address, in the form of two four bit hexadecimal characters, which is used to access the next control word. Four interrupt leads are provided giving sixteen combinations and the interrupt signals are OR-ed with bits of the right hand address character. The resulting address is used to access the next control word by doubling and adding one, the address of each control word being shown above the corresponding word in Fig. 1. The arrangement may be used in time sharing systems where each machine cycle is divided, in this case, into sixteen, the particular sequence of control words depending on the state of the interrupt signals. The programs selected by the control words may relate to I/O devices sharing a common program store. The interrupt signals may be generated within the system or externally, e.g. by I/O devices requiring service.
GB4077573A 1972-09-29 1973-08-30 Data processing system Expired GB1441661A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19722247735 DE2247735C3 (en) 1972-09-29 Circuit arrangement for the dynamic allocation of computing time

Publications (1)

Publication Number Publication Date
GB1441661A true GB1441661A (en) 1976-07-07

Family

ID=5857708

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4077573A Expired GB1441661A (en) 1972-09-29 1973-08-30 Data processing system

Country Status (8)

Country Link
JP (1) JPS5746094B2 (en)
CH (1) CH556062A (en)
ES (1) ES419172A1 (en)
FR (1) FR2201782A5 (en)
GB (1) GB1441661A (en)
IT (1) IT993602B (en)
NL (1) NL7313230A (en)
SE (1) SE387453B (en)

Also Published As

Publication number Publication date
JPS5746094B2 (en) 1982-10-01
IT993602B (en) 1975-09-30
CH556062A (en) 1974-11-15
FR2201782A5 (en) 1974-04-26
DE2247735B2 (en) 1975-06-12
DE2247735A1 (en) 1974-04-18
ES419172A1 (en) 1976-04-16
SE387453B (en) 1976-09-06
NL7313230A (en) 1974-04-02
JPS4973047A (en) 1974-07-15

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19920830