GB1435929A - Coded data enhancer systems - Google Patents

Abstract

1435929 Inserting parity bits BELL & HOWELL CO 6 Aug 1973 [4 Aug 1972] 37152/73 Heading G4C Apparatus for inserting parity bits into a stream of n bit binary words at terminal 12 (Fig. 1) each associated with n clock pulses from a source 48 includes circuitry 87 (Fig. 2) for deriving for each word a parity bit and circuitry for deriving from n clock pulses from the clock 48 n+ 1 clock pulses to allow accommodation of the parity bits into the stream. As described 7-bit NRZ words are clocked into a first shift register 36. Parity generator 87 comprising exclusive NOR gates 88, exclusive OR gates 89, AND gates 92 and NOR gates 93 derives a signal at terminal 96 if the shift register contains an even number of "1" bits (check after amendment). The shift register 36 is connected via seven gates 51 to a second eight-bit shift register 37, the output from the parity generator being fed via an eighth gate 51 to the first stage of the register 37. The clock pulses from clock 48 of frequency f are fed together with feedback signals from a counter 161 (Fig. 3) to a phase detector 101 connected via an amplifier stage 102 to a voltage controlled oscillator 103 deriving at terminal 147 a clock signal having a frequency 8f. This signal is fed to two counters, a divide-by-7 counter 167 and the divide-by-8 counter 161. The output signal 81 of counter 167 which is consequently a frequency 8/ 7 f is used to read-out the second shift register 37. Parallel transfer of data from the first shift register to the second occurs when a count of four in counter 167 coincides with a count of seven in counter 161, this condition being detected by a NAND gate 155.