GB1432227A - Information-processing systems - Google Patents
Information-processing systemsInfo
- Publication number
- GB1432227A GB1432227A GB1751673A GB1751673A GB1432227A GB 1432227 A GB1432227 A GB 1432227A GB 1751673 A GB1751673 A GB 1751673A GB 1751673 A GB1751673 A GB 1751673A GB 1432227 A GB1432227 A GB 1432227A
- Authority
- GB
- United Kingdom
- Prior art keywords
- register
- central unit
- control
- stable
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010365 information processing Effects 0.000 title 1
- 230000002093 peripheral effect Effects 0.000 abstract 4
- 230000006870 function Effects 0.000 abstract 2
- 244000309464 bull Species 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
- G06F9/267—Microinstruction selection based on results of processing by instruction selection on output of storage
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Storage Device Security (AREA)
- Communication Control (AREA)
Abstract
1432227 Digital data processing COMPAGNIE HONEYWELL BULL 11 April 1973 [18 April 1972] 17516/73 Heading G4A Each of a plurality of control units, one of which 2a is shown in Fig. 1 control communication between a central unit 1 and an associated group of peripheral units. The central unit 1 comprises a main store 11 and read only store 12, with a section 122 assigned to calculation tables and a section 121 assigned to micro programmes, linked to a processor 13. The control unit comprises a read only store 21, register section 22 and switching section 23. Memory 21 is addressed from a register (S, Fig. 2, not shown) and read out to further registers (N, F) one of which is selected to read an address and micro-function in accordance with the state of a bi-stable (bs), read out occurring at a clock pulse (XTLEV) and addressing at a clock pulse (XTAD). The bi-stable is controlled by two signals (VAR, VAR) to select the next micro function in accordance with the current value of the signals and the output of a comparator (CL, Fig. 4, not shown) which compares data in a plurality of registers or fixed data with data in a selected register (L, Fig. 7, not shown). To communicate between the central unit 1 and a peripheral disc storage unit the central unit transmits five control words. A service signal (DIR, Fig. 3, not shown) is received by the central unit when selection of the control unit is assumed to have been made which causes a control word fed to a register (U) to be decoded by a decoder (DD) to derive a signal (sel 1 ...) to select one of the peripheral units and a signal (sp) to set a bi stable (bm, Fig. 2, not shown) to derive a start signal for a micro programme held in the memory 21. A micro-function is consequently generated which sets bi-stable (bk, Fig. 4, not shown) to deliver a signal to the central unit. The central unit responds with a control word which is fed to a register (P, Fig. 7, not shown), bi-stable (bk, Fig. 4, not shown) being simultaneously reset. The next microfunction (TPL) results in the contents of the register (P) being transferred to the register (L), the bi-stable (bk) being again set to transmit a signal to the central unit for admission of the next control word. Successive control words are entered into registers (A, B, C) and represent the numbers of the sector, head and track to be selected and indicate that a positioning function is needed. The last address processed is held in a register associated with the peripheral unit, positioning being effected by comparison between the old and new addresses. The last control word specifies a read/write operation, data being received from the disc serially. A test operation of the control unit may be effected by transferring from the central unit the appropriate five control words.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7213525A FR2181123A5 (en) | 1972-04-18 | 1972-04-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1432227A true GB1432227A (en) | 1976-04-14 |
Family
ID=9097027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1751673A Expired GB1432227A (en) | 1972-04-18 | 1973-04-11 | Information-processing systems |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS4918434A (en) |
DE (1) | DE2319756A1 (en) |
FR (1) | FR2181123A5 (en) |
GB (1) | GB1432227A (en) |
IT (2) | IT983931B (en) |
NL (1) | NL7304953A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3999163A (en) * | 1974-01-10 | 1976-12-21 | Digital Equipment Corporation | Secondary storage facility for data processing systems |
FR2273317B1 (en) * | 1974-05-28 | 1976-10-15 | Philips Electrologica | |
FR2307407A1 (en) * | 1975-04-09 | 1976-11-05 | Singer Co | Data interface module for connecting subsystems - couples subsystems to common transmission line by coding outgoing and decoding incoming signals |
US4028668A (en) * | 1975-12-22 | 1977-06-07 | Honeywell Information Systems, Inc. | Apparatus for selectively addressing sections and locations in a device controller's memory |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3623022A (en) * | 1969-12-29 | 1971-11-23 | Ibm | Multiplexing system for interleaving operations of a processing unit |
US3654617A (en) * | 1970-10-01 | 1972-04-04 | Ibm | Microprogrammable i/o controller |
-
1972
- 1972-04-18 FR FR7213525A patent/FR2181123A5/fr not_active Expired
-
1973
- 1973-04-10 NL NL7304953A patent/NL7304953A/xx not_active Application Discontinuation
- 1973-04-11 GB GB1751673A patent/GB1432227A/en not_active Expired
- 1973-04-17 IT IT2309773A patent/IT983931B/en active
- 1973-04-18 DE DE19732319756 patent/DE2319756A1/en not_active Ceased
- 1973-04-18 IT IT6812173A patent/IT984479B/en active
- 1973-04-18 JP JP4330673A patent/JPS4918434A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPS4918434A (en) | 1974-02-18 |
IT983931B (en) | 1974-11-11 |
DE2319756A1 (en) | 1973-10-31 |
NL7304953A (en) | 1973-10-22 |
FR2181123A5 (en) | 1973-11-30 |
IT984479B (en) | 1974-11-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |