GB1431205A - Monolithic semiconductor circuit arrangement - Google Patents

Abstract

1431205 Stabilizing bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 30 May 1973 [30 June 1972] 25825/73 Heading H3T A FET storage circuit comprises crosscoupled field effect transistors T 1 , T 2 storing binary information and transistors T 3 , T 4 reading out and writing; the latter being held non-conductive for inoperation over word line WL whereby T 1 and T 2 are separated from bit lines B0 B1 and fed from V L over FET's T 5 and T 6 , whose gates are linked to a circuit supplying a potential dependent on the threshold of the FET's. For read out or write a signal on word line WL drives T 3 , T 4 conductive, so that for read the potentials at points 1, 2 are applied to bit lines B0, B1 and to the read amplifiers; while for write the signals are fed into storage transistors T 1 , T 2 over T 3 , T 4 . Current in T 5 , T 6 must compensate the leakage in T 1 , T 2 respectively and for T 1 conducting and T 2 blocked, the potential of point 2 must be held by current in T 6 compensating leakage current of blocked T 2 , while T 5 , T 6 must have high resistance. Thus the difference between the gate to source voltage and the threshold voltage must be as low as possible, which is achieved by applying to the gate electrodes a potential dependent on the respective threshold voltages of the FET's. The FET's T 7 , T 8 , T 9 , T 10 , T 11 simulate the operation of the connected storage cells with T 8 corresponding to T 6 when T 1 is conducting and T 9 corresponding to transistor T 1 while T 7 determines the current in a chain interconnecting potential V H and the potential V R ; derived from voltage division by FET's T 10 , T 11 across potentials V L , V H . The potential V G at 3 = V R + V T9 + V T8 corresponding to threshold voltages of T 8 , T 9 is applied to the gates of T 5 , T 6 . In a modification (Fig. 2) Vg is developed and fed to the storage cells over an interface stage comprising a further series of FET's; yet another FET being connected into the chain of T 7 , T 8 , T 9 with the interface FET's in series between V H and earth and their gates energized from the junctions of T 7 and the additional FET and from T 8 , T 9 respectively to develop potential V G at the junction of the decoupling FET's. Mathematics is given. A further modification (Fig. 3, not shown) derives additional compensation by utilizing another FET stage and also feedback stages.