GB1425067A - Telemetering synchronization and demodulation apparatus includin an ambiguity eliminating device - Google Patents

Telemetering synchronization and demodulation apparatus includin an ambiguity eliminating device

Info

Publication number
GB1425067A
GB1425067A GB2006973A GB2006973A GB1425067A GB 1425067 A GB1425067 A GB 1425067A GB 2006973 A GB2006973 A GB 2006973A GB 2006973 A GB2006973 A GB 2006973A GB 1425067 A GB1425067 A GB 1425067A
Authority
GB
United Kingdom
Prior art keywords
phase
output
multiplier
circuit
nrz
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2006973A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National dEtudes Spatiales CNES
Original Assignee
Centre National dEtudes Spatiales CNES
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR7215408A external-priority patent/FR2182632B1/fr
Priority claimed from FR7216867A external-priority patent/FR2194091B1/fr
Application filed by Centre National dEtudes Spatiales CNES filed Critical Centre National dEtudes Spatiales CNES
Publication of GB1425067A publication Critical patent/GB1425067A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1425067 Digital di-phase receivers CENTRE NATIONAL D'ETUDES SPATIALES 27 April 1973 [28 April 1972 10 May 1972] 20069/73 Heading H4P A synchronizing and demodulating receiver circuit for a di-phase modulated carrier, gives a NRZ output, fed through a delay to one stage or more than one cascaded stages, each including a generator deriving clock pulses of frequency F by multiplication of NRZ output signal with the same signal delayed, the arrangement incorporating a phase locked loop, with a NRZ detector at its output. The delay may be obtained in a shift register (21) (Fig. 4, not shown) fed through amplifier (23) and 2 level limiter (24) providing a rectangular output, stepped at double frequency. The multiplier may be in the form of an exclusive OR (22) logic circuit (A+B=mod 2 sum) feeding into a phase locked loop including exclusive OR 26, amplifier (27) filter (28) and operational amplifier (29) receiving a reference voltage and oscillator (20) feeding a tapped dividing chain 19; output is taken from terminal B. The arrangement comprises cascaded chains I-III each comprising an amplifier 2, generator 3 and phase loop 4. As there are two transitions per period of the carrier frequency FO modulated by di-phase, generator 3I and loop 4I operate at 2FO which is halved at 5 to feed multiplier 6 which may be alternatively of analogue type. The modulated wave is also applied to the other input of multiplier 6 which produces a di-phase output to circuit II operating at 2F (twice bit rate) which is halved at 7 before being supplied to multiplier 8 which produces NRZ signals to circuit III at bit rate F; the main function of this circuit is to eliminate ambiguity. To reduce the noise band at the input, band pass filters 9, 10 switched by 11a, 11b are provided for each carrier; switches 12a-12c provide for alternative bit rates. It is stated that the threshold of the loop is much lower than the threshold of a system detecting transistions in a noisy message hence a greater amount of noise may be tolerated.
GB2006973A 1972-04-28 1973-04-27 Telemetering synchronization and demodulation apparatus includin an ambiguity eliminating device Expired GB1425067A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR7215408A FR2182632B1 (en) 1972-04-28 1972-04-28
FR7216867A FR2194091B1 (en) 1972-05-10 1972-05-10

Publications (1)

Publication Number Publication Date
GB1425067A true GB1425067A (en) 1976-02-18

Family

ID=26217063

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2006973A Expired GB1425067A (en) 1972-04-28 1973-04-27 Telemetering synchronization and demodulation apparatus includin an ambiguity eliminating device

Country Status (2)

Country Link
DE (1) DE2321637B2 (en)
GB (1) GB1425067A (en)

Also Published As

Publication number Publication date
DE2321637B2 (en) 1976-04-22
DE2321637A1 (en) 1973-11-15

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee